JPH0750453B2 - I / O control system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control system, and more particularly to an input / output control method for connecting a high speed input / output device to a low speed central processing subsystem.

[0002]

2. Description of the Related Art Conventionally, when a data processing system is constructed, it is usually constructed so as to take into consideration the balance between the performance of an arithmetic processing system and the performance of an input / output system. For example, as shown in FIG. 2, when the central processing unit 1, the main storage devices 2 and 3, and the input / output processing device 11 are connected to the memory bus 100, the input / output device (not shown) is input / output. It is connected to the input / output processing device 11 via the control devices 12a to 12c.

In this case, a method of performing DMA (Direct Memory Access) between the main storage device 3 and the input / output device is generally used. Here, the channel program for performing the DMA is stored in the storage area 3a of the main storage device 3,
The data is stored in the data area 3b, and the control data for performing the DMA is stored in the storage area 3c.

However, when the performance of the central processing unit 1 is low, the bus transfer capability of the memory bus 100 connecting the devices including the central processing unit 1 is also low, so that the input / output device and the main memory faster than the bus transfer capability. DMA with the device 3 cannot be performed. For example, the bus transfer capacity is 4MB / S
It is impossible to connect a semiconductor disk device having a transfer capacity of 6 MB / S and a semiconductor disk controller to the above system.

That is, although the performance of the arithmetic processing system is moderate, the performance of the arithmetic processing system is desired when a high-speed and large-capacity input / output device (for example, a magnetic disk device or a semiconductor disk device) is to be connected, or from various conditions. Even in a data processing system (for example, a development evaluation system that uses an emulator as a central processing unit) in which the speed cannot be increased, there are cases in which the latest high-speed input / output device is desired to be connected.

In such a case, in the conventional technique, there is a method of improving the performance of the memory bus 100 by using a central processing unit having a high arithmetic processing performance in preparation for waste. Further, a large-capacity buffer memory is provided between the input / output device and the main storage device 3, and DM between the buffer memory and the input / output device is provided.
A, there is also a method of performing processing in two stages, such as DMA between the buffer memory and the main storage device 3. Alternatively, there is a method of connecting an input / output device having low performance according to the performance of the arithmetic processing system.

Techniques for improving the efficiency of data transfer between devices having different processing performances by using the above-mentioned large capacity buffer memory include the technique disclosed in Japanese Patent Publication No. 61-34181 and Japanese Patent Laid-Open No. 62-43745. The technique disclosed in Japanese Laid-Open Patent Publication No. 1-155457 is known.

[0008]

The above-mentioned conventional technique has the following problems. In other words, if the performance of the bus is improved by using a central processing unit with high arithmetic processing performance, the price and size of the entire system will increase.
The entire system can hardly enjoy the merit of speeding up the central processing unit.

When a large-capacity buffer memory is provided between the input / output device and the main storage device to improve the processing performance, the hardware is increased and the control becomes complicated, and the DMA is also added.
Even if the performance is satisfactory, the overhead of the input / output processing device (command chain processing, etc.) accompanying the DMA is not improved. As a result, there is a problem that command overruns and data overruns frequently occur in a magnetic disk device, etc., where command processing time has a performance limitation, and it is practically unusable.

Further, when the input / output devices are selected and connected according to the performance of the central processing unit, the system configuration is greatly restricted, and there is a problem that the essential devices cannot be connected depending on the system. .

Therefore, an object of the present invention is to provide an input / output control system capable of connecting a high-speed input / output device exceeding the performance of a memory bus to a low-speed / inexpensive processor system without changing any software. It is in.

[0012]

An input / output control system according to the present invention comprises a central processing unit, an input / output processing unit, and a plurality of input / output control units connected to the input / output processing unit.
An input / output control system for a data processing system including a plurality of input / output devices connected to each of the plurality of input / output control devices, and a main storage device, wherein the central processing device and the main storage device are connected. A low-speed common bus, high-speed interface means for connecting the input / output processing device and the main storage device, and a data transfer between the main storage device and the input / output device provided in the central processing unit. A means for writing a channel program to be controlled into the main storage device; a means provided in the central processing unit for instructing the input / output processing device to execute the channel program written in the main storage device; Means for reading and executing the channel program written in the main memory in response to an instruction from the central processing unit, the input / output processing unit; It arranged in the processing apparatus, and means for notifying the central processing unit that the data transfer between the main storage device and the output device by execution of the channel program is terminated.

[0013]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the central processing unit 1 is 1 μs
It is a synchronous processor that operates with a clock of (10 ⁻⁶ seconds). The main storage devices 2 and 3 each have a capacity of 4 MB, and the main storage device 2 has a storage capacity of "000000" to "3FFF."
The FF 'address (the inside of the ″ is a hexadecimal number) is allocated to the main storage device 3 from the address “400000” to the address “7FFFFF”.

The allocation of addresses to the main storage devices 2 and 3 is determined by setting switches in the devices. Further, the main storage devices 2 and 3 each have a 4-bank structure, and are capable of 4-way interleaving.

The above-mentioned central processing unit 1 and main storage unit 2,
3 are connected to each other by a memory bus 100.
The memory bus 100 has a 22-bit address bus and 32
Bit data bus (read and write are independent)
And a control signal line. Also, memory bus 1
00 operates with a clock synchronized with the central processing unit 1, and 4
It has MB / S bus performance.

When the central processing unit 1 attempts to access the main memory units 2 and 3, it outputs a memory address to the address bus (if the access is a write access, it also outputs the write data to the write data bus) and performs necessary control. Signal line (eg request line, command line, light mask line)
Drive.

The main memories 2 and 3 monitor the address on the address bus in the machine cycle in which the request line is driven, and check whether or not the address is the address of the own device. When the access is a write access, if the address on the address bus is the address of the own device, the main storage devices 2 and 3 fetch the data of the write data bus and write the data to the position designated by the address.

When the access is a read access, and the address on the address bus is the address of the own device, the main memory devices 2 and 3 read continuous 4-byte data from the position designated by the address. Drive read data bus. Further, the main memory devices 2 and 3 drive control signal lines (reply signal line and error signal line) and respond to the central processing unit 1 to complete one access.

Input / output control devices 5a-5 are provided under the input / output processing device 4 by standardized I / O interfaces.
c is connected. The input / output devices connected under the input / output control devices 5a to 5c include both high-speed devices such as magnetic disks and semiconductor disks, and low-speed devices such as magnetic tape devices and consoles. The transfer rate is 4.5-9MB / S for disk devices and 4 for low-speed devices.
It is about 00 to 1250 KB / S.

In FIG. 1, magnetic disk devices 6a to 6d are connected under the input / output control device 5a, magnetic tape devices 7a to 7d are connected under the input / output control device 5b, and the input / output control device 5c is connected. A display device 8a, an input device 8b such as a console, a printer 9, and a floppy disk 10 are connected under it.

Since the input / output processing unit 4 controls the DMA with the high-speed input / output unit, the input / output processing unit 4 is faster than the memory bus 100.
It operates with a clock of 0 ns. A DMA data bus (not shown) inside the input / output processing device 4 has a width of 4 bytes, and the transfer capability of the input / output processing device 4 is 80 MB / S.

Further, the input / output processing device 4 is connected to the main storage device 3 by a high speed interface 101.
The interface 101 operates in 50 ns synchronized with the clock of the input / output processing device 4. The clock of the input / output processing device 4 is 50 ns and the clock of the memory bus 100 is 1 μm.
s is an asynchronous clock signal. Further, the main storage device 3 is configured to send data at a timing synchronized with the memory bus 100 or the interface 101, respectively.

Further, the input / output processing unit 4 is the memory bus 1
It is connected to the central processing unit 1 by a start instruction signal line 102 other than 00 and an end interrupt signal line 103. The activation instruction signal line 102 is a signal line for instructing activation of the channel program from the central processing unit 1 to the input / output processing unit 4, and the end interrupt signal line 103 indicates that the execution of the channel program is completed. This is a signal line for notifying the central processing unit 1 from. Both the start instruction signal line 102 and the end interrupt signal line 103 are referenced by the processor of each device after being synchronized with the internal clock in the receiving device.

The operation of the embodiment of the present invention will be described with reference to FIG. When the OS (operating system) running on the central processing unit 1 receives a read request on the magnetic disk from the user program, it performs the following operation.

First, the OS running on the central processing unit 1 secures the data area 3b for storing the read data from the magnetic disk on the main storage device 3, and initializes the data area 3b. Since this operation is performed on the virtual memory, the control data (actually the address conversion table and the page management table) for associating the logical address on the virtual memory with the physical address on the real memory is also stored in the storage area of the main memory 3 at the same time. Made on 3c. After this, the OS creates a channel program in the storage area 3a of the main storage device 3.

The channel program created in the storage area 3a is a chain of a 16-byte header part and an 8-byte channel command word. The header portion of the channel program includes a channel number designating the magnetic disk devices 6a to 6d, and the channel command word includes a command, a flag, an address of the data area 3b, and a data count.

Here, the command sequence is set file mask, seek cylinder, seek RPS, search ID, and read data. Further, the data address is indicated by a logical address which is an address on the virtual memory.

A 16-byte communication area is defined as a fixed address on the main memory 3 between the central processing unit 1 and the input / output processing unit 4. When the above operation is completed, the central processing unit 1 writes the logical address indicating the beginning of the channel program and the address information indicating the storage location of the control data in the communication area on the main memory 3. After that, the central processing unit 1 activates the activation instruction signal line 102 and instructs the input / output processing unit 4 to start the channel program.

A processor (not shown) of the input / output processing unit 4 is controlled by a microprogram, and the microprogram is always in the idle state and the activation instruction signal line 10 is always present.
2 is being monitored. When the microprogram recognizes activation of the start instruction signal line 102, the magnetic disk device 6
A device number (logical channel number) corresponding to a to 6d is added to the queue. Here, the queue is created in the main storage device 3 and managed by the microprogram of the input / output processing device 4.

The microprogram adds the device number to the queue and then designates the designated magnetic disk device 6a-6d.
In order to notify that there is a channel program waiting for the execution start, the start wait signal line defined on the I / O interface is activated.

The input / output control device 5a, to which the magnetic disk devices 6a to 6d are connected under the control, responds to the activation of the start wait signal line and instructs the input / output processing device 4 to start the execution of the channel program. Is sent. When the input / output processing device 4 receives the code, the magnetic disk device 6
I / O controller 5a has a total of 9 bytes including 1 byte for the device number that specifies a to 6d and 8 bytes for the first channel command.
Send to. At this time, the input / output processing device 4 removes the corresponding magnetic disk devices 6a to 6d from the queue and displays the status during execution of the channel program.

When the input / output controller 5a receives the device number and the channel command word, it executes the command of the channel command word to the designated magnetic disk devices 6a-6d. If there is a command chain, the I / O controller 5a requests the I / O processor 4 for the next channel command word.

The input / output processing unit 4 sends the next channel command word to the input / output control unit 5a in response to a request from the input / output control unit 5a. The input / output control device 5a decodes and executes the channel command word received from the input / output processing device 4.

If the channel command word indicates data transfer (DMA), the I / O processor 4 prepares for data transfer after sending the command. At this time, since the address of the data area 3b is described by the logical address in the channel command word, the input / output processing device 4 refers to the control data stored in the storage area 3c of the main storage device 3 and sets it in the channel command word. The address described by the logical address is converted into the physical address on the main storage device 3.

The above address conversion processing and data transfer preparation are performed while accessing the main memory device 3, but the main memory device 3 and the input / output processing device 4 are connected by a high-speed interface 101 different from the memory bus 100. Since it is possible to perform high-speed access, the overhead does not exceed the time limit.

When the input / output control device 5a recognizes that the received command requires data transfer, it starts data transfer instead of command chain request. When the command is a read data command, the input / output control device 5a reads data from the magnetic disk devices 6a to 6d and sends the data to the input / output processing device 4 in 1-byte units.

In the input / output processing device 4, the input / output control device 5a
The 1-byte unit data from the input / output control device 5a is received by a data buffer (not shown) connected to the I / O interface. When 4 bytes of the data are stored in the data buffer, the input / output processing device 4 writes the data in the data area 3b of the main storage device 3.

The input / output processing unit 4 attempts to continue the above operation for the count indicated by the channel command word. The input / output processing device 4 ends the data transfer when the count data is written to the main storage device 3 or the data on the magnetic disk is exhausted. Further, when the command chain continues, the I / O controller 5a requests the I / O processor 4 to fetch the channel command word.

When the above operation is repeatedly executed and the execution of the channel command word having the command chain flag "0" is completed, the execution of the channel program is completed.
When the input / output control device 5a completes the execution of the channel program, it sends to the input / output processing device 4 a code 1 byte, a device number 1 byte, and a status 3 byte, which signal the end.

When the input / output processing device 4 receives the end notification from the input / output control device 5a, it creates an end report message including status 3 bytes in the communication area on the main memory 3 and activates the end interrupt signal line 103. Then, the central processing unit 1 is interrupted.

In response to the interrupt from the input / output processing unit 4, the central processing unit 1 fetches the end report message from the communication area on the main storage unit 3 and outputs the end report message.
Report to S. The OS notifies the I / O end to the user program requesting the data reading. Through the above processing, a series of input / output operations are completed and the user program is restarted.

The input / output processing device 4 frequently accesses the main storage device 3 while executing the above-mentioned channel program. However, since the main memory device 3 and the input / output processing device 4 have high performance in synchronization with the clock 50 ns of the input / output processing device 4, the performance does not deteriorate when the main memory device 3 is accessed. .

On the other hand, when the input / output processing device 4 is directly connected to the low-speed memory bus 100 to access the main memory device 3, a performance of 4 MB / S or more, which is the upper limit performance of the memory bus 100, is required. Magnetic disk device 6a having
~ 6d cannot be connected. Further, in that case, since the access time of the memory bus 100 is long, the overhead related to the command chain processing is significantly increased, and the command overrun (magnetic disk devices 6a to 6d) is increased.
One rotation loss occurs because the command processing is not completed on the gap.

As described above, the main memory 3 connected to the central processing unit 1 via the low-speed memory bus 100 is connected to the input / output processing unit 4 by the high-speed interface 101, and the input / output processing unit 4 is connected to the memory bus. By connecting the start instruction signal line 102 and the end interrupt signal line 103 other than 100 to the central processing unit 1, the channel program written in the main storage device 3 by the central processing unit 1 is input / output processing unit 4
By executing the above method, an input / output device having a performance faster than the data transfer capacity of the memory bus 100 can be connected to the present system. Therefore, it is possible to connect a high-speed input / output device exceeding the performance of the memory bus to a low-speed / inexpensive processor system without making any changes to the software such as the OS.

[0046]

As described above, according to the present invention, the main storage unit and the input / output processing unit, which are connected to the central processing unit by the low-speed common bus, are connected by the high-speed interface, and the central processing unit is connected. The data transfer between the main storage device and the input / output device is completed by the signal line for instructing the input / output processing device to execute the channel program written between the output processing device and the main storage device and the execution of the channel program. By connecting with a signal line that informs the central processing unit that it has done so, it is possible to connect a high-speed input / output device that exceeds the performance of the memory bus to a low-speed / cheap processor system without making any changes to the software. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Central Processing Unit 2, 3 Main Storage Device 3a Channel Program Storage Area 3b Data Area 3c Control Data Storage Area 4 Input / Output Processing Device 5a-5c Input / Output Control Device 6a-6d Magnetic Disk Device 100 Memory Bus 101 Interface 102 Startup Instruction signal line 103 End interrupt signal line

Claims (2)

[Claims] 1. A central processing unit, an input / output processing unit, a plurality of input / output control units connected to the input / output processing unit, and a plurality of input / output units connected to each of the plurality of input / output control units. An input / output control system for a data processing system including: a main storage device; and a low-speed common bus connecting the central processing device and the main storage device, the input / output processing device, and the main storage device. A high-speed interface means for connecting to the central processing unit, means for writing a channel program, which is provided in the central processing unit, for controlling data transfer between the main storage device and the input / output device to the main storage device, and the central processing unit. Means for instructing the input / output processing device to execute the channel program written in the main storage device, and means for providing the input / output processing device with the central processing unit. Means for reading and executing the channel program written in the main storage device in response to the instruction, and the main storage device and the input / output device provided in the input / output processing device for executing the channel program. And a means for notifying the central processing unit that the data transfer with the device has been completed. 2. Means for synchronizing an instruction from the central processing unit with an internal clock provided in the input / output processing unit, and an internal clock for notifying from the input / output processing unit provided in the central processing unit. The input / output control system according to claim 1, further comprising: