JPH0750349A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease manufacturing cost by forming a control gate and a floating gate with a single layer conductive film. CONSTITUTION:On the side of a polycrystal Si film 14a, which is a control gate, a polycrystal Si film 14b which is a floating gate is arranged. Between the counter surfaces 34 of respective polycrystal Si films 14a and 14b, a polycrystal Si film 33 is embedded via a SiO2 film 32. Consequently, even though polycrystal Si films 14a and 14b are separate from each other planarily, there are large capacitance coupling coefficients of polycrystal Si films 14a and 14b. Hence, this enables a channel hot electron 36 generated on the drain side end of a channel 35 under the polycrystal Si film 14a to be injected only to the polycrystal Si film 14b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a control gate and a floating gate.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional example E of the present invention.
The manufacturing method of PROM is shown. In order to manufacture this conventional example, as shown in FIG. 6A, a SiO ₂ film (not shown) for a pad having a film thickness of 50 nm and a film thickness of 100 nm are formed on the surface of the Si substrate 11. And the SiN film (not shown) are sequentially formed, and then a resist (not shown) is processed on the SiN film to form a pattern of the element active region.

After that, RI using this resist as a mask
After patterning the SiN film with E and removing the resist, impurities for forming a channel stopper are ion-implanted into the Si substrate 11 using the SiN film as a mask.
Then, the SiO ₂ film 12 is formed on the surface of the element isolation region by LOCOS oxidation using the SiN film as an oxidation prevention mask. Then, the SiN film and the SiO ₂ film for the pad are sequentially removed by etching to form a SiO ₂ film 13 as a gate oxide film having a film thickness of 25 nm on the surface of the element active region.

Next, as shown in FIG. 6B, the film thickness is 15
nm polycrystal Si film 14 is deposited on the entire surface, and POCl ₃
Exposed to vapors such as phosphorus and phosphorus from the vapors
4 is performed for 1 hour at a temperature of 950 ° C., and then the polycrystalline Si film 14 is divided into patterns in the extending direction of the control gate to be formed later. A resist (not shown) is processed above. Then, the polycrystalline Si film 14 is patterned by RIE using this resist as a mask, and then the resist is removed.

Thereafter, a SiO ₂ film having a thickness of 15 nm is formed on the surface of the polycrystalline Si film 14 by thermal oxidation at a temperature of 1100 ° C., and a SiN film having a thickness of 15 nm is formed on the SiO ₂ film by the CVD method. Formed on the surface of this SiN film for 2 to 3n.
ON as an insulating film for capacitive coupling after being oxidized to a film thickness of m
The O film 15 is formed on the surface of the polycrystalline Si film 14.

After that, a polycrystalline Si film 1 having a film thickness of 30 nm is formed.
6 is deposited on the entire surface and exposed to vapor such as POCl ₃ to thermally diffuse phosphorus or the like into the polycrystalline Si film 16 from this vapor at a temperature of 950 ° C. for 1 hour. A resist (not shown) is processed on the polycrystalline Si film 16 to form a control gate pattern.

RI using this resist as a mask
The polycrystalline Si film 16, the ONO film 15, and the polycrystalline Si film 14 are sequentially patterned with E, and then the resist is removed. By this patterning, a control gate is formed by the polycrystalline Si film 16, and the polycrystalline Si film 14 is separated for each memory cell to form a floating gate.

After that, the polycrystalline Si films 16 and 14 and SiO
_{2 With the} film 12 or the like as a mask, P with an acceleration energy of about 100 keV and a dose amount of about 1 × 10 ¹⁴ cm ⁻²
Hos ⁺ is ion-implanted into the Si substrate 11. And
Annealing is performed at a temperature of 1000 ° C. for 30 minutes to obtain N ^−.
The diffusion layers 17a and 17b of the mold are formed.

Next, as shown in FIG. 6C, the film thickness is 30
A 0 nm SiO ₂ film 21 is deposited on the entire surface by the CVD method,
The entire surface of the SiO ₂ film 21 and the exposed SiO ₂ film 13
RIE is performed to form sidewalls of the SiO ₂ film 21 on the polycrystalline Si films 14, 16 and the like. Then, a SiO ₂ film 22 having a film thickness of 25 nm is deposited on the entire surface by the CVD method.

After that, the polycrystalline Si films 16 and 14 and SiO
_{The 2} films 21, 12 and the like are used as a mask and the SiO ₂ film 22 is used.
While preventing metal contamination, etc., As ⁺ S is added with an acceleration energy of about 70 keV and a dose amount of about 8 × 10 ¹⁵ cm ^-2.
Ions are implanted into the i substrate 11. Then, annealing is performed in dry oxygen at a temperature of 1000 ° C. for 40 minutes to form N ⁺ type diffusion layers 23a and 23b.

Next, as shown in FIG. 6D, the film thickness is 60
The SiO ₂ film 24 as an interlayer insulating film having a thickness of 0 nm is CV
After being deposited on the entire surface by the D method, a resist (not shown) is processed on the SiO ₂ film 24 to form a pattern of contact holes for bit lines and source lines. Then, RIE is performed using this resist as a mask to open contact holes 25 reaching the diffusion layers 23a and 23b in the SiO ₂ film 24 and the like, and then the resist is removed.

After that, an Al film 26 having a film thickness of 1.2 μm is deposited on the entire surface, and a resist (not shown) is processed on the Al film 26 to form a pattern of bit lines, source lines and the like. Then, the Al film 26 is patterned by RIE using this resist as a mask, and then the resist is removed.

After that, P-Si as an overcoat film is formed.
An N film 27 is deposited on the entire surface, and a resist (not shown) is processed on the P-SiN film 27 to have a pattern of openings for electrode pads. Then, RIE is performed using this resist as a mask to form an opening (not shown) for the electrode pad in P-SiN.
After forming the film 27, the resist is removed. Then, the Al film 26 is further sintered to complete this conventional example.

[0014]

However, in one conventional example manufactured as described above, as is clear from FIG.
Since the control gate and the floating gate have a laminated structure, it is necessary to form these control gate and the floating gate with the two-layer polycrystalline Si films 16 and 14. Therefore, the structure is complicated, the manufacturing process is long, the yield is low,
The manufacturing cost was high.

Particularly, in a semiconductor device in which a logic circuit is mounted in the peripheral circuit portion, the polycrystalline Si film in the logic circuit is 1
Since it is a layer, the second-layer polycrystalline S
It is necessary to form the i-wiring, and it is inevitable to increase the manufacturing cost of the semiconductor device having the EPROM. Further, when the polycrystalline Si film is changed from one layer to two layers, there is a concern that the yield may be reduced due to dust or the like when patterning the second-layer polycrystalline Si film, which also causes an increase in manufacturing cost. Was there.

[0016]

In the nonvolatile semiconductor memory device according to claim 1, a floating gate 14b is arranged beside the control gate 14a, and the control gate 14a and the floating gate 14b are opposed to each other. A space between the surfaces 34 is filled with the conductive film 33 with the insulating film 32 interposed therebetween.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
A constricted portion 37 constricted in the gate length direction is provided in the control gate 14a.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
These facing surfaces 3 in a state where the facing surfaces 34 are fitted to each other.
4 is bent.

[0019]

In the nonvolatile semiconductor memory device according to the first aspect, the floating gate 14b is arranged beside the control gate 14a. Therefore, the control gate 14a and the floating gate 14 are provided.
b can be formed of a single-layer conductive film.

The control gate 14a and the floating gate 1
Since the space between the respective facing surfaces 34 of the control gate 14a and 4b is filled with the conductive film 33 with the insulating film 32 interposed therebetween,
Even if the floating gate 14b and the floating gate 14b are two-dimensionally separated from each other, the capacitive coupling coefficient between the control gate 14a and the floating gate 14b is large. Therefore, the charge 36 generated at the drain side end of the channel 35 under the control gate 14a can be injected only into the floating gate 14b.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
Since the electric field is concentrated on the constricted portion 37 provided in the control gate 14a and a large amount of the charge 36 is generated in the constricted portion 37, the charge 37 can be efficiently injected into the floating gate 14b.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
Since the facing surface 34 between the control gate 14a and the floating gate 14b is bent, the facing area is large, and since the facing surfaces 34 are fitted together, the control gate 14a and the floating gate 1
The capacitive coupling coefficient with 4b is further large, and the charge 36 can be efficiently injected into the floating gate 14b.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First to fourth embodiments of the present invention applied to an EPROM will be described below with reference to FIGS.
The components corresponding to the conventional example shown in FIG.
The same reference numerals are attached.

FIG. 2 shows the first embodiment, and FIG. 1 shows the manufacturing method thereof. Also in the manufacture of the first embodiment, as shown in FIG. 1A, Si as a gate oxide film is used.
An O ₂ film 13 is formed and then polycrystalline S is deposited on the entire surface.
Until the pre-deposition method is performed on the i film, the same steps as in the case of manufacturing the conventional example shown in FIG. 6 are performed.

However, in order to manufacture the first embodiment, thereafter, a resist is processed on the polycrystalline Si film to form a pattern of control gates and floating gates extending laterally of each other. Then, the polycrystalline Si film is patterned by RIE using this resist as a mask, and as shown in FIGS. 1B and 2, the polycrystalline Si film 14a as a control gate and the polycrystalline Si film as a floating gate are patterned. 14b.

After that, the resist is removed, and another resist 31 covering the element active region between the polycrystalline Si films 14a and 14b is patterned again. And polycrystalline Si
Using the films 14a and 14b, the resist 31 and the SiO ₂ film 12 as a mask, the same ion implantation as in the case of manufacturing the conventional example described above is performed, and the resist 31 is further removed and annealed to obtain an N ⁻ -type. Diffusion layers 17a and 17b are formed.

Next, as shown in FIG. 1C, thin SiO
_{The second} film 32 and the polycrystalline Si film 33 having a film thickness of about 400 nm are sequentially deposited on the entire surface, and RIE is performed on the entire surface of the polycrystalline Si film 33 and the exposed SiO ₂ films 32 and 13 to obtain the polycrystalline Si film. The sidewalls composed of the film 33 and the SiO ₂ film 32 are formed on the polycrystalline Si films 14a and 14b, and
The polycrystalline Si film 33 fills the space between the facing surfaces 34 of the polycrystalline Si films 14a and 14b with the O ₂ film 32 interposed therebetween.

After that, the polycrystalline Si films 14a, 14b, 3
3 and the SiO ₂ film 12 as a mask, As ⁺ is ion-implanted into the Si substrate 11 with an acceleration energy of about 80 keV and a dose amount of about 7 × 10 ¹⁵ cm ^-2 , and an N ⁺ type diffusion layer 23a, 23b is formed. And the film thickness is 25n
The SiO ₂ film 22 of m is deposited on the entire surface by the CVD method, and heat treatment is performed in dry oxygen at a temperature of 1000 ° C. for 40 minutes to densify the SiO ₂ film 22. afterwards,
As shown in FIG. 1D, the same steps as those for manufacturing the above-mentioned conventional example are executed again to complete the first example.

As is apparent from the above description of the manufacturing method, in the first embodiment, the polycrystalline Si films 14a and 14b are formed.
Since only one layer is used, the compatibility with the normal MOS transistor manufacturing method is good. Therefore, MOSIC
The production of the EPROM can be easily introduced into the production line, the examination for introducing a new process is almost unnecessary, and the production start-up cost can be reduced. Moreover, since only one layer of the polycrystalline Si films 14a and 14b is used, the step difference of the base of the Al film 26 is small. Therefore, the step coverage of the Al film 26 is good, and the yield and reliability are high.

In the write operation in the first embodiment, 8 V is applied to the polycrystalline Si film 14a which is the control gate, 0 V is applied to the diffusion layer 23a which is the source, and the diffusion layer 2 which is the drain.
A voltage of 10V is applied to 3b. Then, the polycrystalline S
A channel 35 is formed under the i film 14a, channel hot electrons 36 are generated at the end of the channel 35 on the side of the diffusion layer 23b, and the polycrystalline Si film 14b, which is a floating gate, forms a capacitance with the polycrystalline Si film 14a. Be combined.
As a result, the channel hot electrons 36 become polycrystalline S
It is injected into the i film 14b.

In the read operation, the polycrystalline Si film 1 is also used.
5V for 4a, 0V for diffusion layer 23a, 1V for diffusion layer 23b
Are applied respectively. Then, a channel is formed under the polycrystalline Si film 14a, and the polycrystalline Si film 14b is capacitively coupled with the polycrystalline Si film 14a. As a result, if electrons are not injected into the polycrystalline Si film 14b, a channel is formed under the polycrystalline Si film 14b and a current flows, but if electrons are injected into the polycrystalline Si film 14b, a large amount of electrons are injected into the polycrystalline Si film 14b. Since no channel is formed under the crystalline Si film 14b and no current flows, the stored information can be determined.

In the erase operation, the polycrystalline Si film 14b is also used.
However, unlike the conventional example shown in FIG. 6, since the polycrystalline Si film 14a is not laminated on the polycrystalline Si film 14b in this first embodiment, the polycrystalline Si film 14b is not formed. It can be efficiently irradiated with ultraviolet rays and has excellent erasing characteristics.

FIG. 3 shows a second embodiment. The second embodiment is substantially the same as the first embodiment shown in FIGS. 1 and 2 except that the constricted portion 37 constricted in the gate length direction is provided in the polycrystalline Si film 14a. Have a configuration.

FIG. 4 shows a third embodiment. The third embodiment has substantially the same configuration as the first embodiment shown in FIGS. 1 and 2 except that the facing surfaces 34 are bent with the facing surfaces 34 fitted to each other. have. As the bent state of the facing surface 34, as shown in FIG.
In the case where the facing surface 34 of the polycrystalline Si film 14a has a convex shape,
As shown in (b), the facing surface 34 of the polycrystalline Si film 14a may be concave.

FIG. 5 shows a fourth embodiment. In the fourth embodiment, SiO ₂ film SiO ₂ film 12 also in the element active region which is island-like, surrounded by 12 is provided, T
The base end portion 38 of the V-shaped polycrystalline Si film 14b is made of island-shaped SiO 2.
And rides on ₂ film 12, a polycrystalline Si island SiO ₂ film 12 with film 14b is divided on both sides of the base end portion 38
No. 1 shown in Figures 1 and 2 except that
The structure is substantially similar to that of the embodiment. However, the divided polycrystalline Si films 14a are also electrically connected to each other.

The third embodiment shown in FIG. 4 has a larger facing area between the facing surfaces 34 than the first embodiment shown in FIGS. 1 and 2 and the second embodiment shown in FIG. In the shown fourth embodiment, the facing area of the facing surfaces 34 is larger than that in the third embodiment shown in FIG.

[0037]

In the non-volatile semiconductor memory device according to the first aspect of the present invention, since the control gate and the floating gate can be formed of a single-layer conductive film, the structure is simple, the manufacturing process is short, and the yield is high. , The manufacturing cost is low.

In the non-volatile semiconductor memory device according to claim 2,
Since the charges can be efficiently injected into the floating gate, the difference in threshold voltage between the injected state and the non-injected state is large.
Therefore, the stored information can be easily determined and the reliability is high.

In the non-volatile semiconductor memory device according to claim 3,
Since the charges can be efficiently injected into the floating gate, the difference in threshold voltage between the injected state and the non-injected state is large.
Moreover, since the capacitance coupling coefficient between the control gate and the floating gate is large, the potential of the floating gate can be easily controlled, and the on-current is large even if the floating gate is arranged on the side of the control gate. Therefore, the determination of the stored information is easier and the reliability is higher.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a manufacturing method of a first embodiment of the invention of the present application in the order of steps and taken along a line I-I in FIG.

FIG. 2 is a plan view of the first embodiment.

FIG. 3 is a plan view of the second embodiment.

FIG. 4 is a plan view of a third embodiment.

FIG. 5 is a plan view of a fourth embodiment.

FIG. 6 is a side sectional view showing a manufacturing method of a conventional example of the present invention in the order of steps.

[Explanation of symbols]

14a Polycrystalline Si film 14b Polycrystalline Si film 32 SiO ₂ film 33 Polycrystalline Si film 34 Opposing surface 37 Constricted portion

Claims (3)

[Claims] 1. A non-volatile structure in which a floating gate is arranged beside the control gate, and a space between the respective facing surfaces of the control gate and the floating gate is filled with a conductive film via an insulating film. Semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a constricted portion constricted in the gate length direction is provided in the control gate. 3. The non-volatile semiconductor memory device according to claim 1, wherein the facing surfaces are bent while the facing surfaces are fitted to each other.