JPH0745655A - Sealing structure of semiconductor element - Google Patents
Sealing structure of semiconductor elementInfo
- Publication number
- JPH0745655A JPH0745655A JP5192542A JP19254293A JPH0745655A JP H0745655 A JPH0745655 A JP H0745655A JP 5192542 A JP5192542 A JP 5192542A JP 19254293 A JP19254293 A JP 19254293A JP H0745655 A JPH0745655 A JP H0745655A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- sealed
- transfer molding
- tcp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体素子の収納容器
の構造に関し、更に詳しくは、TAB方式の形態を取る
半導体素子の封止構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a container for semiconductor devices, and more particularly to a sealing structure for semiconductor devices in the form of a TAB system.
【0002】[0002]
【従来の技術】従来の、TAB方式の実装形態(以下、
「TCP」と呼ぶ。)を取った半導体素子の封止構造
(以下、「パッケージ」と呼ぶ。)の断面図を図3に示
す。2. Description of the Related Art Conventional TAB type mounting modes (hereinafter referred to as
Call it “TCP”. 3 is a sectional view of a semiconductor element sealing structure (hereinafter referred to as "package").
【0003】図3において、ポリイミド等から成るキャ
リアテープ5の表面に銅等の導電性のある材料により回
路パターンを形成し、「TABテープ」と呼ばれる回路
基板を構成する。このTABテープの回路パターンと外
部回路とを接続する部分6をアウターリードと呼称し、
TABテープの回路パターンと半導体素子とを接続する
部分4をインナーリードと呼称する。半導体素子1は、
外部回路との電気的及び機械的接合性を向上させるため
の金等からなるバンプ3を介してTABテープのインナ
ーリード4に、ギャングボンディングと呼ばれる熱圧着
で他のインナーリードとともに一括して電気的及び機械
的に接合することでTCPとなる。この後、接続部及び
半導体素子の保護のために、アウターリードを残して樹
脂等からなるモールド封止材2でトランスファーモール
ドにより封止することでパッケージとなる。この場合、
保護する必要のある半導体素子の回路構成面(以下、
「能動面」と呼ぶ。)及びTABテープのインナーリー
ドとの電気的接合部以外の部分については必要以上の封
止樹脂が存在することになる。In FIG. 3, a circuit pattern is formed on the surface of a carrier tape 5 made of polyimide or the like with a conductive material such as copper to form a circuit board called "TAB tape". The portion 6 that connects the circuit pattern of the TAB tape to an external circuit is called an outer lead,
The portion 4 that connects the circuit pattern of the TAB tape and the semiconductor element is called an inner lead. The semiconductor device 1 is
Through the bumps 3 made of gold or the like for improving the electrical and mechanical bondability with the external circuit, the inner leads 4 of the TAB tape are collectively electrically connected together with other inner leads by thermocompression bonding called gang bonding. And TCP is obtained by mechanically joining. After that, in order to protect the connection portion and the semiconductor element, the outer leads are left and they are sealed by transfer molding with a mold sealing material 2 made of resin or the like to form a package. in this case,
The circuit configuration surface of the semiconductor element that needs to be protected (hereinafter,
Call it the "active surface". ) And the portion of the TAB tape other than the electrically joined portion with the inner lead, there is more sealing resin than necessary.
【0004】[0004]
【発明が解決しようとする課題】しかし、使用する機器
に対する軽薄短小への要求から半導体素子は高集積化が
進み半導体素子の外形は大きくなり、パッケージの外形
も従来に比べ大きくなる一方である。従って、外形の大
きい半導体素子を従来のようにパッケージにすると、半
導体素子の厚みだけは従来と同じであるため、封止に使
用するモールド樹脂の量が多くなることから、部品とし
てのパッケージの重量が半導体素子の大きさに比例して
重くなるという問題点を有することとなった。また、紫
外線消去書換え可能読みだし専用メモリー(以下、「U
VEPROM」と呼ぶ)や電荷結合素子(以下、「CC
D」と呼ぶ。)等の半導体素子の回路構成面、あるいは
光半導体素子の光学的接合部をモールド封止することが
できない半導体素子についてはTCPにした場合、トラ
ンスファーモールドによるパッケージ化が困難であると
いう問題点も有することとなった。However, due to the demand for light, thin, short, and small devices to be used, the semiconductor element is becoming highly integrated, and the outer shape of the semiconductor element is becoming larger, and the outer shape of the package is becoming larger than ever. Therefore, if a semiconductor element with a large outer shape is packaged as in the conventional case, the thickness of the semiconductor element is the same as in the conventional case, and the amount of mold resin used for sealing is large. Has a problem in that it becomes heavier in proportion to the size of the semiconductor element. In addition, a read-only memory that can be erased and rewritten with ultraviolet light (hereinafter, "U
VEPROM ") and charge coupled device (hereinafter referred to as" CC
D ". ) And the like, or a semiconductor element in which the optical junction of the optical semiconductor element cannot be molded and sealed, when TCP is used, there is a problem that packaging by transfer molding is difficult. It became a thing.
【0005】本発明の目的は、TCPを樹脂から成るモ
ールド封止材を使用したトランスファーモールドより封
止した場合のパッケージの重量を、従来に比べ低減する
こと、また、UVEPROM、CCD等の半導体素子の
能動面がモールド封止できない半導体素子をTCPにし
た場合にトランスファーモールドによりパッケージ化を
可能にすることにある。An object of the present invention is to reduce the weight of a package when TCP is sealed by a transfer mold using a mold encapsulant made of a resin, as compared with the prior art, and a semiconductor device such as UVEPROM or CCD. When a semiconductor element whose active surface is not mold-sealed is TCP, transfer molding enables packaging.
【0006】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため下記の手段をとる。The present invention adopts the following means in order to achieve the above object.
【0007】(手段1)半導体素子と外部回路との電気
的接合部並びに能動面のみを、トランスファーモールド
より樹脂封止する。(Means 1) Only the electrical connection between the semiconductor element and the external circuit and the active surface are sealed with resin by transfer molding.
【0008】(手段2)半導体素子と外部回路との電気
的接合部のみを、トランスファーモールドより樹脂封止
する。(Means 2) Only the electrical connection between the semiconductor element and the external circuit is sealed with resin by transfer molding.
【0009】[0009]
【実施例】以下、本発明の実施例を図1、図2、図4、
図5及び図6により説明する。(手段1)に基づきTC
Pに本発明を実施した例の断面図を図1に示す。図1に
示すように、TABテープのインナーリード4と半導体
素子2を例えばギャングボンディングによりバンプ3を
介して接合し、TCPにする。次に、半導体素子とTA
Bのインナーリードの接合部、並びに半導体素子の能動
面のみをトランスファーモールドにより樹脂封止する。
トランスファーモールドでは、図6に示す様に上下或い
は左右に分割可能なモールド金型9の分割面に、樹脂を
注入することで形成するキャビティー10と呼ばれる空
洞が設けられており、このキャビティーに封止しようと
するTABに接続された半導体素子2を挟み込み、金型
を閉じキャビティーに樹脂を注入し硬化させパッケージ
を形成している。本発明のよれば、半導体素子の樹脂に
より封止する部分を、図1に示すように半導体素子の回
路構成面を平面とした場合の外周部分より外側へはみ出
すことがないようにするため、モールド金型9上のキャ
ビティー10の構造において、キャビティー10と半導
体素子2の両者の側面の境界を、封止樹脂が入り込まな
い10μm以下程度の間隔になるようキャビティーの側
面部分を製作し、このキャビティーに半導体素子をはめ
込み樹脂成形することで、図1に示すようにTABテー
プと半導体素子の接続部並びに半導体素子の能動面だけ
を樹脂封止する事ができる。EXAMPLES Examples of the present invention will be described below with reference to FIGS.
This will be described with reference to FIGS. 5 and 6. TC based on (Means 1)
A sectional view of an example in which the present invention is applied to P is shown in FIG. As shown in FIG. 1, the inner lead 4 of the TAB tape and the semiconductor element 2 are joined together via the bump 3 by, for example, gang bonding to form a TCP. Next, the semiconductor element and TA
Only the joint portion of the inner lead of B and the active surface of the semiconductor element are resin-molded by transfer molding.
In the transfer mold, as shown in FIG. 6, a cavity called a cavity 10 formed by injecting a resin is provided on the dividing surface of a molding die 9 that can be divided into upper and lower parts or left and right parts. The semiconductor element 2 connected to the TAB to be sealed is sandwiched, the mold is closed, and resin is injected into the cavity and cured to form a package. According to the present invention, in order to prevent the portion of the semiconductor element to be sealed with resin from protruding outside the outer peripheral portion when the circuit configuration surface of the semiconductor element is a flat surface as shown in FIG. In the structure of the cavity 10 on the mold 9, the side surfaces of the cavity 10 and the semiconductor element 2 are formed such that the side surfaces of the cavity are separated by 10 μm or less so that the sealing resin does not enter. By fitting the semiconductor element into this cavity and molding the resin, only the connecting portion between the TAB tape and the semiconductor element and the active surface of the semiconductor element can be resin-sealed as shown in FIG.
【0010】また、(手段2)による本発明の一実施例
を図2、図4及び図5を用いて説明する。図2は本発明
の実施例の断面図で、図4及び図5は図2に示す本発明
の実施例の製造方法の一例を示す図である。An embodiment of the present invention by (means 2) will be described with reference to FIGS. 2, 4 and 5. 2 is a sectional view of an embodiment of the present invention, and FIGS. 4 and 5 are views showing an example of a manufacturing method of the embodiment of the present invention shown in FIG.
【0011】図4に示すように、半導体素子1とTAB
テープのインナーリード4とのバンプ3を介して接合を
行いTCPにした後、半導体素子の回路構成面で露光等
のために開口部としたい部分に、例えば耐熱性のある透
明なシリコーン等の樹脂7を、半導体素子の回路構成面
を平面とした場合の、樹脂により封止しようとする断面
に於ける厚さと等しくなるように板状にして、例えば紫
外線硬化型の接着剤8で接着する。この後、手段1と同
じくトランスファーモールドにより樹脂封止する。図5
に示すような成形後のパッケージの接着材8に紫外線を
照射する事で接着材の粘着力を低下させ、板状の樹脂7
は剥離する。以上の方法で図2に示すようなパッケージ
が完成する。As shown in FIG. 4, the semiconductor element 1 and the TAB are
After bonding to the inner lead 4 of the tape via the bump 3 to form a TCP, a resin such as a heat-resistant transparent silicone is formed on a portion of the semiconductor element circuit configuration surface where an opening for exposure or the like is to be formed. 7 is formed into a plate shape so as to have the same thickness as the cross section to be sealed with resin when the circuit configuration surface of the semiconductor element is a flat surface, and is adhered by, for example, an ultraviolet curing adhesive 8. After that, resin sealing is performed by transfer molding as in the case of the means 1. Figure 5
The adhesive force of the adhesive is reduced by irradiating the adhesive 8 of the package after molding as shown in FIG.
Peels off. The package as shown in FIG. 2 is completed by the above method.
【0012】[0012]
【発明の効果】本発明によれば、従来のTCPと比較し
て、封止樹脂2の占有する体積が、従来の例を示す図3
の封止樹脂2の体積に比べ20%程度まで抑えることが
でき、TCPの軽量化及び小型化を実現することが可能
となる。また、従来トランスファーモールドTCP化が
困難であったUVEPROMやCCD、光半導体素子等
の受光、発光を機能に持つ素子をTCP化する事がで
き、かつ、半導体素子と封止樹脂の線膨張率の違いによ
るパッケージの反りが発生しないという効果がある。ま
た、従来の製造工程と比較して、トランスファーモール
ド工程に於いて使用するモールド金型の形状が異なるだ
けで、本発明を実施する上での生産工程への影響が非常
に少ないという効果がある。According to the present invention, as compared with the conventional TCP, the volume occupied by the sealing resin 2 is shown in FIG.
The volume can be suppressed to about 20% of the volume of the sealing resin 2 and the TCP can be reduced in weight and size. In addition, elements such as UVEPROMs, CCDs, and optical semiconductor elements that have functions of receiving and emitting light, which have been difficult to form by transfer mold TCP, can be formed into TCP, and the linear expansion coefficient of the semiconductor element and the sealing resin can be reduced. There is an effect that the package does not warp due to the difference. Further, compared with the conventional manufacturing process, only the shape of the molding die used in the transfer molding process is different, and there is an effect that the production process in implementing the present invention is significantly less affected. .
【図1】本発明の手段1に基づく一実施例の断面図。FIG. 1 is a sectional view of an embodiment according to means 1 of the present invention.
【図2】本発明の手段2に基づく一実施例の断面図。FIG. 2 is a sectional view of an embodiment based on means 2 of the present invention.
【図3】従来のTCPの断面図。FIG. 3 is a sectional view of a conventional TCP.
【図4】本発明の手段2に基づく一実施例の形成過程を
示す断面図。FIG. 4 is a cross-sectional view showing the forming process of an embodiment based on means 2 of the present invention.
【図5】本発明の手段2に基づく一実施例の形成過程を
示す断面図。FIG. 5 is a cross-sectional view showing the forming process of one embodiment based on means 2 of the present invention.
【図6】本発明の手段1に基づく一実施例の形成過程を
示す断面図。FIG. 6 is a cross-sectional view showing the forming process of one embodiment based on means 1 of the present invention.
1 半導体素子 2 封止樹脂 3 バンプ 4 インナーリード 5 キャリアテープ 6 アウターリード 7 耐熱性のある樹脂 8 紫外線硬化型の接着剤 9 モールド金型 10 キャビティー 1 Semiconductor Element 2 Sealing Resin 3 Bump 4 Inner Lead 5 Carrier Tape 6 Outer Lead 7 Heat-Resistant Resin 8 UV-Curing Adhesive 9 Mold Die 10 Cavity
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 // B29L 31:34 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display area // B29L 31:34
Claims (2)
の封止方法に関し、半導体素子と外部回路との電気的接
合部並びに回路構成面のみに、樹脂等からなるモールド
封止材によってトランスファーモールドを施すことを特
徴とする半導体素子の封止構造。1. A method of encapsulating a semiconductor element in a TAB mounting form, which is transfer-molded with a molding encapsulant made of a resin or the like only on an electrical joint between the semiconductor element and an external circuit and a circuit configuration surface. A sealing structure for a semiconductor element, characterized in that:
の封止方法に関し、半導体素子と外部回路との電気的接
合部のみに、樹脂等からなるモールド封止材によってト
ランスファーモールドを施すことを特徴とする半導体素
子の封止構造。2. A method of encapsulating a semiconductor element having a TAB mounting structure, wherein transfer molding is performed only on an electrical junction between the semiconductor element and an external circuit with a mold encapsulating material made of resin or the like. Characteristic semiconductor element sealing structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05192542A JP3141634B2 (en) | 1993-08-03 | 1993-08-03 | Semiconductor device manufacturing method and resin sealing mold |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05192542A JP3141634B2 (en) | 1993-08-03 | 1993-08-03 | Semiconductor device manufacturing method and resin sealing mold |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0745655A true JPH0745655A (en) | 1995-02-14 |
JP3141634B2 JP3141634B2 (en) | 2001-03-05 |
Family
ID=16293015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05192542A Expired - Fee Related JP3141634B2 (en) | 1993-08-03 | 1993-08-03 | Semiconductor device manufacturing method and resin sealing mold |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3141634B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08306899A (en) * | 1995-04-27 | 1996-11-22 | Lg Semicon Co Ltd | Package for solid-state image pickup element and its preparation |
JPH11168154A (en) * | 1997-08-25 | 1999-06-22 | Motorola Inc | Semiconductor element and manufacture thereof |
US6476507B1 (en) | 1999-08-10 | 2002-11-05 | Towa Corporation | Resin sealing method and resin sealing apparatus |
KR100494666B1 (en) * | 2001-12-28 | 2005-06-13 | 동부아남반도체 주식회사 | connceting ccd image senser for csp semiconducter |
US8865022B2 (en) | 2011-01-06 | 2014-10-21 | Shin-Etsu Chemical Co., Ltd. | Phosphor particles and making method |
US9617469B2 (en) | 2011-01-06 | 2017-04-11 | Shin-Etsu Chemical Co., Ltd. | Phosphor particles, making method, and light-emitting diode |
-
1993
- 1993-08-03 JP JP05192542A patent/JP3141634B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08306899A (en) * | 1995-04-27 | 1996-11-22 | Lg Semicon Co Ltd | Package for solid-state image pickup element and its preparation |
JPH11168154A (en) * | 1997-08-25 | 1999-06-22 | Motorola Inc | Semiconductor element and manufacture thereof |
US6476507B1 (en) | 1999-08-10 | 2002-11-05 | Towa Corporation | Resin sealing method and resin sealing apparatus |
KR100494666B1 (en) * | 2001-12-28 | 2005-06-13 | 동부아남반도체 주식회사 | connceting ccd image senser for csp semiconducter |
US8865022B2 (en) | 2011-01-06 | 2014-10-21 | Shin-Etsu Chemical Co., Ltd. | Phosphor particles and making method |
US9617469B2 (en) | 2011-01-06 | 2017-04-11 | Shin-Etsu Chemical Co., Ltd. | Phosphor particles, making method, and light-emitting diode |
Also Published As
Publication number | Publication date |
---|---|
JP3141634B2 (en) | 2001-03-05 |
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