JPH0744583A - High-grade synthesizing device - Google Patents

Abstract

PURPOSE:To provide a high grade synthesizing device in which the result of resource assignment in a high grade synthesis system can be easily obtained. CONSTITUTION:This device is equipped with a resource-classified C/DFG preparing means 102 which prepares a control data flow graph (C/DFG) which is classified for each resource based on information related to resource assignment, and a C/DFG display means 103 which displays the C/DFG prepared by the resource-classified C/DFG preparing means 102. Thus, the result of the resource assignment can be easily confirmed on the C/DFG, and the efficiency of the confirming work of the result of resource assignment can be sharply improved. The situation of the usage of the resource, that is, whether or not each computing element and storage element is used in a specific cycle time can be also easily obtained, and the using frequency of each computing element and storage element can be easily confirmed on the C/DFG, so that the work of the evaluation and correction of the result of resource assignment can be effectively attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-level synthesizer for synthesizing a logic circuit from the operating specifications of a digital circuit to be designed.

[0002]

2. Description of the Related Art With the increase in the scale of LSIs, design automation tools have become important. Therefore, for the purpose of shortening the logic design period, an automatic logic synthesizing system for automatically synthesizing a logic circuit from a function description at a register transfer level has been used. Furthermore, recently, for the purpose of shortening the functional design period, a high-level synthesis system that automatically synthesizes a register transfer level circuit from an operation specification description that algorithmically describes the operation specification of the design target has also been used. There is.

Conventionally, in order for a designer to grasp and confirm the specifications described by the operation specification description, a graph called a control data flow graph (hereinafter abbreviated as C / DFG) is a flow of data and processing for the data. It was done by displaying. In this C / DFG, processing for data is represented by vertices, and data flow is represented by edges.

As a method using C / DFG, for example,
PGPaulin, JPKnight and EF Girczuc, "HAL: A Mu
lti-Paradigm Approach to Automatic Data Path Synth
esis ", Proceedings of the 23rd ACM / IEEEE Deisign A
utomation Conference, pp.263-270, 1986 is known. In addition, processing such as scheduling and resource allocation is performed based on the operation specification, and high-level synthesis is advanced. For confirmation work of the resource allocation result, a table output regarding the resource allocation result is compared with the operation specification and C / DFG. I was going.

[0005]

However, in the conventional resource allocation confirmation work, table output, operation specification, C / D
Since it is compared with the FG, there is a problem that the work is complicated and it is very difficult to grasp the allocation result when the design target is large-scale.

The present invention is intended to solve the above problems, and it is an object of the present invention to provide a high-level synthesis apparatus capable of easily grasping the result of resource allocation in a high-level synthesis system.

[0007]

In the high-level synthesis apparatus according to the present invention, resource-based C / DFG creating means for creating C / DFGs distinguished for each resource based on information on resource allocation, and resource-based C / DFG creating means C / DFG display means for displaying the C / DFG created by the C / DFG creation means.

[0008]

According to the above means, the present invention firstly provides C / by resource
The C / D in which the DFG creating means distinguishes the column position and display color for each resource based on the information on the result of resource allocation
The FG information is generated, and then the C / DFG display means displays this craft based on the C / DFG information. As a result, the result of resource allocation can be easily confirmed on the C / DFG.

[0009]

【Example】

[Embodiment 1] The structure of the present invention is shown in FIG. As shown in FIG. 1, the present invention provides a high-level synthesis processing unit 101, resource-based C / DF.
G creation unit 102, C / DFG display unit 103, C / DFG
The information storage unit 104 and the resource allocation information storage unit 105 are included.

This embodiment will be described below by taking the C / DFG shown in FIG. 2 as an example. The high-level synthesis processing unit 101 is a unit that performs a conventional high-level synthesis process. When the operation specification of the design target is input, the high-level synthesis processing unit 101 performs a scheduling process that allocates each operation in the operation specification to each cycle time, and performs C / D.
FG information is generated and stored in the C / DFG information storage unit 104. The C / DFG information includes the node table shown in FIG.
It comprises an edge table shown in FIG. 4 and a time cycle table not specified here.

As shown in FIG. 3, the node table is C /
Node numbers numbered in the order of DFG node generation,
The node type indicating whether the node represents an input variable, operation, or storage element in the operation specification, the input variable name or the node name indicating the operation type, and the C / D of the node
It is composed of a coordinate value indicating a display position on the FG and an edge number connected to each input / output of the node.

As shown in FIG. 4, the edge table has an edge number numbered in the order of C / DFG edge generation, a node number and a terminal identifier at the start point of the edge, and a node number and a terminal identifier at the end point of the edge. It consists of The time cycle table includes a node number scheduled for each cycle and information about a line segment (broken line portion in FIG. 2) which is a delimiter between the cycles on the C / DFG.

When the high-level synthesis processing unit 101 generates the information of the node table, the edge table, and the time cycle table and stores them in the C / DFG information storage unit 104, the C / DFG display unit 103 displays the C / DFG. Display on the device. The C / DFG display unit 103 holds information about the shape for each node type (referred to as node shape information) as shown in FIG. In FIG.
The solid line part shows the shape of the node, the x shows the terminal position of the node, the broken line rectangle shows the display position of the node name, and the two-dot broken line rectangle shows the display position of the node number.

When the C / DFG display unit 103 is activated,
First, the node table shown in FIG. 3 is read out and each node in the node table is displayed at the position indicated by the coordinate value. For example, in the process of the node number 1 in FIG. 3, since the node type of the node number 1 is input, the node name a at the position of the coordinates (x _i1 , y _i ) is based on the node shape information of the input node.
The node display consisting of is displayed on the display device.

Further, in the processing of the node number 9, since the node type is the operation, the circle and the two line segments, the node name +, at the position of the coordinates (x ₁ , y ₂ ) are calculated from the node shape information of the operation node. A node display consisting of node number 9 is performed. Next, the C / DFG display unit 103 obtains the coordinates of each start point and end point of the edge table from the coordinate values of the node table and the terminal position of the node shape information, and displays each edge on the display device. Finally, the C / DFG display unit 103 reads out information about a line segment that separates each cycle from the time cycle table and displays it on the display device. With the above processing, the C / DFG shown in FIG.
Is displayed.

Next, the high-level synthesis processing unit 101 allocates arithmetic unit resources to each arithmetic node, and stores the result in the resource allocation information storage unit 105 in the format shown in FIG. 6 (called an arithmetic unit allocation table).
Store with. FIG. 6 shows that, for example, the nodes with node numbers 10 and 12 are assigned the adder named ADD1.

When the arithmetic unit allocation table is stored in the resource allocation information storage unit 105 by the high-level synthesis processing unit 101, the resource-based C / DFG creation unit 102 advances the processing according to the processing flow shown in FIG. Here, it is assumed that the arithmetic unit coordinate table is shown in FIG. 8 and is stored in the resource-specific C / DFG creating unit 102. In the processing flow shown in FIG. 7, the processing of steps S71 to S73 is repeatedly applied to all the arithmetic units in the arithmetic unit allocation table in FIG.

First, as the arithmetic unit number 1, the arithmetic unit coordinate table shown in FIG. 8 is drawn to obtain the x coordinate x ₁ (step S7).
1). Next, from the arithmetic unit number 1 in the arithmetic unit allocation table,
Obtain the name ADD1 of the calculator, and add it to the x coordinate x ₁ at the top of the drawing.
A command for displaying D1 is sent to the C / DFG display unit 103 (step S72). Further, next, from the operator number 1 in the operator assignment table, the node numbers 10 and 12 of the operation to which this operator is assigned are obtained, and the x coordinate of the coordinate value of the node numbers 10 and 12 in the node table is x. _It is rewritten to ₁ (step S73).

After repeating the same processing for the arithmetic units with arithmetic unit numbers 2 to 4, the conventional C / DFG input node arrangement processing is applied to rearrange the nodes (steps). S74), the contents of the node table shown in FIG. 3 are changed as shown in FIG. The resource-based C / DFG creating unit 102 activates the C / DFG display unit 103 after the above processing is completed. The C / DFG display unit 103 performs the processing of the command for displaying the arithmetic unit name transmitted from the resource-specific C / DFG creation unit 102 and the processing similar to that described in the display of FIG. The C / DFG shown is displayed on the display device.

In the design using the conventional high-level synthesizer, it is necessary to grasp how the arithmetic units are allocated from the C / DFG shown in FIG. 2 and the output of the arithmetic unit allocation table shown in FIG. was there. On the other hand, in the present invention,
Since the C / DFG shown in FIG. 10 can be displayed, the C / DF
It is possible to easily grasp which arithmetic node on G is assigned to which arithmetic unit. Further, as is clear from FIG. 10, it is possible to easily grasp the status of the usage of each computing unit, that is, whether each computing unit is used in a specific cycle time, and the usage frequency of each computing unit is easy on the C / DFG. Can be confirmed.

[Embodiment 2] An embodiment will be described below in which a storage node indicating a latch of a C / DFG signal is also displayed.

FIG. 11 shows a node table when the storage node is also displayed. Here, a storage node is added as a node type. Based on this, the C / DFG shown in FIG.
It is displayed by the FG display unit 103. In the explanation below,
The description will focus on the processing of the added storage node.

The high-level synthesis processing unit 101 allocates a storage element resource to each storage node and outputs the result to the resource allocation information storage unit 1.
The format of FIG. 13 in 05 (called storage element allocation table)
Store with. In FIG. 13, for example, node numbers 18 and 20
It is shown that the storage element named REG1 is assigned to the node.

When the high-level synthesis processing unit 101 stores the arithmetic unit allocation table and the storage element allocation table in the resource allocation information storage unit 105, the resource-specific C / DFG creation unit 102 processes according to the processing flow shown in FIG. And the processing shown in the processing flow of FIG. 14 is further performed before performing the input node rearrangement processing in step S74. Here, the storage element coordinate table is shown in FIG. 15, and the resource-specific C / DFG is shown.
It is assumed that it is stored in the creation unit 102.

In the processing flow shown in FIG. 14, step S
The processing of steps 141 to S143 is shown in FIG.
Repeatedly applied to all three storage elements. First, as the storage element number 1, the storage element coordinate table shown in FIG.
Subtract 5 to get the x coordinate x ₀ . (Step S141).
Next, the storage element name REG1 is obtained from the storage element number 1 in the storage element allocation table, and RE is set to the x coordinate x ₀ at the top of the drawing.
A command for displaying G1 is sent to the C / DFG display unit 103 (step S142).

Further, next, from the storage element number 1 in the storage element allocation table, the node numbers 18 and 20 of the node to which this storage element is allocated are obtained, and the coordinate value x of the node numbers 18 and 20 in the node table is obtained. The coordinates are rewritten to x ₀ (step S143). Hereinafter, the same processing is repeated for the storage elements with storage element numbers 2 to 4.

Subsequently, the conventional C / DFG input node arrangement processing is applied to rearrange the input nodes, and the arrangement shown in FIG.
The contents of the node table shown in FIG. 1 are changed as shown in FIG. The resource-based C / DFG creating unit 102 activates the C / DFG display unit 103 after the above processing is completed. C /
The DFG display unit 103 is a resource-specific C / DFG creation unit 102.
The processing of the command for displaying the arithmetic unit name and the storage element name sent by the CPU and the processing similar to that described in the display of FIG. 2 are performed, and the C / DFG shown in FIG. 17 is displayed on the display device.

As is apparent from the above description, since C / DFG as shown in FIG. 17 can be displayed in the present invention, C / DFG is displayed.
It is possible to easily grasp the result of resource allocation, which operation node on the DFG is assigned to which operation unit, and which storage element is assigned to which storage node. Further, as is clear from FIG. 17, it is possible to easily grasp the situation of resource use such as whether or not each arithmetic unit / storage element is used at a specific cycle time, and the frequency of use of each arithmetic unit / storage element. It can be easily confirmed on C / DFG.

In the first and second embodiments described above, the x-coordinate of each arithmetic unit number and each storage element number is prepared in advance by a coordinate table, but the x-coordinate of the arithmetic unit number i = arithmetic node Display start point x coordinate + (i−1) × coordinate interval may be calculated as follows: x coordinate of storage element number i = storage node display start point x coordinate + (i−1) × coordinate interval. In the first and second embodiments, the column positions of the C / DFG display nodes are displayed separately for each allocated resource, but the colors and line types may be displayed separately. good. this is,
For example, in the arithmetic unit coordinate table (FIG. 8), information about display colors such as red for arithmetic unit number 1 and yellow for arithmetic unit number 2 is also stored, and a field indicating the display color is provided in the node table. This can be easily realized by obtaining the display color of the arithmetic unit number corresponding to each arithmetic node of the node table from the arithmetic unit coordinate table and storing it, and displaying it in the color corresponding to this in the C / DFG display section. . Further, both the column position and the color may be displayed separately.

Further, by designating the arithmetic unit number in the resource-specific C / DFG creation unit and changing the display color of the node table only for the arithmetic node corresponding to the designated arithmetic unit number, It is also possible to change the display color and highlight only the node assigned to the arithmetic unit having the specific arithmetic unit number designated by the user.

[0031]

As described above, by using the present invention, the resource allocation result can be easily confirmed on the C / DFG, and the efficiency of the resource allocation result confirmation work can be greatly improved. In addition, it is possible to easily understand the usage status of resources such as whether or not each computing unit / memory element is used in a specific cycle time, and to easily check the usage frequency of each computing unit / memory element on the C / DFG. Therefore, it is also effective for the work of evaluating / correcting the resource allocation result.

[Brief description of drawings]

FIG. 1 is a configuration diagram according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of C / DFG.

FIG. 3 is a diagram showing the contents of a node table corresponding to the C / DFG shown in FIG.

FIG. 4 is a diagram showing the contents of an edge table corresponding to the C / DFG shown in FIG.

FIG. 5 is a diagram showing node shape information.

FIG. 6 is a diagram showing the contents of an arithmetic unit allocation table.

FIG. 7 is a diagram showing a processing flow of a resource-specific C / DFG creation unit according to an embodiment of the present invention.

FIG. 8 is a diagram showing the contents of a calculator coordinate table.

9 is a diagram showing the contents of a node table after the processing flow of FIG. 7 is applied.

FIG. 10 is a C / DF generated according to an embodiment of the present invention.
The figure which shows G.

FIG. 11 is a diagram showing the contents of a C / DFG node table including storage nodes.

FIG. 12 is a C / DF corresponding to the node table of FIG.
The figure which shows G.

FIG. 13 is a diagram showing the contents of a storage element allocation table.

FIG. 14 is a diagram showing a processing flow of a resource-specific C / DFG creation unit for a storage node according to an embodiment of the present invention.

FIG. 15 is a diagram showing the contents of a storage element coordinate table.

16 is a diagram showing the contents of a node table after the processing flows of FIGS. 7 and 14 have been applied.

FIG. 17 shows C / produced by the second embodiment of the present invention.
The figure which shows DFG.

[Explanation of symbols]

 101 High-level synthesis processing unit 102 Resource-specific C / DFG creation unit 103 C / DFG display unit 104 C / DFG information storage unit 105 Resource allocation information storage unit

Claims (2)

[Claims] 1. A resource-specific C / DFG creating means for creating a control data flow graph distinguished for each resource in a high-level synthesizing device for synthesizing a logic circuit from an operation specification of a digital circuit. And a C / DFG display means for displaying the control data flow graph created by the resource-specific C / DFG creation means. 2. The high-level synthesis apparatus according to claim 1, wherein the resource-specific C / DFG creating means creates a control data flow graph in which a column position is distinguished for each resource.