JPH0738570A - Srts control method - Google Patents

Abstract

PURPOSE:To make self-traveling possible even in the case of cell losing or the like by previously predicting RTS information to be received and using the predicted RTS information when the RTS information to be received is lost. CONSTITUTION:When the RTS information is inputted to an input selecting means 1, this time, it is outputted as RTS. At the same time, the this-time RTS is inputted and stored in a first storage means 2, and it is outputted to a subtracting means 3 as last-time RTS. At the subtracting means 3, a differential value is calculated by taking difference between the last-time RTS and the this-time RTS from the input selecting means 1, and the calculated differential value is stored by a second storage means 4. At a judging means 5, the differential value outputted from the second storage means 4 is outputted to an adding means 6 as a predictive differential value. The adding means 6 calculates predictive RTS by adding the predictive differential value to the last-time RTS from the first storage means 2. When the RTS loss is inputted, the calculated predictive RTS is used as the this-time RTS in place of the lost RTS information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
Transfer Mode: An asynchronous transfer mode) relates to a method of converting a signal asynchronous with a network clock into cells in communication.

[0002]

[Prior Art] International Telegraph and Telephone Consultative Committee (CCITT)
Recommendation I. In 363, SRTS (Synchronous) is used as a means for transferring the frequency information of the original signal when the signal asynchronous with the network clock is transferred into cells by ATM.
Residual Time Stamp) is recommended. This is an I.D. As indicated by reference numeral 363, the p-bit counter is driven by the x-divided clock fnx of the network clock fn, and the output of this counter is latched every N counts of the clock fs of the transferred signal. The latched result is called RTS (Residual Time Stamp) information.
This RTS information is used as CSI (Convergence Subla
yer Indication) bit, and the receiving side uses the phase locked loop PLL based on the received RTS information.
To reproduce the clock fs.

[0003]

In the above-mentioned SRTS, it is necessary to consider the case where, for example, a cell is lost and RTS information is lost. I. According to 363 R
TS information is transferred using 4 cells out of 8 cells, but R
If even one of the four cells transmitting the TS information is lost, the RTS information is lost. Therefore, even if cell loss continues at a rate of once every eight cells, RTS information may be lost continuously. At this time, the PL on the receiving side
In some cases, L may run at a frequency completely unrelated to the clock fs of the signal to be transferred, and the output of the receiving side may deviate from the allowable frequency range of the clock fs. Further, even if the correct RTS information can be received after that, the PLL keeps the clock f
It may take some time to converge to s.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and in the case where RTS information is lost due to cell loss or the like, a signal transmitted through a PLL on the receiving side is The purpose is to provide means for self-propelled near the clock fs.

For this purpose, the present invention receives an RT.
The S information is predicted in advance, and when the RTS information to be received is lost, the predicted RTS information is used.

[0006]

As an example of the transferred RTS information, the clock fs of the transferred signal is 44.736 MHz which is a digital third group in North America, and the network clock fn is 15 of the synchronous digital hierarchy SDH.
5.52 MHz, frequency division ratio x is 2 and a frequency-divided clock f is 2.
When nx is 77.76 MHz, the RTS information is as shown in FIG. 1 when the 4-bit binary number is represented by a decimal number. The difference between these RTS sequences is 12 or 1.
It can be seen that this is simple repetitive information such as 3 and almost 12 and 13 appear alternately. The difference series has a period of 2, for example, in the paper “Jitter in SRTS” (1992 IEICE Spring Conference,
(Scheduled to be announced in March 1993),
This is because the parameter called the remainder is near 1/2. The receiving side uses this fact to calculate the difference between the previous RTS and the current RTS. When the difference is 12, the difference predicted value of the next RTS is set to 13, and when the difference is 13, the difference predicted value of the next RTS is calculated. Is set to 12. Then, a value obtained by adding the difference prediction value to the previous RTS is set as a prediction RTS value, and when the RTS is lost due to a cell loss or the like, this RTS value is calculated as
Used as TS.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the SRTS control method of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention when the period of the difference series is 2.

In the figure, reference numeral 1 is a reception RT which is an input.
It is an input selection unit that selects either S or the predicted RTS based on the presence or absence of the RTS loss signal, and outputs this time as the RTS. The received RTS is the received RTS information,
Predicted RTS is not received because RTS information is lost,
RTS information predicted by the present invention, which is RT
The S loss indicates a detection signal when the RTS information is lost. Reference numeral 2 is a first storage means for storing the current RTS output from the input selection means 1, and 3 is a subtraction means for obtaining the difference between the current RTS and the previous RTS stored in the first storage means. Reference numeral 4 is second storage means for storing the difference obtained by the subtraction means 3, and reference numeral 5 is determination means for determining the next difference value from the difference value stored in the second storage means. 6 is the predicted difference value obtained by the judgment means 5 and the current R from the first storage means.
TS is added to obtain the predicted RTS, which is output to the input selection means 1.

Next, the operation of the SRTS control method of the embodiment will be described. The RTS information transferred by the SRTS method in ATM is output as the RTS this time when input to the input selection unit 1. On the receiving side this time R
Clock f of signal transferred by PLL based on TS
It is used to regenerate s. At the same time, the RTS this time is input and stored in the first storage means 2, and is output to the subtraction means 3 as the previous RTS. In the subtraction means 3, the previous RT
The difference value is obtained by taking the difference between S and the current RTS from the input selection means 1, and the obtained difference value is stored in the second storage means. When the difference value output from the second storage unit 4 is 12, the determination unit 5 outputs 13 to the addition unit 6 as a prediction difference value, and when the difference value is 13, outputs 12 to the addition unit 6 as a prediction difference value. The adding means 6 uses the predicted difference value as the first value.
The predicted RTS is obtained by adding to the previous RTS from the storage means 2. The predicted RTS thus obtained is received by the input selection means 1 as RT.
When STS is lost and is not input and RTS loss is input, it is used as the RTS this time instead of the lost RTS information.

The clock fs of the signal transferred again is 4
4.736MHz, divided clock fns is 77.76M
Considering the case of Hz, the RTS predicted by this embodiment
The information corresponds to the case where fs is around 44.736 MHz, so when the RTS information is lost, the PL on the receiving side is lost.
L is controlled to oscillate near fs. Therefore, even if the RTS information is lost due to cell loss, the PLL on the receiving side does not oscillate outside the allowable frequency range of fs,
Moreover, when the RTS information is correctly received, the pull-in time becomes short.

Although FIG. 2 shows the case where the cycle of the RTS difference series is 2, the present invention can be applied even when the cycle of the difference series is other than 2. FIG. 3 is a block diagram showing the configuration of the embodiment of the present invention when the difference series is 12, 12, and 13 and the cycle is 3. In FIG. 3, the calculated difference value is stored twice by the two second storage units 4-1 and 4-2. In the judging means 5, when both the stored difference values are 12, 13 is set as the predicted difference value, and in other cases, it is 12
Is the predicted difference value.

Generally, even if the difference series has a period of 4 or more, the present invention can be applied by increasing the number of difference values to be stored.

Also, as is apparent from the embodiment of FIG. 2 or 3, the present invention will operate correctly even if the received RTS is lost continuously. That is, when the received RTSs are continuously lost, the next predicted RTS value is generated based on the predicted RTS value used in the past, so that the output current R
TS is a correct prediction value.

[0015]

As described above, according to the present invention,
Even if the RTS information is lost due to cell loss or the like when an asynchronous signal is transferred by ATM, the lost RTS can be predicted, the PLL on the receiving side can be free-running in the vicinity of fs, and again. If the RTS is correctly received, the PLL synchronization can be achieved quickly.

[Brief description of drawings]

FIG. 1 Example of RTS information series

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention when the difference sequence period is 2.

FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention when the difference series has a period of 3;

[Explanation of symbols]

 1 Input Selection Means 2 First Storage Means 3 Subtraction Means 4, 4-1 and 4-2 Second Storage Means 5 Judgment Means 6 Addition Means

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[Procedure amendment]

[Submission date] November 16, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H04Q 3/00 9076-5K (72) Inventor Hiromi Ueda 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. A p-bit counter is driven by an x-divided clock fnx of a network clock fn, and the information latched every N counts of a clock fs of a signal to be transferred is transferred to a receiving side for reception. On the side, a means for selecting one of the received transfer information value and the predicted information value and outputting it as the current transfer information value; a first storage means for storing the current transfer information value and outputting it as the previous transfer information value;
A means for obtaining a difference value between the current transfer information value and the previous transfer information value, a second storage means for storing n difference values, and a next difference from the n difference values stored by the second storage means. It is characterized by further comprising means for predicting a value and outputting it as a prediction difference value, and means for outputting the prediction information value from the prediction difference value and the previous transfer information value output from the first storage means. SRTS control method.