JPH0738277B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a read-only semiconductor memory device, and is particularly used for a mask ROM having a NAND structure.

(Prior Art) Generally, semiconductor memory devices have various structures, but mask ROMs for writing data during the manufacturing process are well known and widely used. This mask
There are various types of ROM configurations and formation methods,
A large capacity mask ROM has a NAND structure as shown in FIG. That is, between the power supply V _DD and the ground point, for example, a depletion type MOS transistor L1, a selection MOS transistor (enhancement type) S1, which functions as a load element, and memory cell MOS transistors M1 to M8 are connected in series. Above MOS transistor L
The gate of 1 is connected to the connection point (node N1) between the MOS transistor L1 and the selection MOS transistor S1, and the gate of the selection MOS transistor S1 is composed of memory cell MOS transistors M1 to M8. A signal X for selecting is supplied. Also, the MO for the above memory cells
Signals W1 to W8 for selecting one memory cell MOS transistor in the memory block 11 are supplied to the gates of the S transistors M1 to M8, respectively. And
By supplying the potential of the node N1 to the sense amplifier 12 and amplifying it, the stored data is read from the selected memory cell MOS transistor.

In a mask ROM with such a configuration, M
Whether to make the OS transistors M1 to M8 enhancement type,
“1” of data depending on whether to use depletion type,
Write "0". In the circuit of FIG. 7, the memory cell MOS transistors M2 and M4 are depletion type,
Assuming that the memory cell MOS transistor M4 is selected, as shown in the timing chart of FIG. 8, the signal X is set to "1" level, the signals W1 to W3 and W5 to W8 are set to "1" level, and the signal W4 is set. To “0” level. As a result, the selection MOS transistor S1 and the memory cell MOS transistors M1 to M3 and M5 to M8 are turned on. Further, since the memory cell MOS transistor M4 is a depletion type, the transistor M4 is also turned on. Therefore, the node N1 is discharged, and the sense amplifier 12 detects and amplifies it to read the stored data. Next, when the memory cell MOS transistor M3 is selected, the signal W3 is set to the “0” level and all other signals are set to the “1” level.
Then, since the memory cell MOS transistor M3 is of the enhancement type, it is turned off, the discharge path of the node N1 is cut off, and the node N1 is charged by the load MOS transistor L1. Data is read from the memory cell MOS transistor M3 by detecting and amplifying this with the sense amplifier 12.

However, if "1" and "0" of data are stored depending on whether the memory cell MOS transistor is the enhancement type or the depletion type, the number of the enhancement type MOS transistors in the memory cell block 11 and the depletion type are stored. If the ratio of the number of MOS transistors of the same type is different, the magnitude of the current flowing through the memory cell block 11 is different. In other words, the discharge speed of the node N1 and the potential of the "0" level at the time of discharge are the memory cell MOSs connected in series
It depends on the ratio of the number of enhancement type and depletion type MOS transistors.

For example, as shown in FIG. 9A, a memory cell block
When the memory cell MOS transistors M1 to M7 in 11 are enhancement type and only the transistor M8 is depletion type, when the memory cell MOS transistor M8 is selected, all other transistors M1 to M7 are enhancement type. Therefore, the current flowing through the memory cell block 11 is the smallest. On the other hand, as shown in FIG. 9B, the memory cell MO that constitutes the memory cell block 11
When all the S transistors M1 to M8 are depletion type, the memory cell current is the largest. This is because the depletion type MOS transistor has a negative threshold voltage, so that the depletion type MOS transistor can flow more current than the enhancement type if the potentials of the signals W1 to W8 are the same. Therefore, in the circuit as shown in FIG. 7, the discharge speed becomes the slowest when the data is read from the memory cell block 11 as shown in FIG. 9 (a). There is a drawback that the data read speed is determined by.
Since the current flowing through the memory cell block is the smallest at this time, it is necessary to determine the current drive capacity of the load transistor L1 accordingly.
The current driving capacity of the node N1 cannot be increased and the charging of the node N1 is also delayed.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor memory device, the current flowing through the memory cell block depends on the ratio of the number of enhancement type and depletion type of the memory cell MOS transistors forming the memory cell block. However, if there are many enhancement type MOS transistors for memory cells that constitute a memory cell block, there is a drawback that the read speed decreases. In addition, since it is necessary to set the current driving capability of the load transistor in accordance with such a memory cell block, it is difficult to increase the read speed even in a memory cell block that often has a depletion type as a memory cell MOS transistor. is there.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a semiconductor memory device which can take a large amount of current flowing through a memory cell block and improve the reading speed.

[Structure of Invention]

(Means for Solving Problems) That is, according to the present invention, in order to achieve the above object, a memory cell MOS in a memory cell block is provided.
Data with more "1" or "0" is assigned to the transistor in the depletion type, and the memory cell MOS transistor is connected between the selection MOS transistor for selecting this memory cell block and the memory cell MOS transistor. A MOS transistor for bit check is provided to store whether or not the conductivity type is assigned.

(Operation) According to such a configuration, since the number of depletion type MOS transistors in the memory cell block can be always more than half, it is possible to increase the current flowing through the memory cell block and improve the read speed.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 7 are designated by the same reference numerals, and the selection MOS in FIG.
A bit check MOS transistor CT whose conduction is controlled by a signal C is provided between the transistor S1 and the memory cell MOS transistor M1. This bit-check MOS transistor CT has one memory cell block 11
It stores which one of the stored data, "1" or "0", is assigned to the depletion type MOS transistor. That is, the depletion type or the enhancement type stores the data "1" for each memory cell block 11. That is, if the number of “1” s stored in one memory cell block 11 is large, the data of “1” is assigned to the depletion type, and if the number of “0s” is large, the data of “0” is depleted. Assigned to. By doing so, more than half of the memory cell MOS transistors M1 to M8 in the memory cell block 11 are of the depletion type.

Hereinafter, this will be described in detail with reference to FIG. In the example shown in FIG. 2, the number of “1” s and “0s” and the transistors corresponding to “1” s and “0s” in the case where eight memory cell MOS transistors are present in the memory cell block 11. The types and types of bit check transistors are shown. For example, when there are two "1" data and six "0" data, as in No. 3, the "0" data is transferred to the depletion type (D) MOS transistor.
"1" level data is assigned to each enhancement type (E) MOS transistor. Then, this is stored by making the bit check MOS transistor CT an enhancement type. Also, as shown in No. 6, when there are 5 "1" data and 3 "0" data,
Data of "1" is assigned to the depletion type MOS transistor, and data of "0" is assigned to the enhancement type MOS transistor. Then, this is stored by making the bit check MOS transistor CT a depletion type. Also, as shown in No. 5, when the data of “1” and the data of “0” are the same, the data of “1” is assigned to the depletion type MOS transistor and the data of “0” is assigned to the enhancement type MOS transistor. , Make the bit check MOS transistor CT a depletion type.

According to such a configuration, since the number of depletion type MOS transistors in the memory cell block 11 can be always more than half, the current flowing through the memory cell block 11 can be increased and the load transistor L1 also has a large current driving capability. Can be used, so the reading speed can be greatly improved.

Although FIG. 2 illustrates the case where eight memory cell MOS transistors are formed in the memory cell block 11, the same applies to other numbers such as 16 or 32. Yes.

FIG. 3 shows a semiconductor memory device actually formed by arranging the memory cell blocks 11 shown in FIG. 1 in a matrix. In FIG. 3, 13 and 14 are memory cell arrays, and the memory cell arrays 13 and 14 are further divided into a plurality of arrays 13 ₁ , 13 ₂ and 14 ₁ , 14 ₂ . The selection transistor S1R constituting these memory cell arrays 13, 14, S2R, ... and S1L, S2L, ... respectively,
The output signals X1R, X2R, ... And X1L, X2L ,. Also, bit check MOS
The transistors CT1R, CT2R, ... And CT1L, CT2L, .. are output signals C1R, C2R, ... And C1L, C2L ,.
Conduction is selectively controlled by. Similarly, MO for memory cells
The S transistors M1R, M2R, ..., M8R and M1L, M2L, ..., M8L are also output signals W11R, W12R ,.
Conduction is selectively controlled by 18R and W11L, W12L, ..., W18L. 16 is a column decoder, and the output signal Y1 of this column decoder 16 is
, Rn, Y2R, ..., YnR and Y1L, Y2L ,. Select gate CG1R, CG2R, ..., C above
One end of each of GnR and CG1L, CG2L, ..., CGnL is commonly connected to each of the arrays 13 ₁ , 13 ₂ , 14 ₁ and 14 _2, and a load MOS transistor L1 is connected between these common connection points and the power supply V _DD. , L1, ... are provided. Each load MOS transistor L above
One end side node N1 of L1, ...
Sense amplifier connected to array 13 ₁ with 12, ...
12 Output D1R, and output D1L of the sense amplifier 12 connected to the array 14 ₁ each of which is supplied to the data decision circuit 17 _1. The data judgment circuit 17 ₁ is composed of an inverter 19 and a P-channel type MOS transistors Q1~Q4 and N-channel type MOS transistor Q5~Q8 Prefecture of the read stored data from the MOS transistor for the memory cell of one array Is inverted or non-inverted depending on whether the bit check MOS transistor of the other array is a depletion type or an enhancement type, and the stored data of the selected memory cell MOS transistor is determined and output to an output buffer (not shown). Similarly, each output of the sense amplifier 12 connected to the array 13 ₂ D2R, and output D2L of the sense amplifier 12 connected to the array 14 ₂ is supplied to the data decision circuit 17 _2. This data judgment circuit 17 ₂ has the same configuration as the data judgment circuit 17 ₁ described above, and the stored data read from the memory cell MOS transistor of one array is used to determine whether the bit check MOS transistor of the other array is a depletion type. MOS for memory cell selected by inverting or non-inverting depending on enhancement type
The data stored in the transistor is determined and output to an output buffer (not shown).

As shown in the figure, in the circuit of FIG. 3, two memory cell arrays 13 and 14 are present on the right side and the left side of the row decoder 15, but the MOS transistor for bit check of the data of the memory cell array 13 on the right side corresponds to the left side. The bit check MOS transistor for data in the left memory cell array 14 is incorporated in the corresponding memory cell array 13 on the contrary, in the memory cell array 14 . For example, the bit check MOS transistor CT1R is a memory cell M
1L to M8L, and transistor CT1L is for memory cells M1R to M8R. As described above, in the configuration example of FIG. 3, the row decoder 15 is sandwiched between the left and right sides, and the memory cell blocks existing at symmetrical positions on the left and right sides have bit check MOS transistors for each other. There is. However, this is a circuit type, and it is not necessary to arrange them symmetrically in terms of pattern.

Next, the operation of the circuit configured as described above will be described with reference to the truth table shown in FIG. D1L and D1R are the data read by the sense amplifiers 12 and 12 as shown in FIG. 3, and the sense amplifiers 12 and 12 are "when the memory cell composed of the depletion type MOS transistor is selected. Data of "0" is output, and data of "1" is output when a memory cell including an enhancement type transistor is selected. Now, when the address signal A0 is "0", assuming that the data of the memory cell is read from the cell array 14 on the left side and the bit check data is read from the cell array 13 on the right side, the data D1L is read from the cell array on the left side. The data D1R is the data read from the cell array on the right side. Z1 is data output from the data determination circuit 17 ₁ to the output buffer based on these data D1L and D1R. The data judgment circuit 17 ₁ shown in FIG. 3 is constructed so as to satisfy the truth table. When the data D1L read by the sense amplifier 12 is “0” and D1R is also “0”, the memory cell storage data and bit check data D1R is “0”, so the memory cell MOS transistor and bit check The MOS transistor for use is a depletion type. Therefore, as shown in FIG. 2, the memory cell stores "1" data. Therefore, the output Z1 is "1". On the other hand, the output D1L of the sense amplifier 12 is "1" and D1R is "0".
In this case, the MOS transistor for the memory cell is the enhancement type. Also, since the bit check MOS transistor is a depletion type,
The transistor stores "0", and the output Z1 is "0". Also, the output D1L of the sense amplifier 12 is "0" and D1R is "1".
At this time, since the memory cell MOS transistor is a depletion type and the bit check MOS transistor is an enhancement type, the memory cell MOS transistor stores "0" and the output Z1 is "0". Furthermore, when the outputs D1L and D1R of the sense amplifier 12 are both “1”,
MOS transistor for memory cell and M for bit check
Since the OS transistor is the enhancement type, the memory cell MOS transistor stores "1". Therefore, the output Z1 is set to "1".

The same applies when the address signal A0 is "1", where D1R is memory cell data and D1L is check data. In this way, the bit check data identifies whether it is an enhancement type MOS transistor or a depletion type MOS transistor that stores "1" or "0" in each memory cell block.

In the above description, when the address signal A0 is “0”, data is read from the memory cell in the left memory cell array 14 , and when the address signal A0 is “1”, the data in the right memory cell array 13 is read. Although the data is read from the memory cell, the present invention is not limited to this. When data is read from a certain memory cell block, the bit having the bit check data existing for the memory cell block is simultaneously read from the bit. The check data may be read out.

Next, a case where data is read from the memory cell M1R will be described as an example with reference to FIG. At this time, the column decoder
16 output signals Y2R, Y2L are "1", other output signals Y1R, Y1L, Yn
R and YnL are all “0”. Therefore, select gate CG2R,
CG2L is turned on. Also, the output signal of the row decoder 15
Set X1R and X1L to the "1" level, and set X2R, ..., X2L, ... to the "0" level. This allows the signals X2R, ..., X2
The MOS transistors S2R, ..., S2L, ... To which L, ... Are supplied are turned off. On the other hand, the MOS transistors S1R and S1L to which the signals X1R and X1L are supplied are turned on. The signal C1R for controlling the bit check MOS transistor connected to the selected memory cell MOS transistor M1R is at "1" level, and the bit check signal corresponding to the memory cell MOS transistor M1R on the opposite side of the row decoder 15 is used. MOS transistor CT
The signal C1L controlling 1L is at "0" level. Signal W11R ~ W
Signal W11 for the MOS transistor M1R selected from 18R
Only R is at "0" level and all other signals are at "1" level. On the other hand, signals W11L to W18L that oppose these memory cell MOS transistors with row decoder 15 in between are all at "1" level. Therefore, the right memory cell array 13
Then, the storage data of the memory cell M1R whose gate is at the "0" level is read, and the sense amplifier 12 detects this and outputs the "1" level. On the other hand, in the memory cell array 14 on the left side, data is read from the bit-check MOS transistor CT1L whose gate is at “0” level, and the bit-check MOS transistor is an enhancement type. When this is detected, "1" level is output. Therefore, the sense amplifier 12,1
Since the outputs of 2 are both at "1" level, the data judgment circuit 1
The output signal Z1 of 7 ₁ goes to "1" level, and the MOS
It can be seen that the storage data of the transistor M1R is "1".

FIG. 6 shows the signals X1R, C1R, W11R to W18R as described above,
In the truth table of X1L, C1L, W11L to W18L, the above signals are generated from the address signals A0, A1, A2, A3 in this example. That is, the circuit may be assembled so as to satisfy the truth table. Also, the truth table that outputs the signals X1R, X2R, ... Is not shown, but this is the same as the conventional one.
Addresses such as A4 and A5 may be added so that one of them is selected according to the memory cell capacity. Also, in FIG. 6 above, one memory cell block is composed of eight memory cell MOS transistors,
For example, when the transistor is composed of 16 or 32 transistors, an address signal may be added corresponding to the transistor so that the same function is provided.

With such a configuration, since more than half of the memory cell MOS transistors forming one memory cell block can be of the depletion type, a larger amount of current can be set in the memory cell block than in the conventional case, and the load MOS can be set.
Since the transistor L1 having a large current driving capability can be used, the reading can be performed at higher speed.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain the semiconductor memory device capable of increasing the current flowing through the memory cell block and improving the reading speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an extracted memory cell portion of a semiconductor memory device according to an embodiment of the present invention, and FIG.
FIG. 3 is a diagram for explaining the operation of the circuit shown in FIG.
Circuit diagrams of a semiconductor memory device constructed by using the circuit shown in FIG. 4, FIGS. 4 to 6 are diagrams for explaining the operation of the circuit shown in FIG. 3, and FIGS. 7 to 9 are conventional diagrams. It is a figure for demonstrating a semiconductor memory device. S1, S1R, S2R, ..., S1L, S2L, ... MOS transistor for selection, M
1, M2, ..., M8, M1R, M2R, ..., M8R, M1L, M2L, ..., M8L ... MOS transistor for memory cell, 11 ... Memory block, CT, CT1R, C
T2R, ..., CT1L, CT2L, ... Bit check MOS transistors, 17 ₁ , 17 ₂ ... Data judgment circuit.

Claims (1)

[Claims] 1. A selection transistor, and a plurality of memory cell blocks each including the selection transistor and a plurality of memory cell transistors connected in series between the selection transistor and a reference potential. In a semiconductor memory device that stores data according to whether the memory cell transistor is an enhancement type or a depletion type, the memory cell transistor in the corresponding memory cell block is connected in series and stores the stored data. A bit check transistor for storing which "1" or "0" is assigned to the depletion type, a first selecting means for selecting a memory cell transistor in the memory cell block, and a first selecting means. The bit check corresponding to the memory cell block selected by Second selection means for selecting a transistor for the memory cell, storage data read from the transistor for the memory cell selected by the first selection means, and the second data
Whether the data stored in the selected memory cell transistor is "1" or "0" based on the two data including the bit check data read from the bit check transistor selected by the selection means. A data determining means for determining and outputting, and of the data of “1” or “0” to be written to the plurality of memory cell transistors connected in series in the memory cell block, the data having the larger number is selected. A semiconductor memory device characterized by being assigned to a depletion type.