JPH0737340A - Data decoder - Google Patents

Abstract

PURPOSE:To achieve a quick following of the predicted value for viterbi decoding and the improvement in control accuracy by comparing the error between the amplitude of a transmitted signal and the predicted amplitude with a reference error, determining the correcting width, and correcting the error with the selected correcting width. CONSTITUTION:A reproduced signal input 46 is inputted in a reproducing clock period, and the amplitude value is inputted as digital information. The value is compared with values Tn1-Tn0, which are controlled a predicted sample-value control circuit 53. The absolute values E2-E0 of the errors and the polarities of the errors S2-S0 are outputted. A tolerance comparing circuit 41 and a decoded-path judging circuit 42 output decoded information 48, which is delayed by (m) bits from the input 46. In an error comparing circuit 12, the absolute values of the errors E2-E0 are compared with a reference error (e) of an error setting circuit 11. The result is outputted to an error-comparing-information selecting circuit 14 by delaying the result by the (m) bits through a delay circuit 13. One piece of error comparison information is selected from the combination of the decoded pieces of the information delayed by the (m) bits and (m-1)bits from the input 46. One of the large and small correcting widths is selected by a correcting-width selecting circuit 15. The predicition-sample-value control circuit 53 changes the predicted sample value in accordance with a polarity selecting circuit 52 and the correcting-width selecting circuit 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding device,
In particular, the present invention relates to a data decoding device that applies Viterbi decoding in order to eliminate the influence of inter-code interference of transmission signals.

[0002]

2. Description of the Related Art Reduction of transmission errors due to the influence of intersymbol interference or the like is a major problem in data transmission systems such as broadcasting, communication and recording media, and Viterbi decoding is considered to be a means for overcoming this problem. ing. As a data transmission system, the data reproduction method applying Viterbi decoding to the data reproduction from the optical disk medium is, for example, "High density recording by Viterbi decoding", Technical Report of the Institute of Television Engineers, Vol.14, No.64,
pp.13-17, Vir'90-63, (Sep.1990) and "Optimization experiment of reproduction equalizer in digital magnetic recording", Technical Report of IEICE, Vol.14, No.47, pp.7 ~ 12, Vir'90-49, (Sep. 1990). In the Viterbi decoding shown in these, signal detection is performed by maximum likelihood decoding in which inter-code interference is inversely used to select the decoding path with the highest likelihood, and when the error rate for S / N uses waveform equalization. Can be smaller.
A specific example of the Viterbi decoding circuit according to these conventional techniques is disclosed in, for example, Japanese Patent Laid-Open No. 4-21973, but here, the recording / reproducing characteristics of the optical disk are regarded as class I (1 + D) partial response characteristics and Viterbi decoding is performed. The prior art will be described for the case where decoding is applied.

FIG. 9 is a block diagram of a recording / reproducing system of an optical disk, and shows the position of Viterbi decoding. In FIG. 9, 1 is a precoder, 2 is a characteristic model of an optical disc, 3 is a Viterbi decoder, 4 is recording data input, and 5 is reproduction data output. The optical disc characteristic model 2 is 21 optical discs,
It consists of 6 noise inputs, 22 adders and 23 filters. The recording data input from the recording data input 4 is recorded on the optical disc 21 after the precoder 1 has performed 1 / (1 + D) arithmetic processing. The characteristics of the optical disc can be modeled by a random noise adder 22 having an average value of zero and a filter 23 having a class I (1 + D) partial response characteristic. The reproduced signal from the modeled optical disk is input to the Viterbi decoder 3 and reproduced data 5 is output by the Viterbi algorithm described below.

FIG. 10 shows an example of a reproduced waveform corresponding to an isolated pit in the partial response characteristic of class I (1 + D). The amplitude value is 1.0 at sample points t = 0 and t = 1T, and the other sample points are It is 0.0. The reproduced signal waveform from the optical disk can be generated by superposing the isolated reproduced waveforms corresponding to the data series.

FIG. 11 shows an example of Viterbi decoding prediction sample values based on the isolated reproduction waveform of FIG. 10, and three prediction sample values of T0 to T2 are obtained by superimposing isolated reproduction waveforms by a combination of adjacent 2 bits. Set. That is, when T0 is the bit combination "00", T1 is the bit combination "01" or "1".
In the case of 0 ", T2 is the respective prediction sample value in the case of the bit combination" 11 ". E0 to E2 are the absolute values of the errors between the reproduced signal amplitude Yn and these three prediction sample values T0 to T2,
The Viterbi decoding handled here performs maximum likelihood decoding using these values to find the data sequence with the highest probability. Details of the Viterbi algorithm are as follows.

Decoding passes "0" and "at some time n"
If the metric corresponding to 1 "is m _n (1), m _n (0), then m _n (1) = min {m _n-1 (1) + E2, m _n-1 (0) + E1} m _n (0) = min {m _n-1 (1) + E1, m _n-1 (0) + E0} where min is a function that chooses the smaller value, and if the metric is small, degrees means that high. If these metric difference and _{Q n Q n = m n (} 1) -m n (0) = min {Q n-1 + E2, E1} -min {Q n-1 + E1, E0}, where Q _n-1 + E2 ≦ E1 and Q _n-1 + E1 ≦ E0 the decoding path is “1”
Can be merged as Qn = E2-E1.

When Q _n-1 + E2> E1 and Q _n-1 + E1 ≦ E0, the decoding paths cannot be merged and Qn = -Q _n-1 .

In the case of Q _n-1 + E2> E1 and Q _n-1 + E1> E0, it can be merged as the decoding path "0", and Qn = E1-E0.

FIG. 12 is a state transition diagram and a trellis diagram for four states (S00 to S11) of a combination of two bits of a reproduced signal. The broken line shows the state transition of bit "0", and the solid line shows the state transition of bit "1". For example, if the combination of two bits of the reproduction signal is "00" and the state is S00, the next bit can have the state S00.
It also indicates S01. FIG. 13 is a state transition diagram and a trellis diagram when S00 and S10 and S01 and S11 of the four states (S00 to S11) of FIG. 12 are put together into two states. It is determined that the decoding path connects to S0 under the above conditions, it is not determined whether the decoding path connects to S0 or S1 under the conditions, and it is determined that the decoding path connects to S1 under the conditions. To do. Decoded data is obtained by repeatedly performing this likelihood determination to obtain a surviving path.

FIG. 7 is a diagram showing an example of a Viterbi decoding circuit corresponding to the above-mentioned Viterbi algorithm applied to an optical disk device. In FIG. 7, a block 40 indicated by a broken line is a prediction sample value comparison means, 41 is a likelihood determination means, 42 is a decoding path determination means, and 43, 44, 45 are levels corresponding to the above-mentioned prediction sample values of T0 to T2. An input, 46 is a reproduction signal input, 47 is a clock input, and 48 is a data decoding output. In the predicted sample value comparison means 40, 301 to 303 are absolute error detection circuits,
In the likelihood determination means 41, 304 and 305 are addition circuits, and 306 and 308.
Is a subtracting circuit, 307 is an inverting circuit, 309 and 310 are comparing circuits, 311
Is a 3-input selection circuit, and 312 is a latch circuit. In the decoding path determination means 42, 313 and 314 are 2-input selection circuits, 31
5,316 is a register circuit.

The absolute error detection circuit 301 of the predictive sample value comparing means 40 shown in FIG. 7 takes the absolute error between the reproduced signal input 46 and the predictive sample value input 43 corresponding to the combination "11" of the adjacent bits of 2 bits to obtain the absolute error. Outputs E2. The absolute error detection circuit 302 is a combination of the reproduction signal input 46 and the adjacent bit of 2 bits.
Absolute error with the predicted sample value input 44 corresponding to 01 "or" 10 "is taken and absolute error E1 is output.
303 is a combination of the reproduction signal input 46 and two adjacent bits "0"
The absolute error from the predicted sample value input 45 corresponding to "0" is obtained and the absolute error E0 is output. The addition circuit 30 of the likelihood determination means 41.
4 adds the output Q _n-1 of the latch circuit 312, which is the metric difference 1 bit before, and the absolute error E2, and the adder circuit 305 outputs the output Q _n-1 of the latch circuit 312, which is the metric difference 1 bit before. Add the absolute error E2. The comparator circuits 309 and 310 are the output Q _n-1 + E2 of the adder circuit 304, the absolute error E1, and the adder circuit 305.
The output Q _n-1 + E1 of the above is compared with the absolute error E0, and the comparison result is output to the input selection circuit 311 and the register circuits 315 and 316 of the decoding path determination means 42. From the comparison result, the above-mentioned likelihood determination condition is obtained. Subtraction circuits 306 and 308
Is the difference between absolute error E2 and absolute error E1 E2-E1 and absolute error E1
And the difference E1-E0 of the absolute error E0 is output to the 3-input selection circuit 311. The inverting circuit 307 inverts the polarity (positive or negative) of the output Q _n-1 of the latch circuit 312, which is the metric difference one bit before, and outputs the inverted signal to the 3-input selection circuit 311. The 3-input selection circuit 311 is a subtraction circuit 30.
According to the comparison results of the comparison circuits 309 and 310, only one input which is the metric difference after the likelihood determination is selected from the three inputs from the 6,308 and the inverting circuit 307 according to the comparison result of the comparison circuits 309 and 310. The latch circuit 312 latches the metric difference selected by the 3-input selection circuit 311, and the output thereof is used for determining the likelihood of the next bit. The register circuits 315 and 316 of the decoding path determining means 42 record the outputs of the comparison circuits 309 and 310 at the clock cycle of the clock input 37, respectively, and at the same time record the outputs of the 2-input selection circuits 313 and 314. Two-input selection circuits 313 and 314 switch respective register outputs of a plurality of bits for switching serial or parallel shift of register circuits 315 and 316 according to outputs of comparison circuits 309 and 310. That is, the comparison circuits 309 and 3
When the output of 10 is the above likelihood determination condition, the two-input selection circuits 313 and 314 both operate so as to switch to the register output from the register circuit 315. Further, under the likelihood determination condition, the 2-input selection circuit 313 operates so as to switch to the register output from the register circuit 316, and the 2-input selection circuit 314 operates so as to switch to the register output from the register circuit 315. Further, under the likelihood determination condition, both 2-input selection circuits 313 and 314 operate so as to switch to the register output from the register circuit 316. As a result, the outputs of the register circuits 315 and 316 coincide with each other under the likelihood determination condition and the data decoding before that time is confirmed. Also, when the likelihood determination condition is met, the two do not match and are indeterminate. Since the number of register stages of 315 and 316 in the normal register circuit is more than the maximum number of continuous likelihood judgment conditions, decoding output
38 is obtained by delaying the number of register stages from the likelihood determination. The decoded output 48 is output from the register circuit 316 because the register circuits 315 and 316 always have the same output if the likelihood determination condition is merged into either "1" or "0". This is because the decoding output 48 is representative.

In this Viterbi decoding circuit, for example, a low-frequency level fluctuation occurs in a reproduction signal from an optical disk,
When the predicted sample value of Viterbi decoding is deviated due to the non-linear distortion due to heat, a data error due to decoding is likely to occur. Therefore, it is necessary to adaptively control the predicted sample value according to the fluctuation of the reproduction signal. As a standard algorithm for this adaptive control, there is a control method called a sine algorithm. In this method, the predicted sample value corresponding to the Viterbi state of the decoded data is increased or decreased by a fixed correction width α depending on the polarity of the difference between the reproduced signal and the predicted sample value. That is, Tn _i = T (n−1) _i + α · SgnT (nm) _i . Here, n is a control sample point, m is the Viterbi decoding delay bit number, and i is the Viterbi state (2,1,0).

FIG. 8 is a block diagram of the adaptive control of the conventional Viterbi decoding by the sign algorithm. In FIG.
Reference numeral 50 denotes a Viterbi decoding circuit, which is composed of a predicted sample value comparison circuit 40, a likelihood comparison circuit 41, and a decoding path determination circuit 42 as in the circuit shown in FIG. Reference numeral 51 is a polarity data delay circuit, 52 is a polarity data selection circuit, and 53 is a predicted sample value control circuit. 46 is the input value of the playback signal, 43 to 45
Is the default value of the predicted sample value, 48 is the decoded output,
It is shown by the same reference numeral as the circuit shown in FIG.

In FIG. 8, the prediction value comparison circuit 40 compares the absolute error E2 to E0 between the input value 46 of the reproduced signal and the three kinds of prediction sample values Tn2 to Tn0 output from the prediction sample value control circuit 52 with a likelihood comparison circuit. At the same time as outputting to 41, the polarity of error S2 ~
The S0 is output to the polarity data delay circuit 51. Likelihood comparison circuit
41 performs likelihood determination based on absolute errors E2 to E0, and outputs the likelihood determination result to the decoding path determination circuit 42. Decoding path determination circuit 42
The decoding path is determined from the likelihood determination result, and the decoding data
Is output. The decoded data 48 is delayed by m bits from the time when the reproduced signal is input. The polarity data delay circuit 51 shifts the polarity bits S2 to S0 of the error between the reproduction signal input and the three types of predicted sample values Tn2 to Tn0 by the delay amount m bits by which the decoded data is obtained from the reproduction signal input, and the respective m bits. The delayed polarity data is output to the polarity data selection circuit 52.
The polarity data selection circuit 52 delays the delayed polarity data from S2 to S0 by m bits in the decoding path determination circuit 42 and m.
The selected polarity data is output to the predictive sample value control circuit 53 by selecting the 2-bit combination of the data delayed by -1 bit. The predicted sample value control circuit 53 selects the predicted sample value corresponding to the polarity data selected by the polarity data selection circuit 52, and increases / decreases by a fixed correction width α according to the algorithm described above. That is, m of the decoding path determination circuit 42
If the 2 bits delayed by m-1 bits are "11", the polarity data S2 delayed by m bits is selected, and the predicted sample value Tn2 is increased or decreased by the correction width α depending on whether the polarity is positive or negative. If the m and m-1 bits delayed by 2 bits of the decoding path determination circuit 42 are "10" or "01", the m-bit delayed polarity data S1 is selected, and the predicted sample value Tn1 is corrected according to the polarity of the polarity. Increase or decrease by width α. Further, when the m and m-1 bits delayed by 2 bits of the decoding path determination circuit 42 are "00", the m-bit delayed polarity data S0 is selected and the predicted sample value Tn0 is increased or decreased by the correction width α depending on the polarity of the polarity. .

According to this adaptive control configuration, the prediction sample value adaptively fluctuates according to the level fluctuation of the reproduction signal, so that decoding errors can be reduced as compared with the case where the prediction sample value is fixed.

[0016]

However, even in this adaptive control type Viterbi decoding system, the correction width α for changing the predicted sample value is always constant. Therefore, if the correction width α is large with respect to the level fluctuation of the reproduced signal, the tracking speed is large. Is faster, but the adaptation accuracy is coarser. If the correction width α is small, the adaptation accuracy becomes fine, but the tracking speed becomes slow. In particular, when the deviation of the initial value of the predicted sample value with respect to the reproduction signal is large, a small correction width α lengthens the time for which the deviation is eliminated, and a data error during that time is likely to occur. Further, when the correction width α is large, the time for eliminating the deviation becomes short, but the deviation does not become smaller than the value of the correction width α, and a data error is likely to occur with respect to a slight level fluctuation of the reproduction signal. Therefore, it is desirable to adaptively fluctuate the correction width α in accordance with the fluctuation characteristic of the reproduced signal, but the prior art has not presented a technique for an effective adaptive control method of a predicted sample value in Viterbi decoding.

Further, in the conventional adaptive control type Viterbi decoding system, the correction widths of a plurality of prediction sample values are all the same, so that the judgment of the data "0" or "1" is clearly made in the decoding pass judgment of the reproduced signal. Adaptive control of high level predicted sample values and low level predicted sample values with respect to the amplitude value of the signal input, and the determination of the data "0" or "1" is delicate. Adaptive control is also modified under the same conditions. Therefore, if adaptive control is performed with a large correction width for all predicted sample values,
Since the correction range of the predicted sample value at the intermediate level, which makes the determination of the data "0" or "1" delicate, becomes large, it becomes difficult to make an accurate decoding path determination, and there is a problem that the decoded data error increases.

An object of the present invention is to effectively control adaptively the predicted amplitude value in accordance with the fluctuation characteristics of a transmission signal in a data decoding apparatus which solves the above-mentioned problems of the prior art and applies adaptive control type Viterbi decoding. It is to provide a data decoding device. Another object of the present invention is to provide a data decoding device that reduces decoded data errors by adaptively controlling a plurality of predicted amplitude values with individual correction widths.

[0019]

In order to achieve the above object, in a data decoding device to which adaptive control type Viterbi decoding is applied, the first aspect of the present invention is to detect an error between a transmission signal amplitude value and a predicted amplitude value. Detecting means, reference error setting means for setting the reference value of the error, error comparing means for comparing the detection error and the reference error, and a plurality of correction widths for correcting the predicted amplitude value are provided, The correction width selection means for switching the correction width and the prediction value control means for correcting the predicted amplitude value with the switched correction width are provided. Further, in the second aspect of the present invention, the correction width selection means provides a plurality of correction widths for correcting the predicted amplitude value, and the predicted amplitude value to be controlled, which is determined by the decoded data string, is at an intermediate level or above or below the transmission signal. The correction width is switched depending on the level.

[0020]

In the first aspect of the present invention, the error comparison means compares whether the error between the transmission signal amplitude value and the predicted amplitude value is larger or smaller than the reference error and outputs the error comparison result. The correction width selection means provides a plurality of correction widths and determines the correction widths from the error comparison result. The predicted value control means corrects the predicted amplitude value corresponding to the decoded data string with the selected correction width. Thereby, when the error between the transmission signal amplitude value and the predicted amplitude value corresponding to the determined decoded data string is larger than the reference value, a large correction width can be selected, and when the error is small, a small correction width can be selected. Not only the predicted value of Viterbi decoding can quickly follow the level fluctuation of the transmission signal, but also the control accuracy can be improved.

In the second aspect of the present invention, the correction width selecting means sets the predicted amplitude value to be controlled, which is determined by the decoded data string, to the level above or below that when the predicted amplitude value which is the intermediate level of the transmission signal is selected. The correction width is switched depending on whether the predicted amplitude value is selected. As a result, the correction width of the predicted amplitude value, which is the intermediate level of the transmission signal, which slightly affects the decoding path judgment, is made finer than the correction width of the predicted amplitude value, which is the upper or lower level. The error in the decoded data can be reduced as compared with the case where the correction width of the amplitude value is the same.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of a data decoding device to which the adaptive control type Viterbi decoding according to the first aspect of the present invention is applied,
The reproduction of the optical disc will be described as an example.

FIG. 8 used in the description of the prior art in FIG.
The same parts as those shown in are indicated by the same reference numerals, and the description of these parts will be omitted. In FIG. 1, reference numeral 11 is a reference error setting circuit, which sets a reference error value e as a reference for comparing the magnitude of error data between the reproduced signal input value and the predicted sample value. Reference numeral 12 denotes an error comparison circuit, which determines the errors E2 to E0 between the reproduction signal input value output from the prediction sample value comparison circuit 40 and the plurality of prediction sample values as the reference error value e set by the reference error setting circuit 11. It compares and outputs the comparison result. An error comparison data delay circuit 13 shifts the error comparison data by the data delay amount determined by the decoded data. Reference numeral 14 is an error comparison data selection circuit, and one error comparison is made from a combination of decoded data delayed by m bits and m-1 bits from the reproduction signal input determined by the decoding path determination circuit 42 from a plurality of delayed error comparison data. Select data. A correction width selection circuit 15 determines the adaptive control correction width corresponding to the selected error comparison data.

In FIG. 1, the reproduction signal input 46 receives the amplitude value as digital data at the reproduction clock cycle.
The sample value comparison circuit 40 uses the reproduction input value and a plurality of predicted sample values Tn2 to Tn controlled by the predicted sample value control circuit 53.
Compared with n0, the absolute value of error E2-E0 and the polarity of error S2-S0
Is output. Likelihood comparison circuit 41 and decoding path determination circuit
42 outputs the decoded data 48 delayed by m bits from the reproduction signal input by the same operation as in FIG. The error comparison circuit 12 compares the absolute values E2 to E0 of the error from the sample value comparison circuit 40 with the reference error e set by the reference error setting circuit 11, and outputs the error comparison data to the error comparison data delay circuit 13. The error comparison data delay circuit 13 delays the error comparison data by m bits and outputs the delayed error comparison data to the error comparison data selection circuit 14. Similar to the operation of the polarity data selection circuit 52 described with reference to FIG. 7, the error comparison data selection circuit 14 selects a plurality of error comparison data delayed by m bits from decoded data delayed by m bits and m-1 bits from the input of the reproduction signal. One error comparison data is selected according to the combination. The correction width selection circuit 15 selects one correction width from the large and small types of correction widths a and b according to the error comparison data selected by the error comparison data selection circuit 14. The predictive sample value control circuit 53 determines the predictive sample value to be controlled, which is determined by the combination of the decoded data delayed by m bits and m-1 bits from the reproduction signal input, from the polarity data selection circuit 52 and the correction width selection circuit 15 Vary according to the correction range.

FIG. 2 is a diagram showing an example of detailed circuits of the predicted sample value control circuit 53 and the correction width selection circuit 15. In the predicted sample value control circuit 53 shown in FIG. 2, 201 to 203 are addition circuits, 204 to 206 are switching circuits, 207 to 209 are latch circuits,
210 is a decoding circuit. Further, in the correction width selection circuit 15, 211 is a polarity switching circuit, 212 is a data switching circuit, and 213 and 21.
Reference numeral 4 is a data setting circuit for setting the correction widths of a and b.

Initial prediction sample values T2 to T0 input from 43 to 45 in the prediction sample value control circuit 53 shown in FIG.
Is a switching circuit 20 for switching before and after the start of Viterbi decoding.
Before the Viterbi decoding is started via 4 to 206, they are recorded in the latch circuits 207 to 209 respectively. When Viterbi decoding starts, the switching circuits 204 to 206 operate so as to input the outputs of the adding circuits 201 to 203 to the latch circuits 207 to 209. Latch circuit
The outputs of 207 to 209 are predicted sample value control circuits shown in FIG.
The predicted sample values Tn2 to Tn0 are input to 40 and are input to the adder circuits 201 to 203, respectively. Adder circuit
201 to 203 add or subtract the outputs of the latch circuits 207 to 209 by the polarity and the correction width selected by the correction width switching circuit 15, and the outputs thereof are output via the switching circuits 204 to 206 to the latch circuit 20.
Entered in 7-209. The decoding circuit 210 decodes 2 bits of decoded data delayed by m bits and m-1 bits from the reproduction signal output from the decoding path determination circuit 42 shown in FIG. 1, and when the 2 bits are "11", the latch circuit 207, If 2 bits are "01" and "10", latch circuit 208 and 2 bits are "
In the case of "00", the latch control signal is output so as to record the corrected predicted sample value in the latch circuit 209. Therefore, the latch circuits 207 to 209 are the predicted samples in which only the latch circuit controlled by the decoding circuit 210 is corrected. Record the value.

The correction width switching circuit 15 includes data setting circuits 213 and 21.
The data switching circuit 212 switches between the correction widths a and b which are set in advance in two different sizes according to the error comparison data output from the error comparison data selection circuit 14. That is, when it is determined that the error comparison data has an error larger than the reference value e, the data setting circuit 213 is set to a large correction width a, and when it is determined to be small, the data setting circuit 214 is set to a small correction width b. . This switching output corresponds to the polarity data from the polarity data selection circuit 52 shown in FIG. 1 in the polarity switching circuit 211, and is switched to the data as it is in the case of positive polarity or the data of 2's complement in the case of negative polarity and added. Output to the circuits 201 to 203.

FIG. 3 is a diagram showing an example of variations in the reproduced signal and the predicted sample value. As shown in FIG. 3, the predictive sample value control circuit 53 shown in FIG. 2 includes a reproduced signal amplitude value and a predictive sample value to be controlled which is determined by a combination of 2 bits decoded by delaying m bits and m-1 bits. If any of the errors E2 to E0 is larger than the reference value e, a large correction width a
When the value is smaller than the reference value e, the value is increased or decreased according to the polarity with a small correction width b.

As a result, the error E2 to E0 between the initial predicted sample value of T2 to T0 set by 43 to 45 and the amplitude value of the reproduced signal.
Is large, the correction is performed with a large correction width a, so that the predicted sample value of the reproduction signal can be followed at high speed. Further, when the error E2 to E0 between the predicted sample value and the amplitude value of the reproduced signal is small, the correction is performed with a small correction width b, so that the accuracy of the predicted sample value for the reproduced signal is improved.

In this embodiment, there are two types of correction widths, a and b, but a plurality of types may be provided depending on the magnitude of the error. Further, a plurality of types of correction widths may be freely changed. Further, although one reference error e is fixed in this embodiment, a plurality of reference errors corresponding to each predicted sample value may be provided, or the reference error may be varied similarly to the control of the predicted sample value.

4 and 5 show an embodiment of a data decoding device to which the Viterbi decoding according to the second aspect of the present invention is applied.

FIG. 4 is almost the same as the data decoding apparatus shown in FIG. 1, except that the correction width selection circuit 15 receives the decoding output of the decoding path determination circuit 42.

Further, FIG. 5 is a diagram showing an example of a detailed circuit of the predicted sample value control circuit 53 and the correction width selection circuit 15 as in FIG. 2, in which the correction width selection circuit 15 has data of four types of correction widths a to d. Setting circuits 513 to 516 and a switching circuit 512 for switching these
Only different. The order of the sizes of the correction widths a to d is a>b>
c> d.

In FIG. 5, the correction width switching circuit 15 has four correction widths a preset by the data setting circuits 513 to 516.
~ D are data switching circuits 512 and error comparison data selection circuit 1
Switching is performed according to the error comparison data output from 4 and 2 bits of decoded data delayed by m bits and m-1 bits from the decoding path determination circuit 42 shown in FIG. That is, when it is determined that the error comparison data has an error larger than the reference value and the decoded data 2 bits are "11" or "00" and the decoding circuit 210 selects the correction of the predicted sample value of the latch circuit 207 or 209, , Switch to the data setting circuit 513 in which the correction width a is set, and the decoded data 2 bits are "01" or "
When the decoding circuit 210 selects the correction of the predicted sample value of the latch circuit 208 at 10 ", it switches to the data setting circuit 514 in which the correction width b smaller than a is set. Further, when the error comparison data has an error smaller than the reference value. When it is determined that the decoded data 2 bits are "11" or "00" and the decoding circuit 210 selects the correction of the predicted sample value of the latch circuit 207 or 209, the data setting circuit 515 having the correction width c is set. Switching, 2 bits of decoded data is "01" or "10"
When the decoding circuit 210 selects the correction of the predicted sample value of the latch circuit 208, the data setting circuit 516 is set to set the correction width d smaller than c. This switching output corresponds to the polarity data from the polarity data selection circuit 52 shown in FIG. 4 in the polarity switching circuit 211, and is switched to the data as it is in the case of positive polarity and is added to the data of 2's complement in the case of negative polarity. Output to the circuits 201 to 203.

FIG. 6 is a diagram showing an example of variations in the reproduced signal and the predicted sample value. As shown in FIG. 6, the predictive sample value control circuit 53 shown in FIG. 5 includes a reproduced signal amplitude value and a predictive sample value to be controlled which is determined by a combination of 2 bits decoded by delaying m bits and m-1 bits. Among the errors E2 to E0, if E2 and E0 are larger than the reference value e, the correction width a is increased or decreased, and if they are smaller than the reference value, the correction width b is increased or decreased. Further, when E1 is larger than the reference value e, it is increased / decreased with a large correction width c, and when it is smaller than the reference value, it is increased / decreased with a small correction width d. Due to such an operation, when the error E2 to E0 between the predicted sample value and the amplitude value of the reproduced signal is large and the level of the predicted sample value is above or below the amplitude value of the reproduced signal, a large correction width a Or c and the level of the predicted sample value is in the middle of the amplitude value of the reproduced signal, it is corrected with a small correction width b or d.
Judgment of decoded data "0" or "1" becomes subtle. Only the predicted sample value near the intermediate amplitude of the reproduced signal is adaptively controlled with a fine correction width, and judgment of decoded data "0" or "1" becomes clear. Since the predicted sample values above and below the reproduced signal amplitude to be judged are adaptively controlled with a rough correction range, the error rate is higher than that of the conventional method in which the predicted sample values at all levels are adaptively controlled with the same correction range. Can be reduced.

In the present embodiment, there are three kinds of predicted sample values for Viterbi decoding, but in addition to this, when the number of Viterbi decoding states is increased to increase the number of predicted sample values, similarly, the reproduced signal The correction width of the plurality of prediction sample values near the intermediate level may be made smaller than the correction width of the other prediction sample values.

[0038]

According to the first aspect of the present invention, in the data decoding device to which the adaptive Viterbi decoding is applied, the adaptive control correction width is switched according to the magnitude of the error between the reproduced signal amplitude value and the predicted sample value. Therefore, it becomes possible to follow the level fluctuation of the reproduced signal at high speed, and at the same time, the correction accuracy can be improved. Further, according to the second aspect of the present invention, the correction width of the prediction sample value near the intermediate level of the reproduction signal amplitude in which the determination of data decoding is delicate among the plurality of prediction sample values is
Since the correction width of the predicted sample values of the upper and lower levels is made finer, the error of data decoding can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a Viterbi decoding adaptive control according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a predicted sample value control according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of Viterbi decoding adaptive control according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of Viterbi decoding adaptive control according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a predicted sample value control according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of Viterbi decoding adaptive control according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a Viterbi decoding circuit.

FIG. 8 is a configuration diagram of Viterbi decoding adaptive control according to a conventional technique.

FIG. 9 is an optical disk recording / playback block diagram.

FIG. 10 is a diagram showing an example of a class 1 partial response isolated reproduction waveform.

[Fig. 11] Fig. 11 is a diagram illustrating an example of Viterbi decoded prediction sample values.

[Fig. 12] Fig. 12 is a diagram illustrating an example of a Viterbi decoding state transition diagram and a trellis diagram.

[Fig. 13] Fig. 13 is a diagram illustrating an example of a Viterbi decoding state transition diagram and a trellis diagram.

[Explanation of symbols]

 11 ... Reference error setting circuit, 12 ... Error comparison circuit, 13 ... Error comparison data delay circuit, 14 ... Error comparison data selection circuit, 15 ... Correction width selection circuit, 40 ... Sample value control circuit, 41 ... Likelihood comparison circuit, 42 ... Decoding path determination circuit, 51 ... Polarity data delay circuit, 52 ... Polarity data selection circuit, 53 ... Predicted sample value control circuit, 201-203 ... Addition circuit, 204-206 ... Switching circuit, 207-209 ... Latch circuit, 210 ... Decoding circuit, 211 ... Polarity switching circuit, 212 ... Data switching circuit, 213 to 216 ... Data setting circuit.

Claims (4)

[Claims] 1. A data decoding apparatus for applying a Viterbi algorithm to a transmission signal to perform data decoding, a prediction value setting means for setting a plurality of prediction values corresponding to the number of Viterbi states, a transmission signal and the prediction value. An error detecting means for detecting an error from the predicted value set by the setting means, a reference error setting means for setting a reference value of the error, a reference error detected by the error detecting means and a reference error setting means. Error comparing means for comparing the reference error with the reference error, correction width selecting means for switching a plurality of correction values for correcting a plurality of predicted values corresponding to the Viterbi state from the error comparison result by the error comparing means, and the correction width selecting means. A data decoding apparatus comprising: a prediction value control means for correcting a prediction value corresponding to a Viterbi state of decoded data with a correction width selected by the means. 2. A data decoding device for applying a Viterbi algorithm to a transmission signal to perform data decoding, and a prediction value setting means for setting a plurality of prediction values corresponding to the number of Viterbi states, and a Viterbi state of decoded data. A plurality of correction widths corresponding to each of the plurality of corresponding predicted values are provided, and a correction width selecting unit that switches the correction width corresponding to the prediction value determined by the combination of the decoded data strings, and the correction width selecting unit is selected. A data decoding apparatus comprising a prediction value control means for correcting a prediction value corresponding to a Viterbi state of decoded data with a correction width. 3. A polarity detecting means for detecting the polarity of the transmission signal and the predicted value set by the predicted value setting means, and a reference error value corresponding to the polarity from the polarity detecting means corresponding to the decoded data. The data decoding device according to claim 1, further comprising a reference error correction means for correcting. 4. The data decoding device according to claim 1, wherein the reference value of the error is provided individually for each of the plurality of predicted values in the Viterbi state.