JPH0732531B2 - Power converter failure detection device - Google Patents
Power converter failure detection deviceInfo
- Publication number
- JPH0732531B2 JPH0732531B2 JP61070841A JP7084186A JPH0732531B2 JP H0732531 B2 JPH0732531 B2 JP H0732531B2 JP 61070841 A JP61070841 A JP 61070841A JP 7084186 A JP7084186 A JP 7084186A JP H0732531 B2 JPH0732531 B2 JP H0732531B2
- Authority
- JP
- Japan
- Prior art keywords
- failure
- circuit
- bridge
- signal
- power converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Protection Of Static Devices (AREA)
- Inverter Devices (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、バイポーラモードFET(以下BIFETと呼ぶ)
(GE商品名IGT)やFETなどの静電誘導形自己消孤素子で
構成したブリッジ回路から成る電力変換器の故障検出回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention is a bipolar mode FET (hereinafter referred to as BIFET).
(GE product name IGT) and FET are related to the failure detection circuit of the power converter consisting of a bridge circuit composed of static induction type self-extinguishing elements.
(従来の技術) 従来のインバータ回路の一例を第3図に示す。交流電源
1をダイオード21〜26から成る整流器2により直流に変
換し、コンデンサ3により平滑化した電圧を、BIFETと
ダイオードを逆並列接続した電気弁41〜46から成るイン
バータブリッジ4により交流電圧に変換し負荷側端子U,
V,Wに供給する。インバータの運転はパルス幅変調制御
(以下PWM制御)回路5により造出された信号がアンド
回路6およびゲート駆動回路7を介してインバータブリ
ッジ4のBIFETをそれぞれ駆動する。PWM制御回路5によ
り、インバータブリッジ4の出力電圧と出力周波数を同
時に制御する場合、最近ではマイクロプロセッサを用い
てPWM信号を発生する方式が多く採用されている。PWM信
号は、アンド回路6により、故障が発生していない場合
のみゲート駆動回路7へ信号を通し、これによりゲート
駆動回路7はインバータブリッジ4の電気弁41〜46をオ
ンオフさせる。インバータブリッジ4の直流母線に接続
した電流検出器8により電流を検出し、過電流検出器9
により、過電流が流れた場合は、アンド回路6の条件入
力により、インバータブリッジ4の電気弁をすべてオフ
にしてインバータブリッジの故障電流を遮断する。(Prior Art) An example of a conventional inverter circuit is shown in FIG. The AC power supply 1 is converted into direct current by the rectifier 2 including the diodes 21 to 26, and the voltage smoothed by the capacitor 3 is converted into the AC voltage by the inverter bridge 4 including the electric valves 41 to 46 in which the BIFET and the diode are connected in anti-parallel. Load terminal U,
Supply to V and W. In the operation of the inverter, the signal generated by the pulse width modulation control (hereinafter, PWM control) circuit 5 drives the BIFET of the inverter bridge 4 via the AND circuit 6 and the gate drive circuit 7, respectively. When the output voltage and the output frequency of the inverter bridge 4 are simultaneously controlled by the PWM control circuit 5, recently, a method of generating a PWM signal using a microprocessor is often adopted. The PWM signal is passed by the AND circuit 6 to the gate drive circuit 7 only when no failure occurs, so that the gate drive circuit 7 turns on / off the electric valves 41 to 46 of the inverter bridge 4. The current detector 8 connected to the DC bus of the inverter bridge 4 detects the current, and the overcurrent detector 9
Accordingly, when an overcurrent flows, all the electric valves of the inverter bridge 4 are turned off and the fault current of the inverter bridge is cut off by the condition input of the AND circuit 6.
一方、零相変流器10により、接地電流を検出し接地故障
検出器11により接地事故が検出されたとき、アンド回路
6の入力条件をオフにして、インバータブリッジ4の電
気弁をオフにし接地電流を遮断する。On the other hand, when the ground current is detected by the zero-phase current transformer 10 and the ground fault is detected by the ground fault detector 11, the input condition of the AND circuit 6 is turned off and the electric valve of the inverter bridge 4 is turned off to ground. Cut off the current.
(発明が解決しようとする問題点) 従来の、この方式では、第3図の出力端子W相が接地し
た場合において、交流電源1のR相がアースに対して正
のとき、接地電流はダイオード21→電気弁45→W相のア
ースの回路で流れ、電流検出器8には流れない場合が発
生する。従って零相変流器10と接地故障検出器11を別に
設けて、接地事故に対して保護をしている。(Problems to be Solved by the Invention) In this conventional method, when the output terminal W phase in FIG. 3 is grounded and the R phase of the AC power supply 1 is positive with respect to the ground, the ground current is a diode. In some cases, the current flows in the circuit of 21 → electric valve 45 → ground of W phase and does not flow in the current detector 8. Therefore, the zero-phase current transformer 10 and the ground fault detector 11 are separately provided to protect against a ground fault.
この様に従来は、過電流保護回路の他に、接地保護回路
用品が必要となり、回路が複数で大きさも大きくなり小
形化の障害となっていた。As described above, conventionally, in addition to the overcurrent protection circuit, a ground protection circuit article has been required, and the number of circuits is large, which is an obstacle to miniaturization.
本発明は特別な接地保護用品を行いることなく、経済的
な論理素子をわずかに追加するのみで接地故障を判別し
保護する電力変換器の故障検出回路を提供する。The present invention provides a fault detection circuit for a power converter that determines and protects a ground fault by adding a few economical logic elements without the need for special ground protection equipment.
(問題点を解決するための手段) 本発明は前述問題を解決するために、静電誘導形自己消
孤素子をブリッジ接続して成る電力変換器の故障検出装
置において、前記静電誘導形自己消孤素子のコレクタ−
エミッタ間電圧が所定の値を越え、かつゲート−エミッ
タ間に印加する駆動信号が有るとき故障検出信号を出力
する検出回路と、前記ブリッジの直流側の正側に接続さ
れた素子グループの故障信号と前記ブリッジの直流側負
側に接続された素子グループの故障信号に分けて検出
し、これら2グループの故障信号の論理積が成立する時
は前記ブリッジの負荷側の短絡故障か該ブリッジの故障
と判定し、前記2グループの故障信号の論理和が成立す
る時は接地故障(または該素子の短絡故障)と判定する
論理演算手段を設けて故障検出装置を構成する。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a failure detection device for a power converter in which electrostatic induction type self-extinguishing elements are bridge-connected. Collector of the extinguishing element
A detection circuit that outputs a failure detection signal when the voltage between the emitters exceeds a predetermined value and there is a drive signal applied between the gate and the emitter, and a failure signal of the element group connected to the positive side of the DC side of the bridge. And a failure signal of an element group connected to the negative side of the bridge on the DC side, and when the logical product of the failure signals of these two groups is established, a short-circuit failure on the load side of the bridge or a failure on the bridge. When the logical sum of the failure signals of the two groups is established, a failure detecting device is configured by providing a logical operation means for determining a ground failure (or a short circuit failure of the element).
(作用) 上記構成において、負荷側に短絡が発生するとその短絡
ルートにあるブリッジの正側と負側の静電誘導形自己消
孤素子に短絡電流が流れ前記論理積が成立して短絡故障
か該ブリッジの故障と判定する。(Operation) In the above configuration, when a short circuit occurs on the load side, a short-circuit current flows through the positive and negative electrostatic induction type self-extinguishing elements of the bridge in the short-circuit route, and the logical product is established to cause a short-circuit failure. It is determined that the bridge has failed.
また、負荷側に接地事故が発生すると該接地点を介して
該ブリッジの正側と負側の静電誘導形自己消孤素子に接
地電流が流れるが、該素子は正側と負側が同時にオンし
ないので前記論理積は成立せず接地故障か該素子の短絡
故障と判断する。When a grounding accident occurs on the load side, a ground current flows through the grounding point to the positive and negative side static induction self-extinguishing elements of the bridge, but the positive side and negative side of the element turn on at the same time. Therefore, the logical product is not established, and it is determined that there is a ground fault or a short-circuit fault of the element.
(実施例) 第1図に本発明の実施例を示す。第3図と同一部分は同
一番号を記し説明は省略する。(Example) FIG. 1 shows an example of the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals and the description thereof will be omitted.
ゲート駆動回路7は各異常検出回路12〜17を介してイン
バータブリッジ4の電気弁41〜46にゲート駆動信号を送
る。異常検出回路12〜17は、各電気弁のBIFETのコレク
タ電圧とゲート駆動信号より、ゲート駆動信号がオン状
態で、コレクタ電圧が設定値より高い時に検出信号を出
力する。検出信号を遅れ回路18,19に送り、遅れ回路18,
19は、検出信号が一定時間以上続いたら異常と判断して
信号を出力する。遅れ回路18,19の出力はオア回路30,31
に入力され、インバータブリッジ4の上側のBIFET郡と
下側のBIFET郡に分けて異常を検出し、更にオア回路32
によりいづれのBIFETの異常でも検出する故障検出信号
Aを出力する。The gate drive circuit 7 sends a gate drive signal to the electric valves 41 to 46 of the inverter bridge 4 via the abnormality detection circuits 12 to 17. The abnormality detection circuits 12 to 17 output a detection signal based on the collector voltage of the BIFET of each electric valve and the gate drive signal when the gate drive signal is in the ON state and the collector voltage is higher than the set value. The detection signal is sent to the delay circuits 18 and 19,
When the detection signal continues for a certain period of time or more, 19 determines that it is abnormal and outputs a signal. The outputs of the delay circuits 18 and 19 are OR circuits 30 and 31.
Is input to the upper BIFET group and the lower BIFET group of the inverter bridge 4, and the abnormality is detected.
Outputs a failure detection signal A for detecting any abnormality in BIFET.
一方、オア回路30と31の出力をアンド回路33に入力し、
上側のBIFET郡と下側のBIFET郡の両方が異常であること
を検出し、この信号Cの過電流故障として出力する。On the other hand, the outputs of the OR circuits 30 and 31 are input to the AND circuit 33,
It is detected that both the upper BIFET group and the lower BIFET group are abnormal, and this signal C is output as an overcurrent fault.
アンド回路33の出力はノット回路34を通しオア回路32の
出力とアンド回路35で論理積をとり信号Bを出力する。
この信号Bは、上側のBIFET郡か、下側のBIFET郡のいづ
れかが異常のとき出力され、この場合、一般的には接地
故障である。但し上、下郡のいづれかのBIFETが短絡故
障を発生した場合もB信号を出力するが、最初から短絡
故障に至ることは少く、過電流状態が一定時間続いた場
合に短絡故障に至るのが一般的でありB信号出力時は接
地故障の確率が極めて高い。The output of the AND circuit 33 is passed through a knot circuit 34 and the output of the OR circuit 32 and the AND circuit 35 are ANDed to output a signal B.
This signal B is output when either the upper BIFET group or the lower BIFET group is abnormal, and in this case, it is generally a ground fault. However, the B signal is output even when one of the BIFETs in Shimogori has a short-circuit fault, but the short-circuit fault rarely occurs from the beginning, and a short-circuit fault may occur when the overcurrent state continues for a certain period of time. In general, the probability of ground fault is extremely high when the B signal is output.
異常検出回路12〜17の具体例を第2図に示す。A specific example of the abnormality detection circuits 12 to 17 is shown in FIG.
駆動信号eiは抵抗52、トランジスタ58,59から成る増幅
器を介して直流電源51の電圧を、BIFET44のゲートに加
え、BIFETをオンさせる。一方、BIFETのコレクタ電圧を
抵抗60,ゼナーダイオード56により検出し、コレクタ電
圧がツェナー電圧等で定まる所定の設定値より高い場合
はトランジスタ55をオンさせ、駆動信号eiを抵抗52,53
で分圧しBIFET44の過電流値を抑制すると同時にフォト
カプラ54の発光ダイオードを駆動し、フォトカプラ受光
側のトランジスタ63をオンさせることにより出力eoを異
常信号として出力させる。抵抗57はトランジスタ55のベ
ースがオープンにならないようにするものであり、抵抗
62はプルアップ抵抗である。この回路では駆動信号eiが
‘1'の時のみしかフォトカプラ54には電流が流れる条件
が無く、異常検出信号は駆動信号eiが‘0'の時には出力
されない。The drive signal e i applies the voltage of the DC power supply 51 to the gate of the BIFET 44 via the amplifier composed of the resistor 52 and the transistors 58 and 59 to turn on the BIFET. On the other hand, the collector voltage of BIFET is detected by the resistor 60 and the Zener diode 56, and when the collector voltage is higher than a predetermined set value determined by the Zener voltage etc., the transistor 55 is turned on and the drive signal e i is set to the resistors 52, 53.
The voltage is divided by to suppress the overcurrent value of the BIFET 44, and at the same time, the light emitting diode of the photocoupler 54 is driven and the transistor 63 on the photocoupler light receiving side is turned on to output the output e o as an abnormal signal. The resistor 57 prevents the base of the transistor 55 from opening, and
62 is a pull-up resistor. In this circuit, the photocoupler 54 has a condition that a current flows only when the drive signal e i is “1”, and the abnormality detection signal is not output when the drive signal e i is “0”.
通常のオン状態ではBIFET44のコレクタ電圧は数V以下
に低下しているが過電流状態ではBIFET44のコレクタ電
圧が急上昇し数十V以上になるので、この状態を異常と
して検出するものである。In the normal ON state, the collector voltage of the BIFET 44 drops to several V or less, but in the overcurrent state, the collector voltage of the BIFET 44 rapidly rises to several tens of V or more, and this state is detected as an abnormality.
(これ等の詳細については先に出願した特願昭60-23334
と特願昭60-92870を参照されたい。) 第1図の回路で、負荷側短絡事故、例えば端子VとWが
短絡状態になった場合を考えるとBIFET43と42がオンの
瞬間、コンデンサ3の電圧はBIFET43と42で分圧される
のでBIFET43と42の異常検出回路16と14は異常検出信号
を遅れ回路18と19に出力し、この状態が一定時間(10μ
S程度)以上続くとオア回路30,31が動作し、信号Aと
信号Cが出力し信号Cは過電流故障と判断する。(For details of these, Japanese Patent Application No. 60-23334 filed earlier.
See Japanese Patent Application No. 60-92870. ) In the circuit of FIG. 1, considering a load side short circuit accident, for example, when terminals V and W are short-circuited, the voltage of capacitor 3 is divided by BIFET 43 and 42 at the moment when BIFET 43 and 42 are turned on. The abnormality detection circuits 16 and 14 of BIFETs 43 and 42 output the abnormality detection signals to the delay circuits 18 and 19, and this state is maintained for a certain time (10 μm
If it continues for more than about S), the OR circuits 30 and 31 operate to output the signals A and C, and the signal C is judged to be an overcurrent fault.
次に、W相が接地した場合を考えると、BIFET42がオン
した瞬間、電源1の電圧が接地回路(BIFET42→ダイオ
ード22,24,26の回路)を通って、BIFET42に印加され、B
IFET42に過電流が流れるとBIFET42のコレクタ電圧が上
昇して異常検出回路14が信号を出力する。Next, considering the case where the W phase is grounded, the voltage of the power supply 1 is applied to the BIFET 42 at the moment when the BIFET 42 is turned on, through the ground circuit (BIFET 42 → the circuits of diodes 22, 24 and 26), and B
When an overcurrent flows through the IFET 42, the collector voltage of the BIFET 42 rises and the abnormality detection circuit 14 outputs a signal.
また、BIFET45がオンの状態では、電源1の電圧は、ダ
イオード21,23,25→BIFET45→接地の回路に印加され、
異常検出回路17が信号を出力する。BIFET45と42は、同
時にオン信号は入らない様制御しているので、オア回路
30と31が同時に出力を出すことはなく、接地事故の場合
は、いづれか片方の出力が出るので、信号AとBが出力
される。When the BIFET45 is on, the voltage of the power supply 1 is applied to the diode 21,23,25 → BIFET45 → ground circuit,
The abnormality detection circuit 17 outputs a signal. BIFET 45 and 42 are controlled so that the ON signal does not enter at the same time, so the OR circuit
In the case of a ground accident, signals 30 and 31 do not output at the same time, and in the case of a grounding accident, either one output is output, so signals A and B are output.
以上の説明の如く一般の過電流では故障信号は、Aと
C、接地事故の場合は、AとBの信号を出力することが
出来るので故障内容を判別し、故障診断を容易にするこ
とが可能である。As described above, in the case of a general overcurrent, the failure signal can output the signals A and C, and in the case of a grounding accident, the signals A and B can be output, so that the failure content can be determined and the failure diagnosis can be facilitated. It is possible.
なお、インバータブリッジは3相の場合のBIFET使用時
について説明したが、FET等の如く電圧信号で駆動出来
るスイッチング素子で、過電流時にコレクタ電圧が上昇
する素子には同一の方法が採用出来ることは云うまでも
ない。In addition, the inverter bridge has been explained when using BIFET in the case of three phases, but it is a switching element that can be driven by a voltage signal such as FET, and the same method can be adopted for the element whose collector voltage rises at the time of overcurrent. Needless to say.
以上説明したように本発明によれば、特別な接地事故検
出回路を設けること無く、過電流検出回路を、インバー
タブリッジの直流母線に対し上下2組に分離し、アンド
とオアの論理演算のみにより故障内容を表示することが
可能となり故障診断として極めて簡単で経済的、かつコ
ンパクトに実現出来る電力変換器の故障検出回路を提供
することができる。As described above, according to the present invention, the overcurrent detection circuit is separated into two sets above and below the DC bus of the inverter bridge without providing a special ground fault detection circuit, and only the logical operation of AND and OR is used. It is possible to provide a failure detection circuit of a power converter that can display the details of a failure and can be realized as a failure diagnosis extremely easily, economically, and compactly.
第1図は本発明による故障検出回路の一実施例、第2図
は第1図の異常検出回路の詳細図、第3図は従来の故障
検出回路である。 1……交流電源、2……整流器、 21〜26……ダイオード、3……コンデンサ 4……インバータブリッジ 41〜46……電気弁、5……PWM制御回路 6……アンド回路、7……ゲート駆動回路 8……電流検出器、9……過電流検出器 10……零相変流器、11……接地故障検出器 12〜17……異常検出回路、18,19……遅れ回路 30,31,32……オア回路、33,35……アンド回路 34……ノット回路、51……直流電源 55,58,59……トランジスタ、54,63……フォトカプラ 56……ゼナーダイオード 52,53,57,60,62……抵抗FIG. 1 is an embodiment of a failure detection circuit according to the present invention, FIG. 2 is a detailed view of the abnormality detection circuit of FIG. 1, and FIG. 3 is a conventional failure detection circuit. 1 ... AC power supply, 2 ... Rectifier, 21-26 ... Diode, 3 ... Capacitor 4 ... Inverter bridge 41-46 ... Electric valve, 5 ... PWM control circuit 6 ... AND circuit, 7 ... Gate drive circuit 8 …… Current detector, 9 …… Overcurrent detector 10 …… Zero-phase current transformer, 11 …… Ground fault detector 12 ~ 17 …… Abnormality detection circuit, 18,19 …… Delay circuit 30 , 31,32 …… OR circuit, 33,35 …… AND circuit 34 …… NOT circuit, 51 …… DC power supply 55,58,59 …… Transistor, 54,63 …… Photo coupler 56 …… Zener diode 52 , 53,57,60,62 …… Resistance
Claims (2)
て成る電力変換器の故障検出装置において、前記静電誘
導形自己消孤素子のコレクターエミッタ間電圧が所定の
値を越え、かつゲート−エミッタ間に印加する駆動信号
が有るとき故障検出信号を出力する検出回路と、前記ブ
リッジの直流側の正側に接続された素子グループの故障
信号と前記ブリッジの直流側の負側に接続された素子グ
ループの故障信号に分けて検出し、これら2グループの
故障信号の論理積が成立する時は前記ブリッジの負荷側
の短絡故障か該ブリッジの故障と判定し、前記2グルー
プの故障信号の論理和が成立する時は接地故障(または
該素子の短絡故障)と判定する論理演算手段を設けたこ
とを特徴とする電力変換器の故障検出装置。1. A failure detection device for a power converter, which comprises a bridge connection of static induction self-extinguishing elements, wherein the collector-emitter voltage of the static induction self-extinction element exceeds a predetermined value, and A detection circuit which outputs a failure detection signal when there is a drive signal applied between the gate and the emitter, and a failure signal of the element group connected to the positive side of the direct current side of the bridge and a negative side of the direct current side of the bridge. The failure signals of the two groups are detected separately, and when the logical product of the failure signals of these two groups is established, it is judged as a short-circuit failure on the load side of the bridge or a failure of the bridge, and the failure signals of the two groups are detected. A failure detecting device for a power converter, which is provided with a logical operation means for determining a ground fault (or a short-circuit fault of the element) when the logical sum of is established.
を印加した後、静電誘導形自己消孤素子がオンするまで
の遅れ時間は出力しないように構成したことを特徴とす
る前記特許請求の範囲第1項記載の電力変換器の故障検
出装置。2. The delay signals of the two groups are configured such that a delay time until the electrostatic induction type self-extinguishing element is turned on after the drive signal is applied is not output. A failure detection device for a power converter according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61070841A JPH0732531B2 (en) | 1986-03-31 | 1986-03-31 | Power converter failure detection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61070841A JPH0732531B2 (en) | 1986-03-31 | 1986-03-31 | Power converter failure detection device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62230323A JPS62230323A (en) | 1987-10-09 |
JPH0732531B2 true JPH0732531B2 (en) | 1995-04-10 |
Family
ID=13443190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61070841A Expired - Lifetime JPH0732531B2 (en) | 1986-03-31 | 1986-03-31 | Power converter failure detection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0732531B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04138073A (en) * | 1990-09-28 | 1992-05-12 | Sanyo Electric Co Ltd | Hybrid integrated circuit device |
JPH04138075A (en) * | 1990-09-28 | 1992-05-12 | Sanyo Electric Co Ltd | Hybrid integrated circuit device |
-
1986
- 1986-03-31 JP JP61070841A patent/JPH0732531B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS62230323A (en) | 1987-10-09 |
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