JPH0729925A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0729925A JPH0729925A JP5173224A JP17322493A JPH0729925A JP H0729925 A JPH0729925 A JP H0729925A JP 5173224 A JP5173224 A JP 5173224A JP 17322493 A JP17322493 A JP 17322493A JP H0729925 A JPH0729925 A JP H0729925A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- die pad
- semiconductor device
- fixing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップの能動面
にある電極とリードとを結ぶ金属細線の安定な結線技術
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stable metal wire connecting technique for connecting a lead and an electrode on an active surface of a semiconductor chip.
【０００２】[0002]
【従来の技術】図８において、従来の技術を説明する。2. Description of the Related Art A conventional technique will be described with reference to FIG.
【０００３】現状の半導体チップの組立工程は、先ず半
導体チップ１を半導体チップ１を固定するための載置部
（以下ダイパッドと記す）２に半導体チップ１の能動面
とは異なる面を導電性の接着剤３にて固着し、その後、
前記半導体チップ１上の電極（以下パッドと記す）４
と、前記半導体チップ１の周囲に配されたリード５とを
金属細線（以下ワイヤと記す）６によって結ぶ。その
後、封止樹脂７によって前記半導体チップ１及び前記ダ
イパッド２、前記ワイヤ６、前記リード５を封止する。In the current semiconductor chip assembling process, first, the semiconductor chip 1 is mounted on a mounting portion (hereinafter referred to as a die pad) 2 for fixing the semiconductor chip 1, and a surface different from the active surface of the semiconductor chip 1 is made conductive. Secure with adhesive 3, then
Electrodes (hereinafter referred to as pads) 4 on the semiconductor chip 1
And a lead 5 arranged around the semiconductor chip 1 are connected by a thin metal wire (hereinafter referred to as a wire) 6. Then, the semiconductor chip 1, the die pad 2, the wires 6, and the leads 5 are sealed with a sealing resin 7.
【０００４】ここで、半導体チップをダイパッドに固着
する工程（以下ダイアタッチ工程と記す）について、図
９（ａ）、（ｂ）において詳細に説明する。The process of fixing the semiconductor chip to the die pad (hereinafter referred to as the die attach process) will be described in detail with reference to FIGS. 9 (a) and 9 (b).
【０００５】図９（ａ）において、ノズル１８によって
導電性接着剤３がダイパッド２上に吐出される。この
時、ダイパッド２上の導電性接着剤３は、半導体チップ
１（図示せず）との固着時に均一の厚みになるように、
所定の間隔を持って点在している。その後、図９（ｂ）
に示すように、半導体チップ１が固着治具（以下コレッ
トと記す）１９によって、所定の位置に固着される。こ
のとき、半導体チップ１は、コレット１９によって能動
面を吸着保持するか、または、能動面を構成する４辺を
介して吸着保持するかによって接合が行われる。In FIG. 9A, the conductive adhesive 3 is discharged onto the die pad 2 by the nozzle 18. At this time, the conductive adhesive 3 on the die pad 2 has a uniform thickness when fixed to the semiconductor chip 1 (not shown).
It is scattered with a predetermined interval. After that, FIG. 9 (b)
As shown in FIG. 3, the semiconductor chip 1 is fixed at a predetermined position by a fixing jig (hereinafter referred to as a collet) 19. At this time, the semiconductor chip 1 is bonded by either adsorbing and holding the active surface by the collet 19 or adsorbing and holding the active surface through the four sides forming the active surface.
【０００６】またここで、ワイヤにより半導体チップ上
のパッドとリードとを結線する工程（以下ワイヤボンデ
ィング工程と記す）について、図１０において詳細に説
明する。リード５はリード押さえ治具１０とダイパッド
受け治具１１とによって固定され、ワイヤボンディング
が行われる。この時、半導体チップ１とダイパッド受け
治具１１との間には、導電性接着剤３、ダイパッド２が
介在している。The step of connecting the pad and the lead on the semiconductor chip with the wire (hereinafter referred to as the wire bonding step) will be described in detail with reference to FIG. The leads 5 are fixed by the lead pressing jig 10 and the die pad receiving jig 11, and wire bonding is performed. At this time, the conductive adhesive 3 and the die pad 2 are interposed between the semiconductor chip 1 and the die pad receiving jig 11.
【０００７】また、近年における半導体装置への高集積
化及び小型化等の要求に応じて、より半導体チップの面
積が縮小されてきている。その一方、要求される機能の
増加により、高集積化及び小型化の技術を越え、より大
面積の半導体チップも製造されており、将来的にはより
面積の大きい半導体チップの出現が予想されている。In addition, the area of a semiconductor chip has been further reduced in response to the recent demand for higher integration and smaller size of semiconductor devices. On the other hand, due to the increase in required functions, technology for higher integration and miniaturization has been exceeded, and semiconductor chips with a larger area have been manufactured, and it is expected that semiconductor chips with a larger area will appear in the future. There is.
【０００８】[0008]
【発明が解決しようとする課題】本発明は、上述の従来
技術を用いた半導体装置を使用し、以下に示すような問
題があることを見いだした。The present invention uses the semiconductor device using the above-mentioned conventional technique and has found out the following problems.
【０００９】従来の技術を用いた半導体装置の構造を用
いて、面積の大きい半導体チップのダイアタッチを行え
ば、ノズル１８先端の所定の間隔で点在する吐出孔（図
示せず）より吐出される導電性接着剤３の量は不安定と
なり、必然的にダイパッド２上に所定の間隔で点在する
導電性接着剤３の各々の量にムラが生じ易くなる。この
ムラにより、ダイパッド２と半導体チップ１との間の導
電性接着剤３の厚みが不均一となる。そして、この厚み
の不均一によってダイパッド２平面に対して、半導体チ
ップ１の能動面側を含む平面に傾きが発生する。If a semiconductor chip having a large area is die-attached by using the structure of a semiconductor device using the conventional technique, the nozzles are ejected from ejection holes (not shown) scattered at a predetermined interval. The amount of the conductive adhesive 3 is unstable and inevitably causes unevenness in the amount of each conductive adhesive 3 scattered on the die pad 2 at predetermined intervals. Due to this unevenness, the thickness of the conductive adhesive 3 between the die pad 2 and the semiconductor chip 1 becomes uneven. Due to this uneven thickness, the plane including the active surface side of the semiconductor chip 1 is inclined with respect to the plane of the die pad 2.
【００１０】また、半導体チップ１の面積が大きけれ
ば、載置するためのダイパッド２も面積が大きくなり、
ダイパッド２に反りもしくは傾きが発生し易い状態とな
る。反りもしくは傾きのあるダイパッド２に半導体チッ
プ１を裁置すれば、半導体チップ１の能動面側を含む平
面に傾きが生ずる。If the area of the semiconductor chip 1 is large, the area of the die pad 2 for mounting is also large,
The die pad 2 is easily warped or tilted. When the semiconductor chip 1 is placed on the warped or tilted die pad 2, the flat surface including the active surface side of the semiconductor chip 1 is tilted.
【００１１】また、近年、半導体チップをコレットによ
りダイパッドの所定の位置に固定する際、半導体チップ
の能動面にダメージを与えぬように、半導体チップの４
辺を介してダイアタッチするのが一般的になってきてい
る。しかし、半導体チップの４辺を介してダイアタッチ
を行う為には、半導体チップの形状に対応した多数種の
コレットを準備しなければならず、コストの増加、及び
組立準備に関わる手配工数の増加を招いていた。Further, in recent years, when a semiconductor chip is fixed to a predetermined position of a die pad by a collet, the semiconductor chip 4 is protected so as not to damage the active surface of the semiconductor chip.
It is becoming more common to make a die attach through a side. However, in order to perform die attachment via the four sides of the semiconductor chip, it is necessary to prepare many types of collets corresponding to the shape of the semiconductor chip, which increases costs and increases man-hours required for assembly preparation. Was invited.
【００１２】ワイヤボンディング工程において、このよ
うな状態では、前述に示した理由により、面積の大きい
半導体チップ１の能動面側を含む平面が、ダイパッド２
の前記半導体チップ１を裁置しない裏面と接するダイパ
ッド受け治具１１の平面に対して傾きを生ずる。一方、
パッド４とリード５とをワイヤ６にて配線する図示しな
いボンディング装置の一部であるボンディング治具（以
下キャピラリと記す）１２のＺ軸方向は、ダイパッド受
け治具１１の平面をＸ−Ｙ平面として制御されている。
つまり、半導体チップ１の能動面を含む平面の垂直方向
とキャピラリ１２のＺ軸方向とが一致しないこととな
る。In the wire bonding step, in such a state, the plane including the active surface side of the semiconductor chip 1 having a large area is in the die pad 2 due to the reason described above.
The semiconductor chip 1 is inclined with respect to the plane of the die pad receiving jig 11 in contact with the back surface on which the semiconductor chip 1 is not placed. on the other hand,
In the Z-axis direction of a bonding jig (hereinafter referred to as a capillary) 12 that is a part of a bonding device (not shown) that connects the pad 4 and the lead 5 with a wire 6, the plane of the die pad receiving jig 11 is an XY plane. Is controlled as.
That is, the vertical direction of the plane including the active surface of the semiconductor chip 1 and the Z-axis direction of the capillary 12 do not match.
【００１３】さて、ボンディング工程におけるワイヤ６
とパッド４またはワイヤ６とリード５との接続は、キャ
ピラリ１２によりワイヤ６を接続対象となるパッド４ま
たはリード５とに押しつけ、加重・熱・超音波等による
エネルギをキャピラリ１２からパッド４またはリード５
方向に加え、ワイヤ６とパッド４及びワイヤ６とリード
５との間に合金を形成して接合するものである。Now, the wire 6 in the bonding process
, The pad 4 or the wire 6 and the lead 5 are connected to each other by pressing the wire 6 against the pad 4 or the lead 5 to be connected by the capillary 12 and applying energy by load, heat, ultrasonic waves or the like from the capillary 12 to the pad 4 or the lead 5. 5
In addition to the direction, an alloy is formed and bonded between the wire 6 and the pad 4 and between the wire 6 and the lead 5.
【００１４】前述の状態にてボンディングを行えば、理
想状態に比較してキャピラリ１２とワイヤ６と接触面積
が減少する。また、キャピラリ１２からの加重及びエネ
ルギの伝達にムラが生じ、ワイヤ６とパッド４またはワ
イヤ６とリード５との合金形成は十分とは言えない状態
となり、不十分な接合となる。If the bonding is performed in the above-mentioned state, the contact area between the capillary 12 and the wire 6 is reduced as compared with the ideal state. Further, unevenness occurs in the load and energy transmission from the capillary 12, and the alloy formation between the wire 6 and the pad 4 or the wire 6 and the lead 5 is not sufficient, resulting in insufficient bonding.
【００１５】また、以下に示す問題をも引き起こす。半
導体チップ１の能動面に傾きがあると、前記半導体チッ
プ１を裁置しない裏面と接するダイパッド受け治具１１
の平面から前記半導体チップ１の能動面までの距離が一
定ではなくなることとなる。すなわち、キャピラリ１２
が前記半導体チップ１のパッド４まで移動するＺ軸方向
の距離が一定ではなくなる。このことにより、適切なボ
ンディング条件の設定が、及び適切なボンディングが不
可能となる。Further, the following problems are also caused. If the active surface of the semiconductor chip 1 is tilted, the die pad receiving jig 11 is in contact with the back surface on which the semiconductor chip 1 is not placed.
Therefore, the distance from the plane to the active surface of the semiconductor chip 1 is not constant. That is, the capillary 12
However, the distance in the Z-axis direction that moves to the pad 4 of the semiconductor chip 1 is not constant. This makes it impossible to set proper bonding conditions and proper bonding.
【００１６】また、近年の半導体チップの消費電力の増
加により、半導体チップの発熱が増加してきている。こ
の熱を半導体装置外部へ逃がさなければ、半導体チップ
の機能を損なうこととなってしまう。そこで、ダイパッ
ド裏面に放熱体を固着して、その放熱体より外部に放熱
していた。しかし、能動面で発生した熱が半導体チップ
裏面のダイパッドまで移動しなければならず、放熱効率
が良好とはいえなかった。Further, due to the recent increase in the power consumption of the semiconductor chip, the heat generation of the semiconductor chip is increasing. Unless this heat is released to the outside of the semiconductor device, the function of the semiconductor chip will be impaired. Therefore, a heat radiator is fixed to the back surface of the die pad, and the heat is radiated to the outside from the heat radiator. However, the heat generated on the active surface has to move to the die pad on the back surface of the semiconductor chip, and the heat dissipation efficiency cannot be said to be good.
【００１７】[0017]
【課題を解決するための手段】本発明の半導体装置は半
導体チップとダイパッドと前記半導体チップの周囲に配
されたリードと、前記半導体チップと前記リードとを結
ぶワイヤ、及び、それら半導体チップとリード、ワイヤ
を封止する樹脂からなる半導体装置において、半導体チ
ップの能動面側に半導体チップの載置部があることを特
徴とする。A semiconductor device according to the present invention is a semiconductor chip, a die pad, a lead arranged around the semiconductor chip, a wire connecting the semiconductor chip and the lead, and the semiconductor chip and the lead. In a semiconductor device made of resin for encapsulating wires, the semiconductor chip mounting portion is provided on the active surface side of the semiconductor chip.
【００１８】[0018]
【作用】半導体チップとダイパッドとの固着を、半導体
チップの能動面にて行うことにより、半導体チップとダ
イパッド受け治具との間にダイパッド、導電性接着剤が
介在せず、半導体チップの傾きを発生させる要因が皆無
となり、ワイヤボンディングの十分な接合を安定に行う
ことができる。[Function] By fixing the semiconductor chip and the die pad on the active surface of the semiconductor chip, the die pad and the conductive adhesive are not interposed between the semiconductor chip and the die pad receiving jig, and the inclination of the semiconductor chip is prevented. There is no factor to generate, and sufficient wire bonding can be stably performed.
【００１９】[0019]
【実施例】本発明の一実施例を以下に説明する。EXAMPLE An example of the present invention will be described below.
【００２０】図１において、半導体チップ１とダイパッ
ド２との固着を、配線・パッド等がある半導体チップ１
の能動面にて行っている。半導体チップ１の能動面にあ
るパッド４とリード５がワイヤ６にて配線されている。
前記半導体チップ１、ダイパッド２、ワイヤ６、リード
５が封止材７によって封止されている。固着に用いる接
着剤３は非導電性が好ましい。接着剤が導電性の場合
は、半導体チップの能動面側の図示しない絶縁膜の厚み
を増すか、図２に示すように、半導体チップ１とダイパ
ッド２との間に、絶縁性フィルム８を用いることによ
り、絶縁をはかることが可能である。つまり絶縁フィル
ム８と半導体チップ１との間に導電性接着剤３’を用
い、同様に絶縁フィルム８とダイパッド２との間にも導
電性接着剤３’を用いれば良い。In FIG. 1, the semiconductor chip 1 and the die pad 2 are fixed to each other by wiring, pads, etc.
The active side of. Pads 4 and leads 5 on the active surface of the semiconductor chip 1 are wired by wires 6.
The semiconductor chip 1, the die pad 2, the wires 6, and the leads 5 are sealed with a sealing material 7. The adhesive 3 used for fixing is preferably non-conductive. When the adhesive is conductive, the thickness of an insulating film (not shown) on the active surface side of the semiconductor chip is increased, or an insulating film 8 is used between the semiconductor chip 1 and the die pad 2 as shown in FIG. By doing so, it is possible to provide insulation. That is, the conductive adhesive 3 ′ may be used between the insulating film 8 and the semiconductor chip 1, and similarly, the conductive adhesive 3 ′ may be used between the insulating film 8 and the die pad 2.
【００２１】ダイパッドの形状は、ワイヤボンディング
に支障をきたさないものであれば良い。例えば図３
（ａ）に示すように、ダイパッド２の外形寸法は、半導
体チップ１の外形寸法よりも小さくし、ワイヤボンディ
ングに必要なパッド４が露出するような形状が好まし
い。また、図３（ｂ）に示すように、ダイパッド１０の
外形寸法が半導体チップ１よりも大きな場合でも、ワイ
ヤボンディングに必要なパッド４が、露出するような位
置に貫通穴９をダイパッド２に設ければよい。このとき
貫通穴の形状は、特に限定せず、長方形でも楕円形等で
もよい。また、図４に示すように、ダイパッドは一枚の
平板である必要はなく、本実施例に示すように、２分割
として構成されていてもよい。また、本実施例に関わら
ず、３分割以上でもよい。このとき、ダイパッドの形状
はワイヤボンディングに支障の無いものであれば特に限
定しない。The die pad may have any shape as long as it does not hinder wire bonding. For example, in FIG.
As shown in (a), it is preferable that the die pad 2 has an outer dimension smaller than that of the semiconductor chip 1 so that the pad 4 necessary for wire bonding is exposed. Further, as shown in FIG. 3B, a through hole 9 is provided in the die pad 2 at a position where the pad 4 necessary for wire bonding is exposed even when the outer dimension of the die pad 10 is larger than that of the semiconductor chip 1. Just do it. At this time, the shape of the through hole is not particularly limited and may be rectangular or elliptical. Further, as shown in FIG. 4, the die pad does not have to be a single flat plate, and may be divided into two as shown in this embodiment. Further, regardless of the present embodiment, it may be divided into three or more. At this time, the shape of the die pad is not particularly limited as long as it does not hinder wire bonding.
【００２２】次に、本発明の製造方法について説明す
る。Next, the manufacturing method of the present invention will be described.
【００２３】図５、図６（ａ）（ｂ）において、本発明
を適用した場合のダイボンディング工程を示す。図５に
おいて、ダイパッド２及びリード５を含むリードフレー
ム１７が、図示しない冶具によって固定されている。そ
して、図６（ａ）に示すように、ダイパッド２上に接着
剤３が塗布される。その後、図６（ｂ）に示すように、
このダイパッド２に半導体チップ１の能動面を固着する
為に、半導体チップ１の能動面と対抗する裏面をコレッ
ト１３によって吸着保持して接合する。半導体チップ１
の裏面には、能動面とは異なり配線等が無い為、コレッ
トと半導体チップの間に介在するシリコン等の破片によ
り配線を傷つけたり、断線させたりする問題がなく、裏
面全体を容易に吸着できる。半導体チップの裏面吸着が
問題なく実施できれば、半導体チップの辺を介して吸着
保持するタイプのコレットに比較して、汎用性が高ま
る。その為、半導体チップの外形寸法に都度合わせたコ
レットの必要が無くなり、コストダウンがはかれる。能
動面と対抗する裏面を構成する辺を介して吸着保持する
ことによっても接合することができることは、述べるま
でもない。FIGS. 5 and 6A and 6B show a die bonding process when the present invention is applied. In FIG. 5, the lead frame 17 including the die pad 2 and the leads 5 is fixed by a jig not shown. Then, as shown in FIG. 6A, the adhesive 3 is applied onto the die pad 2. After that, as shown in FIG.
In order to fix the active surface of the semiconductor chip 1 to the die pad 2, the back surface facing the active surface of the semiconductor chip 1 is adsorbed and held by the collet 13 and bonded. Semiconductor chip 1
Unlike the active surface, there is no wiring on the back surface of the, so there is no problem of damaging or breaking the wiring due to debris such as silicon interposed between the collet and the semiconductor chip, and the entire back surface can be easily adsorbed. . If the backside suction of the semiconductor chip can be performed without any problem, the versatility is enhanced as compared with a collet of the type that suction-holds the semiconductor chip through the sides. Therefore, it is not necessary to use a collet that matches the external dimensions of the semiconductor chip each time, and the cost can be reduced. It goes without saying that they can be joined also by adsorbing and holding them via the side that constitutes the back surface that opposes the active surface.
【００２４】次に、本発明を適用して製造された半導体
装置において、より放熱特性を向上させる場合について
説明する。Next, a case will be described in which the heat dissipation characteristics of the semiconductor device manufactured by applying the present invention are further improved.
【００２５】図７に示すように、放熱体１４をダイパッ
ド２の半導体チップ１が裁置されている側とは異なる面
に接着剤１６で固着することによって、半導体チップ１
の能動面にて発生した熱がダイパッド２から放熱体１
４、放熱体１４から半導体装置１５の外部へとスムーズ
に伝達される。このとき、放熱体１４の一辺が半導体装
置１５の外部に露出している状態であれば、より熱伝達
の効率は良好となる。また、放熱体１４の一辺が半導体
装置１５の外部に露出していることによって、図示しな
いフィン等の外部放熱体の接続も容易になる。As shown in FIG. 7, the heat sink 14 is fixed to the surface of the die pad 2 different from the side on which the semiconductor chip 1 is placed by the adhesive 16 so that the semiconductor chip 1 is formed.
The heat generated on the active surface of the
4. The heat is smoothly transmitted from the radiator 14 to the outside of the semiconductor device 15. At this time, if one side of the radiator 14 is exposed to the outside of the semiconductor device 15, the efficiency of heat transfer becomes better. Further, since one side of the heat radiator 14 is exposed to the outside of the semiconductor device 15, connection of an external heat radiator such as a fin (not shown) becomes easy.
【００２６】本実施例は一実施例であり、この限りでは
ない。This embodiment is an example, and the present invention is not limited to this.
【００２７】[0027]
【発明の効果】以上述べたように、本発明によれば、半
導体チップとダイパッド受け治具との間にダイパッド、
導電性接着剤が介在せず、半導体チップの傾きを発生さ
せる要因が皆無となり、ワイヤボンディグの十分な接合
を安定に行うことができるという効果を有する。また、
ダイボンディング工程において、多数種の半導体チップ
のサイズに、一対一に対応したコレットを多数準備する
必要がなく、僅かな種類のコレットを準備するのみでダ
イボンディングが可能となり、コストダウンが計れ、作
業も容易となる効果も有する。As described above, according to the present invention, a die pad, between the semiconductor chip and the die pad receiving jig,
Since there is no conductive adhesive, there is no factor that causes the inclination of the semiconductor chip, and there is an effect that sufficient bonding of the wire bond can be stably performed. Also,
In the die-bonding process, it is not necessary to prepare many collets corresponding to one-to-one with the sizes of many types of semiconductor chips, die-bonding is possible by preparing only a few types of collets, and cost reduction can be achieved. Also has the effect of becoming easier.
【図１】 本発明の一実施例である半導体装置の概略断
面図。FIG. 1 is a schematic cross-sectional view of a semiconductor device that is an embodiment of the present invention.
【図２】 本発明の一実施例である半導体装置の概略断
面図。FIG. 2 is a schematic cross-sectional view of a semiconductor device that is an embodiment of the present invention.
【図３】 （ａ）は、本発明の一実施例である半導体装
置の一部を示す概略図。（ｂ）は、本発明の一実施例で
ある半導体装置の一部を示す概略図。FIG. 3A is a schematic view showing a part of a semiconductor device according to an embodiment of the present invention. FIG. 2B is a schematic view showing a part of a semiconductor device which is an embodiment of the present invention.
【図４】 本発明の一実施例である半導体装置の一部を
示す概略図。FIG. 4 is a schematic view showing a part of a semiconductor device according to an embodiment of the present invention.
【図５】 本発明の一実施例である半導体装置の製造方
法を示す概略図。FIG. 5 is a schematic view showing a method of manufacturing a semiconductor device which is an embodiment of the present invention.
【図６】 （ａ）は、図５のＡ−Ａ断面からみた本発明
の一実施例である半導体装置の製造方法を示す概略図。
（ｂ）は、図５のＡ−Ａ断面からみた本発明の一実施例
である半導体装置の製造方法を示す概略図。6A is a schematic view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention as seen from the AA cross section of FIG.
FIG. 6B is a schematic view showing a method of manufacturing a semiconductor device which is an embodiment of the present invention as seen from the AA cross section of FIG. 5.
【図７】 本発明の一実施例である半導体装置の概略断
面図。FIG. 7 is a schematic cross-sectional view of a semiconductor device that is an embodiment of the present invention.
【図８】 従来技術を説明するための半導体装置を示す
概略断面図。FIG. 8 is a schematic sectional view showing a semiconductor device for explaining a conventional technique.
【図９】 （ａ）は、従来技術を説明するための半導体
装置の製造方法を示す概略図。（ｂ）は、従来技術を説
明するための半導体装置の製造方法を示す概略図。FIG. 9A is a schematic view showing a method of manufacturing a semiconductor device for explaining a conventional technique. FIG. 3B is a schematic diagram showing a method of manufacturing a semiconductor device for explaining a conventional technique.
【図１０】 従来技術を説明するための半導体装置の製
造方法を示す概略断面図。FIG. 10 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device for explaining a conventional technique.
１・・・・・・・・・半導体チップ ２・・・・・・・・・ダイパッド ３、３’、１６・・接着剤 ４・・・・・・・・ パッド ５・・・・・・・・・リード ６・・・・・・・・・ワイヤ ７・・・・・・・・・封止樹脂 ８・・・・・・・・・絶縁性フィルム ９・・・・・・・・・貫通穴 １０・・・・・・・・・リード押さえ治具 １１・・・・・・・・・ダイパッド受け治具 １２・・・・・・・・・キャピラリ １３・・・・・・・・・コレット １４・・・・・・・・・放熱体 １５・・・・・・・・・半導体装置 １７・・・・・・・・・フレーム １８・・・・・・・・・ノズル １９・・・・・・・・・コレット 1 ・ ・ ・ ・ ・ ・ Semiconductor chip 2 ・ ・ ・ ・ ・ ・ ・ ・ Die pad 3, 3 ', 16 ・ ・ Adhesive 4 ・ ・ ・ ・ ・ ・ Pad 5 ・ ・ ・・ ・ ・ Lead 6 ・ ・ ・ ・ ・ ・ Wire 7 ・ ・ ・ ・ ・ ・ Encapsulating resin 8 ・ ・ ・ ・ ・ ・ Insulating film 9 ・ ・ ・ ・ ・ ・・ Through hole 10 ・ ・ ・ ・ ・ ・ ・ ・ ・ Lead holding jig 11 ・ ・ ・ ・ ・ ・ ・ Die pad receiving jig 12 ・ ・ ・ ・ ・ ・ ・ Capillary 13 ・ ・ ・ ・··· Collet 14 ····· Heat sink 15 ··· · · Semiconductor device 17 ··· · Frame 18 ··· · Nozzle 19・ ・ ・ ・ ・ ・ ・ Colette
Claims (6)
るための載置部と前記半導体チップの周囲に配されたリ
ードと、前記半導体チップと前記リードとを結ぶ金属細
線、及び、それら半導体チップとリード、金属細線を封
止する樹脂からなる半導体装置において、半導体チップ
の能動面と前記半導体チップを固定するための載置部と
が接続固定されていることを特徴とする半導体装置。1. A semiconductor chip, a mounting portion for fixing the semiconductor chip, leads arranged around the semiconductor chip, thin metal wires connecting the semiconductor chip and the leads, and the semiconductor chips. A semiconductor device made of a resin for encapsulating a lead and a thin metal wire, wherein an active surface of a semiconductor chip and a mounting portion for fixing the semiconductor chip are connected and fixed.
体チップの載置部の少なくとも一部に貫通孔がある事を
特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein at least a part of the mounting portion of the semiconductor chip has a through hole.
体チップの載置部の面積が半導体チップの面積よりも小
さい事を特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein an area of a mounting portion of the semiconductor chip is smaller than an area of the semiconductor chip.
体チップの載置部と半導体チップとの間に絶縁性フィル
ムを介している事を特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein an insulating film is interposed between the mounting portion of the semiconductor chip and the semiconductor chip.
体チップの載置部の半導体チップの載置されている面の
裏面側に放熱用部材が載置されている事を特徴とする半
導体装置。5. The semiconductor device according to claim 1, wherein a heat dissipation member is mounted on the back surface side of the mounting surface of the semiconductor chip on which the semiconductor chip is mounted. .
体チップの少なくとも裏面の一部もしくは少なくとも裏
面を構成する一辺を介して保持し、半導体チップの載置
部に載置する事を特徴とする半導体装置の製造方法。6. The semiconductor device according to claim 1, wherein the semiconductor chip is held on at least a part of the back surface or at least one side forming the back surface and mounted on the mounting portion of the semiconductor chip. Manufacturing method of semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5173224A JPH0729925A (en) | 1993-07-13 | 1993-07-13 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5173224A JPH0729925A (en) | 1993-07-13 | 1993-07-13 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0729925A true JPH0729925A (en) | 1995-01-31 |
Family
ID=15956444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5173224A Pending JPH0729925A (en) | 1993-07-13 | 1993-07-13 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0729925A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7009304B2 (en) | 2002-04-24 | 2006-03-07 | Renesas Technology Corp. | Resin-sealed semiconductor device |
| JP2008300587A (en) * | 2007-05-31 | 2008-12-11 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
-
1993
- 1993-07-13 JP JP5173224A patent/JPH0729925A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7009304B2 (en) | 2002-04-24 | 2006-03-07 | Renesas Technology Corp. | Resin-sealed semiconductor device |
| JP2008300587A (en) * | 2007-05-31 | 2008-12-11 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
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