JPH07288685A - Image processing unit - Google Patents

Abstract

PURPOSE:To improve the image quality of a binarized image by using a digital spatial filter means in common for edge emphasis processing and noise elimination processing effects and for image processing effect selection so as to reduce the entire circuit scale. CONSTITUTION:Four-line data are given to filters 201A, 201B to extract an edge component, image area separate sections 202A, 202B discriminate whether the data are an image including binary information such as a character of an input image or an image such as a background based on edge component data from the filters and provide an output of the result to changeover switches 205A, 205B. An adder 203A adds one of the four-line data and output data from the filter 201A to apply the sum to the switch 205A as image data whose edge component is emphasized. Then a subtractor 204A subtracts the data and the output of the filter 201A to unsharpen the edge and provides the result to other input terminal of the switch 205A as data whose noise component is suppressed and the data are compared with a threshold level and binarized data are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image handling device,
In particular, the present invention relates to an image handling device capable of high-speed processing and having a reduced memory capacity.

[0002]

2. Description of the Related Art Facsimile machines, copying machines, etc. are used as image handling devices for photographing document information, information written on a blackboard or a white board, converting it into binary image information and outputting it, and storing it in a memory. In this type of image handling apparatus, in order to capture image information, a photoelectric conversion element such as a CCD is used as a line sensor to optically or mechanically scan in the sub-scanning direction.

[0003]

As described above, in the conventional image handling apparatus, the line sensor is optically arranged in the sub-scanning direction.
It mechanically scans and captures two-dimensional image information.
Therefore, it takes time to capture image information, and there is a problem in terms of high-speed capture processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image handling apparatus capable of capturing image information at high speed while keeping the memory capacity to a minimum.

[0005]

In order to solve the above-mentioned problems, the image handling apparatus of the present invention has a spatial frequency of the image based on the supplied first data which is digital coded image data. And a digital spatial filter means for obtaining second data representing a high degree of the image data, and an effect of emphasizing an edge of an image by adding the second data to the first data in a dynamic manner. Edge enhancement processing means for obtaining third data, which is image data, and an effect of removing high frequency noise of the image by differentially acting the second data on the first data Noise removal processing means for obtaining fourth data, which is data, and for selectively deriving either the third data or the fourth data based on the second data. In the image handling device including an image processing effect selection means, on the basis of the multivalued image data to the formed by digital coded is the supplied to the data corresponding to the multivalued image data to a certain threshold level 2
Based on the first binary coded image data forming means for obtaining the first binary coded image data which has been subjected to the value conversion process, and the multivalued image data or data corresponding to the multivalued image data. Second binary coded image data forming means for obtaining second binary coded image data which has been subjected to pseudo halftone binary coding processing, and the digitally coded multi-valued image data or Image binarization for adaptively selecting and deriving either the first binary coded image data or the second binary coded image data based on data corresponding to the multi-valued image data. And a processing selection unit.

[0006]

In the present invention, as described above, the digital spatial filter means is used both for obtaining the edge enhancement processing and noise removal processing effects and for selecting the image processing effect (image area separation).

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a configuration block diagram showing an example of an image handling apparatus related to the present invention. In this example, the mirror is scanned and the captured image is divided into a plurality of regions and captured by a two-plate optical system including two imagers (CCD). For example, as shown in FIG. 2A, areas A, B,
To capture the images of C and D, use the mirror 1A with a, b,
Rotate in steps so that they come to positions c and d,
The image information of each divided area of A, B, C and D is taken into the imager through the lens and the optical system 1B. At this time, as shown in FIG. 7B, imagers IA and IB are arranged in the vertical direction (two-plate optical system), and the upper and lower two-divided images of each divided area are captured.

In the two-plate optical system 2, for example, as shown in FIG. 3, an image incident through a lens 2A having an infrared cutoff and an optical LPF characteristic passes through a half prism 2B, and transmitted light passes through an imager IB. The image is formed symmetrically in the vertical and horizontal directions, is reflected by the half prism 2B, and is inverted by the mirror to be imaged on the imager IA.

Imager I output from the two-plate optical system 2
The respective output signals of A and IB are subjected to predetermined processing in the monochrome process sections 3A and 3B, converted into video signals, and stored in the frame buffer 4. The write / read address of the frame buffer 4 is controlled by the memory control unit 14. The frame buffer 4 outputs composite data of the image data from the two imagers IA and IB in which the deviation in the arrangement relationship of the imagers is compensated.

The interpolation section 5 performs interpolation processing based on the image data read from the frame buffer 4 and outputs one piece of image information data. The image data from the interpolation unit 5 is gamma-corrected by the gamma correction unit 6, subjected to halftone processing by the pseudo halftone processing unit 7, and sent to the changeover switch 10.

The edge emphasizing unit 8 performs an edge emphasizing process on the output data from the interpolating unit 5 in order to clarify a black and white part such as an image such as a character or a line drawing. The binarization unit 9 compares the threshold level supplied from the CPU 13 and performs binarization processing. The AF / AE information extraction unit 11 extracts AF information for focus control and AE information for exposure control based on the image data from the interpolation unit 5 and sends the AF information to the CPU 13 to output the two-plate optical system. Drive the lens system of.

After the control of the CPU 13, the image area separating section 12
It is determined whether the image captured based on the image data from the interpolation unit 5 includes a halftone such as a background or a photograph, or a binary image such as a character, and the changeover switch 10 is determined based on the determination result.
To control. That is, the change-over switch 10 outputs the output from the pseudo-halftone processing unit 7 if the captured image is an image including a halftone, and the output from the binarization unit 9 if the captured image is a binary image. .

The boundary buffer 16 receives the control of the memory control 15 and stores the output data from the binarizing unit 9. The overlapping portion of two adjacent images (images A and B in the example of FIG. 2) captured by the predicted mirror scan is read from the boundary buffer 16 and the correlation is detected by the correlation detector 17. To be done. Deviation calculation unit 18
Is the shift amount between the images captured based on the correlation information detected by the correlation detection unit 17 (for example, horizontal shift x, vertical shift y, rotational shift θ),
It is supplied to the memory control unit 14.

The memory control unit 14 includes a CPU 13
The amount of deviation of the imager supplied from the
Based on the deviation information from, the read address that compensates for these deviations is supplied to the frame buffer 4.

The image data output from the change-over switch 10 is controlled by the CPU 20, subjected to a compression process well known in a facsimile or the like in the compression unit 19, and stored in the card via the card interface (I / F) 21. It

FIG. 4 shows the monochrome process units 3A and 3B.
The configuration block diagram of is shown. The output from the imager 31A, which is the processing system of the imager IA, is sampled by the correlated double sampling (CDSI) unit 32A, the gain is adjusted by the AGCI unit 33A, and then the black level is clamped by the clamp I unit 34A. After that, it is converted into digital data by an A / D converter (ADCI) 35A. Imager 3 which is the processing system of Imager IB
1B, correlated double sampling (CDSII) unit 32B,
The AGC unit 33B, the clamp II unit 34B, and the A / D converter (ADCII) 35B have the same functions as the processing system of the imager IA.

The operation of each part of these two systems is performed by the clock CL.
A timing generator (TG) that operates based on a synchronization signal from a signal generator (SSG) 37 that responds to K1.
I) 36A and (TGII) 36B.

FIG. 5 shows an operation timing chart of the apparatus shown in FIG. The upper numbers 0 to 30 in FIG.
Indicates the field number. The fields are alternating fields of even E fields and odd O fields. VD indicates a vertical synchronizing signal.

The operations of imager exposure, imager odd field and even field reading, frame buffer writing (W), binarization processing, boundary buffer writing (W), correlation detection and mirror scan are performed. Done. In the example of FIG. 2, the frame number 24 for which the imager exposure from the area A to the area D is completed four times is 24.
Then, after the final screen is captured, after the post-processing, writing to the memory card is started at frame number 30. As a result, the image acquisition is completed in about 0.5 seconds,
Higher speed is possible.

FIG. 6 is a block diagram showing the configuration of the image handling apparatus according to the present invention, and this example can reduce the memory capacity as compared with the above example. This example has the same circuit configuration for each system of the two imagers as in FIG.
The following description will focus on the A Imager IA system.

CCD 101A as imager IA
The output from is passed through the correlated double sampling section 102A, converted into digital data by the A / D converter 103A, and then written into the field memory 104A.
The area integration unit 105A performs well-known area integration processing based on the digital image data to generate AE data, and supplies the AE data to the CPU 113.

1H delay units (DL) 106A and 107A
Outputs the output from the field memory 104A and the output from the A / D converter 103A with a time delay of 1H. The threshold level generation unit 108A generates a threshold level for binarization based on the data from the area integration unit 105A, and the binarization dither unit 10
9A. The binarization dither unit 109A performs binarization and dither processing based on the inputted information of four lines before and after, and stores the result in the memory 110A under the control of the memory control unit 114.

The image data captured and processed by the CCDs 101A and 101B read out from the memories 110A and 110B in this way are combined and compressed in order to generate a single image by being output by the changeover switch 115.
It is written in the card 117 via the processing unit 116 having a card interface function.

Comparing this example with the example shown in FIG. 1, instead of the frame memory, the field memories 104A, 104 are used.
Since B is used and the binary data is stored in the memory 110A, the purpose can be achieved with a memory capacity that is about half that of the configuration of FIG.

FIG. 7 shows an operation timing chart of this example. In the figure, the lower numbers indicate frame numbers. In this example, since the field memory is used, the storage in the imager is performed every odd (O) field and even (E) field, and the reading of the odd field data and the even field data from the imager is performed. Writing to the field memory and area integration processing are performed during the accumulation period of one field,
After the processing of the two image (A and B) data is completed, the positional deviation (x, y, θ) between the two images is detected. Also, 2
Writing to the value memory 110A and writing to the card,
Writing to the boundary memory 16 is performed at the timing shown. By thus performing the binarization processing on two lines at the same time, higher speed processing becomes possible.

The mirror scan can be performed immediately after the end of exposure (accumulation in the imager), and as shown in FIG. 2, the capture of the image areas A to D is completed in the 13th field, and the accumulation in the imager is completed. (Exposure) is completed.
Further, after post-processing, writing to the memory is started in the 16th field. As a result, as is clear from the comparison with the timing chart shown in FIG. 5, the image can be captured in half the time of the first example, and the speedup can be achieved.

FIG. 8 is a block diagram showing the construction of an embodiment of the image handling apparatus according to the present invention, which is characterized by the binarization processing in the above-mentioned example and improves the image quality. In FIG. 8, the components having the same numbers in the two processing systems have the same function.

In the present embodiment, four lines of data (data of 0H, 1H, 2H, 3H) before and after being supplied to the binarization dither unit 109A shown in FIG. , Laplacian filters) 201A and 201B.

The image area separation units 202A and 202B determine whether the input image is an image including binary information such as characters or an image such as a background based on the edge component data from the filters 201A and 201B. , And outputs the determination result to the changeover switches 205A and 205B. The adder 203A is 4
One of the line data (1H data in this example) and the output data of the filter 201A are added to each other, and the changeover switch 205 is used as image data in which edge components are emphasized.
Supply to one input terminal of A. The subtractor 204A subtracts the one data and the output data of the filter 201A to round the edges, and supplies it to the other input terminal of the changeover switch 205A as image data in which a noise component is suppressed.

The changeover switch 205A is used for the image area separation section 20.
When a discrimination signal that the image is a binary image is supplied from 2A,
The output of the adder 203A is switched and output. Further, when the determination signal that the image is the background image is supplied, the subtractor 204
The output of A is switched and output. Comparator 206A
Output data from the changeover switch 205A to the CPU
And outputs the binarized data in comparison with the threshold level supplied from.

The gamma dither unit 207A is the image area separation unit 2
When it is determined that 02A is a halftone image, the input 1H data is subjected to pseudo halftone processing and output. The changeover switch 208A includes a comparator 206A and a gamma dither unit 20 based on the determination signal from the image area separation unit 202A.
The output from 7A is switched and output. Serial-parallel conversion (S /
The P) unit 209A converts serial data into parallel data and outputs the parallel data.

In this embodiment, the filters 201A and 201A
Since B is shared for image area separation and image processing, the circuit can be miniaturized. Further, it goes without saying that one system can be used instead of the two system.

By the way, in the above embodiment, the divided images are captured by the two imagers. However, for example, an average brightness difference may occur between the divided areas in charge of the respective imagers. In some cases, the exposure conditions are different between the two, and when the two divided images are combined, unevenness may occur in the brightness at the connecting portion between the two images.

Therefore, the following example relating to the present invention relates to a method of generating AE data which solves such a problem and corrects the exposure variation between imagers.

FIG. 9 is a timing chart for creating sensitivity correction data based on AE data. In this example, before the actual exposure, the exposure is started from the field one field before (the first field), and the exposure difference between the two imagers is obtained during the actual imager exposure.

This example is effective when the two imagers IA (CCD1) and IB (CCD2) have overlapping image pickup portions in the shaded area as shown in FIG. 10A, but FIG. Needless to say, it is also effective when overlapping in the vertical direction as shown in FIG. The square division area in FIG.
An area where brightness information is obtained by area integration is shown.

The threshold level for binarization can be determined as follows based on the brightness information obtained above. That is, B1 and B2 and y1 and y
2 is the brightness data of the black level and the area of the image data obtained by the imagers IA and IB, the difference ΔB between the coefficient k and the brightness is k = (Y2-B2) / (Y1-B1) ΔB = B2-B1 and the threshold levels T1 and T2 are defined as T2 = k (T1-B1) + B2 (see FIG. 10C).

The dither for carrying out the halftone processing can be constructed, for example, as shown in FIG. In FIG. 11, the data read from the dither ROM 301 is amplitude-multiplied by the multiplier 302 and then added with the offset value by the adder 303. The result of this addition serves as a reference signal in the comparator 304 and is compared with the input signal to obtain a dither output.
Here, if the amplitude is widened, the gradation reproduction range is widened, and if the offset value is increased, it becomes dark, so that the dither output can be controlled by arbitrarily changing the amplitude and the offset value.

[0039]

As described above, in the image handling apparatus according to the present invention, the digital spatial filter means obtains the edge enhancement processing and the noise removal processing effect and the image processing effect selection (image area separation). Since it is commonly used for image processing, the circuit scale can be reduced as a whole, and the normal binary coded image data or the pseudo halftone binary coded image can be obtained depending on the state of the original image (image area separation). Since the data is adaptively selected and derived, the quality of the binarized image is improved as a whole.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an example of an image handling apparatus related to the present invention.

FIG. 2 is a diagram for explaining the example of FIG.

FIG. 3 is a diagram for explaining the example of FIG. 1.

FIG. 4 is a configuration block diagram of monochrome process units 3A and 3B in FIG.

5 is an operation timing chart of the example shown in FIG. 1. FIG.

FIG. 6 is another block diagram of the configuration of the image handling apparatus related to the present invention.

7 is a diagram showing an operation timing chart of the example shown in FIG.

FIG. 8 is a configuration block diagram showing an embodiment of an image handling apparatus according to the present invention.

9 is an operation timing chart of the embodiment shown in FIG.

FIG. 10 is a block diagram of still another configuration of the image handling apparatus related to the present invention.

11 is a diagram illustrating the example shown in FIG.

[Explanation of symbols]

 1 Mirror Scan 2 2 Plate Optical System 3A, 3B Monochrome Process Section 4 Frame Buffer 5 Interpolation Section 6 Gamma Correction Section 7 Pseudo Halftone Processing Section 8 Edge Enhancement Section 9 Binarization Section 10 Changeover Switch 11 AE, AE Information Extraction Section 12 Image area separation unit 13, 20 CPU 14, 15 Memory control unit 16 Buffer 17 Correlation detection unit 18 Deviation calculation unit 19 Compression unit 21 Card interface (I / F)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/40 101 C

Claims (1)

[Claims] 1. Digital spatial filter means for obtaining second data representing a high degree of spatial frequency of the image based on the supplied first data which is digitally coded image data, and Edge enhancement processing means for obtaining third data, which is image data, to which the effect of enhancing the edge of the image is added by dynamically acting the second data on the first data, and the first data.
Noise removal processing means for obtaining fourth data which is image data to which the effect of removing high frequency noise of the image is added by differentially acting the second data on the data of And an image processing effect selecting means for selectively deriving either the third data or the fourth data on the basis of the above, the supplied multi-valued digital code. A first binary coded image for obtaining first binary coded image data by subjecting image data or data corresponding to the multi-valued image data to binarization processing based on a constant threshold level Data forming means and second binary coded image data obtained by performing pseudo halftone binary coding processing based on the multivalued image data or data corresponding to the multivalued image data. The second binary coded image data forming means, and the digitally coded multi-valued image data or data corresponding to the multi-valued image data. Or the second 2
An image handling device, comprising: an image binarization processing selecting means for adaptively selecting and deriving any one of the value coded image data.