JPH07283339A - Semiconductor device - Google Patents

Abstract

PURPOSE:To extremely reduce failure even for a long use by a brazing material with a higher melting temperature than that for joining a semiconductor element. CONSTITUTION:A metal support plate 1 and an insulation substrate 2, the metal support plate 1 and a heat-resistance insulation plate, the insulation substrate 2 and a metal cooling plate 3, the heat-resistance insulation plate/intermediate metal plate and the metal cooling plate 3/a heat stress relaxing material 4, and the intermediate metal plate and the heat tress relaxing material 4 are joined by a hard brazing material and a brazing material with an approximately 620 deg.C, melting point. Then, these members to be brazed and a semiconductor element 5 are joined by a soft brazing material. Finally, the metal cooling plate 3 and a conductor 6 for electrically connecting the intermediate metal plate are joined by a soft brazing material. Silicon gel 9 is filled to secure the breakdown strength of the semiconductor element and then epoxy resin is filled to airtightly seal silicon gel and to fix an electrode 13 and an electrode 11 is mounted. Heat fatigue resistance can be improved since a part which is easily deformed can be joined firmly and heat resistance improves by joining with a hard brazing material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power controlling semiconductor device such as an IGBT, and more particularly to a semiconductor device having a high reliability with little deterioration in thermal characteristics even with a heating / cooling temperature cycle during use. Is.

[0002]

2. Description of the Related Art When a semiconductor device operates, power loss is unavoidable, which causes heat generation in a semiconductor substrate. In order to operate the semiconductor device safely and stably, it is necessary to effectively dissipate the heat generated during the operation of the semiconductor device to the outside of the package. This heat dissipation is usually achieved by dissipating the heat from the semiconductor substrate, which is a heat source, into the air through each member connected to the semiconductor substrate. A brazing material for interposing substrates of different materials is interposed in the heat conduction path.

Conventionally, a supporting member of a semiconductor device often serves as one electrode of the semiconductor device. For this reason, the semiconductor substrate must be electrically conductively connected to the support member, and the brazing material for joining the substrates is a soft brazing material with a high melting point of 450 ° C. or less, such as Pb-Sn solder. It was joined.

A typical conventional semiconductor device has a structure shown in FIG. In the figure, 111 is a Cu support plate, 222 is an alumina insulating plate, 333 is a Cu heat radiating plate, 444 is a thermal stress buffer plate (hereinafter abbreviated as buffer plate) such as Mo, W, 555 is a Si chip, The four places between these members are joined with soft solder. Each of these members is simultaneously joined with the same soft solder, or is hierarchically brazed with soft solders having different melting points.

In such a semiconductor device, each member causes thermal expansion due to heat generation due to power loss of the Si chip 555 when the device is used, and thermal contraction occurs when the device is stopped. The semiconductor device repeatedly expands and contracts after being used and stopped as described above, and the thermal stress due to the difference in the thermal expansion coefficient between the members on both sides of the solder joint is repeatedly applied to the four solder joints. As a result, the solder causes fatigue failure and cracks occur. This crack spreads as the number of thermal cycles increases, and the heat is not sufficiently dissipated, that is, the heat resistance is increased and the cooling is not sufficiently performed, and the Si chip 555 is destroyed by the heat.

As described above, as a means for suppressing the generation of cracks in the joint due to thermal stress, there is a method of increasing the strength of the joint using a combination of materials having similar thermal expansion coefficients.
As a concrete method of the above, a method of arranging a thermal stress buffer plate such as Mo and W adjacent to each joint as used in the above conventional apparatus is disclosed in JP-A-4-287952. There is. As a specific method of JP-A-5-136286, a method is disclosed in which a net-like body is inserted into the joint portion of the soft solder so as to make the thickness of the joint portion uniform and secure the joint strength.

[0007]

The above-mentioned method of disposing the thermal stress buffer plate at each joint has a great effect on alleviating the thermal stress and has a great effect on suppressing the occurrence of cracks, but the number of members to be joined is large. Since the number of assembling steps increases, the number of assembling steps increases, the cost increases, and since the number of bonding surfaces increases, there is concern that the yield may decrease due to defective bonding. On the other hand, the method of inserting the reticulate body improves the bonding strength as compared with the method of not inserting the reticulate body, but there is a limit to the improvement of the bonding strength as long as soft solder having a low melting point is used. As a result, the fatigue strength is insufficient with respect to the cyclic stress due to the thermal deformation of the substrate due to thermal deformation, it is not possible to completely suppress the occurrence of cracks during long-term use, and there is a possibility of failure due to an increase in thermal resistance. Could not be wiped out.

An object of the present invention is to provide a highly reliable semiconductor device in which failure does not occur even during long-term use.

[0009]

An object of the present invention is to dispose and bond a plurality of heat resistant insulating plates on a metal supporting plate, and to form an intermediate area on the heat resistant insulating plate having a smaller area than that of the heat resistant insulating plates. In a semiconductor device in which a metal plate is placed and joined, a base metal plate is placed and joined on the intermediate metal plate, and a semiconductor element is placed and joined on the base metal plate, the melting temperature of the brazing filler metal of the metal support plate is This is achieved by using a brazing material having a melting temperature higher than that of the brazing material for joining the semiconductor elements. Further, in the semiconductor device having the above structure, the bonding of the semiconductor element is
The joining may be performed with a soft brazing filler metal having a melting point of less than 450 ° C, and the others may be joined with a hard brazing filler metal having a melting point of 450 ° C or higher.

In the semiconductor device having the above structure, the heat-resistant insulating plate and the metal supporting plate may be joined with a hard brazing material having a melting point of 450 ° C. or higher.

In the above semiconductor device, the melting point is 450 ° C.
The above hard brazing material may be composed of two or more kinds of components selected from the group of Cu, Ag, Zn, Sn, P, Au, Ni, Cd, and Ti.

In the above semiconductor device, the melting point is 450 ° C.
The soft brazing material below may be composed of two or more kinds of components selected from the group of Sn, Pb, Sb, Ag, In, Bi, Cd, Cu, Au and P.

In the above semiconductor device, it is effective that the joining portion is made of a hard brazing material having a melting point of 450 ° C. or higher, and is joined by hierarchical brazing using hard brazing materials having different melting points. In the above semiconductor device, a relay terminal of a metal conductor may be arranged and bonded on the metal support plate and the heat resistant insulator by using an adhesive.

[0014]

When the substrates are joined using the brazing filler metal, they are placed in a furnace such as a diffusion furnace in order to join the substrates having a large area uniformly, and further in an inert atmosphere to suppress the oxidation of each member. , The brazing material is melted and joined. In a conventional semiconductor device, when an attempt is made to join a semiconductor element using a hard brazing material having a high melting point, the electrical characteristics of the semiconductor element deteriorate due to heat during heating. Therefore, the semiconductor element is joined with Pb having a melting point of about 300 ° C. -Sn solder is used. Moreover, in order to reduce the amount of thermal deformation during joining, it is advantageous to use a brazing material having a low joining temperature. Therefore, in a conventional power control semiconductor device, joining is performed using a soft brazing material having a melting point of less than 450 ° C.

In addition, the power control semiconductor device has a large substrate area in response to the recent demand for large power control, and it is difficult to integrally bond the same by using the same brazing filler metal because of the precision of the substrate manufacturing process. To secure the strength of the bonding layer,
Although it is necessary to keep the thickness of the brazing material layer above a certain level, it is very difficult to control the thicknesses of the bonding layers of a large number of parts, especially a plurality of semiconductor devices, simultaneously to a certain value. For this reason, it is not possible to join them all with the same brazing material in the manufacturing process using the current technology, and the assembly is performed by hierarchical brazing. Hierarchical brazing refers to a method of first joining with a brazing material having a high melting point, and then using a brazing material having a temperature at which the first joined portion does not remelt, that is, a brazing material having a melting point lower than the melting point of the first brazing material.

Conventionally, a semiconductor element is bonded to a base metal plate, then a wire bonding step for wiring the electrodes of the semiconductor element is performed, and then the intermediate metal plate is bonded and then an insulating substrate. It was customary to assemble them in order, starting from the one with the smallest area. It is considered that this is because it is more advantageous to sequentially assemble the small substrates in terms of improving the assembly accuracy. Therefore, the conventional brazing material has the highest melting point of the brazing material for joining the semiconductor element, and the lowest melting point of the brazing material for joining the metal supporting plate.

However, the cracks at the joints during use were mainly generated between the metal supporting plate or the intermediate metal plate having a large difference in thermal expansion coefficient and the heat resistant insulating plate. In order to suppress the occurrence of cracks at the joint, a metal brazing plate or an intermediate metal plate and a heat-resistant insulating plate are joined using a hard brazing material having a shear strength higher than that of the soft brazing material, and then a semiconductor element is formed using the soft brazing material. If the method of joining is used, cracks do not occur even after long-term use. The tensile strength of these brazing filler metals themselves differs depending on the components, but is generally higher for those with a higher melting point.
Each of the brazing materials has a tensile strength of about 200 MPa or more, which is four times or more that of the conventional Pb-Sn soft brazing material having a tensile strength of about 50 MPa. In this way, if the brazing filler metal itself having high mechanical strength is applied, peeling of the connection portion can be avoided.

However, since joining all with a hard brazing material damages the semiconductor element, it is necessary to use a soft brazing material for joining the semiconductor elements. In this case, the soft brazing material is pre-joined with the hard brazing material. It is important to join using materials. Also, the Cu terminal of the electrode will be joined later, so it will be joined using a soft brazing material. The electrodes can be connected by using an adhesive agent instead of the soft brazing material.

Among the brazing filler metals applied to the connection between the respective members,
A high melting point brazing material is applied first, then a hard brazing material lower than the melting point of the first brazing material (low melting point brazing material), and the semiconductor element is joined with a low melting point soft brazing material. A highly reliable semiconductor device can be obtained by applying a so-called hierarchical junction method utilizing a so-called melting point difference.

Consider a case where the connection of three layers is specifically required. As the first high melting point brazing material, a silver brazing material (JIS standard BAg-1 to BAg-24) having a melting point of about 750 ° C. is used. The second brazing filler metal has a lower melting point than the first brazing filler metal, approximately 650 ° C.
It is made of phosphorous copper brazing filler metal (JIS standard BCuP-1 to BCuP-6) or low melting point phosphorous copper brazing filler metal (Cu-15% Ag-3.5% P-9.5% Sn-1% Au). Since the semiconductor element is mounted on the last connection, solder is used so as not to damage the semiconductor. Among solders, a relatively high melting point solder is used to improve reliability. For example, a solder containing Sn, Sb, Ni, P having a melting point of 250 ° C. is used.

In this way, when the connecting portions are of three layers, the melting point of the brazing material is also three-step. The above-mentioned brazing filler metal is shown as a component of so-called silver brazing filler metal,
A brazing filler metal with a melting point of 750 ° C and containing Ag, P, Cu components, about 65
A so-called phosphor copper brazing material having Ag, P, Sn, and Cu components and having a melting point of 0 ° C. can be applied.

There is also a semiconductor module in the case of four-level connection. In that case, considering the ease of processing, for example, two layers are joined at once with a brazing material at 750 ° C. Next 650 ℃
Join with brazing material. Finally, the semiconductor element is joined with solder having a low melting point.

A method different from the above can be applied to three layers. 2
Join the floors at once with brazing material at 650 ° C. Next, the semiconductor element and the electric terminal are joined using solder.

By properly using the brazing material and the solder as described above, it is possible to obtain a highly reliable semiconductor device in which the components are firmly joined.

In the semiconductor device of the present invention, different materials are connected to each other. Naturally, a difference in thermal expansion occurs due to heating and cooling. Therefore, the joining temperature is preferably as low as possible, and a brazing material having a low melting point and a good thermal conductivity should be applied in consideration of the joining strength.

As described above, it was found that a highly reliable semiconductor device that can withstand long-term use can be obtained by using the melting point difference of the brazing material and combining the solders that do not damage the semiconductor element.

The heat-resistant insulating substrate is preferably an alumina substrate in terms of low cost and thermal expansion coefficient, but aluminum nitride or SiC substrate is suitable in terms of heat conduction. These are appropriately selected according to the power capacity used.

As the adhesive used for joining the metal conductors, low melting point glass, silicon resin, epoxy resin, acrylic resin and the like are used. It is suitable that these adhesives have as high thermal conductivity as possible.

[0029]

【Example】

(Example 1) An example of the present invention will be described with reference to the drawings. 1 shows a configuration of a semiconductor device of Example 1. In Figure 2, 1 is pure C
u (purity 99.9% or more) metal support plate (size 100 mm × 100 mm,
10 mm thick), 2 and 21 are heat-resistant insulating plates made of alumina (size 2
0 mm × 50 mm, thickness 1 mm), 3, 31 are pure Cu (purity 99.9% or more) intermediate metal plate (size 15 mm × 45 mm, thickness 5 mm), 4 is Mo base metal plate (size 15 mm × 20 mm) , Thickness 2 mm), and 5 are semiconductor elements (size 15 mm × 20 mm, thickness 2 mm), and the conductor 6 electrically connecting these elements is a pure Cu electrode plate. Assembling method 1 and 2, 1 and 21, 2 and 3, 21 and 31 and 3 and 4, 31 and 4
Hard solder, i.e. 45% Ag-15% Zn-24% Cd-16% Cu by weight about 620
Bonding is performed with a brazing material (JIS BAg-1) having a melting point of ° C. Next, these brazed members and the semiconductor element of 5 were joined using a soft solder, that is, a brazing material having a melting point of about 240 ° C. of Sn-5% Sb-0.6% Ni-0.05% P. Finally, the conductor 6 for electrically connecting 3 and 31 was joined by using a soft brazing filler metal having a melting point of about 180 ° C. of Pb-37% Sn. In this way, a semiconductor substrate was produced. After covering the board with epoxy case 12,
A silicon gel 9 for ensuring the withstand voltage of the semiconductor element is filled. Next, hermetically sealing the silicon gel and the electrode 1
3 is fixed, epoxy resin is filled, the electrode 11 is attached, and the lid 14 made of epoxy is attached to complete the semiconductor module shown in FIG. The metal support plate at the bottom of the IGBT substrate is fixed in place by screws.

As a comparative example, a semiconductor substrate having a conventional structure as shown in FIG. 6 was produced. Example of metal support plate size
Same as 1. 111 is a pure Cu (purity 99.9% or more) support plate, 2
22 is an alumina insulating plate (99% purity), 333 is pure Cu (99.9% purity)
) Is a heat sink, 444 is a Mo (purity 99%) heat buffer, and 555 is a semiconductor element. These members are joined with a soft brazing material of less than 450 ° C. The sequence of bonding is first Sn-5% S with 555 Si chips and 444 Mo thermal buffer with a melting point of about 240 ° C.
Bonded using b-0.6% Ni-0.05% P. Next, this bonded part is connected to the alumina insulation plate 222 and the alumina insulation plate 222.
And the Cu support plate of No. 3 are similarly joined using a Pb-37% Sn soft brazing material having a melting point of about 180 ° C. All joints are joined with soft solder below 450 ° C. This is also a semiconductor module as shown in Fig. 1.
It was completed as Le.

(Embodiment 2) FIG. 3 shows a part of an IGBT substrate in which the size of the metal supporting plate is the same as that of Embodiment 1. Place a heat-resistant insulator made of alumina or a pure Cu (purity 99.9% or higher) metal conductor 7 on the pure Cu (purity 99.9% or higher) metal support plate 1, and put pure Cu (purity 99.9% or higher) on it. ) Is equipped with conductor terminal 8. Here, 1 and 7 were connected with an epoxy adhesive. Also, 7 and 8 were joined using Pb-37% Sn soft brazing filler metal having a melting point of about 180 ° C.

(Embodiment 3) FIG. 4 shows a semiconductor device structure without the intermediate metal plate of FIG. 10 is a metal support plate made of pure W (purity 99.9%) (size 200 mm × 200 mm, thickness 5 mm), 200 and 210 are heat resistant insulating plates made of aluminum nitride.
(Purity 99%, size 50 mm × 50 mm, thickness 2 mm), 201 and 202, 211
Reference numerals 212 and 212 are layers (thickness: about 100 μm) metallized with Cu so that a heat-resistant insulating plate can be easily joined, and 50 is an IGBT semiconductor element (size 20 mm × 20 mm, thickness 2 mm). Reference numeral 60 electrically connecting these is a conductor of pure Cu (purity 99.9% or more).

For assembly, 10 and 201, 211 are joined with a hard brazing material of 50% Ag-16% Zn-18% Cd-16% Cu having a melting point of about 635 ° C. Next, these brazed members and the IGBT semiconductor device 50
Was joined using a soft brazing material of Sn-5% Sb-0.6% Ni-0.05% P having a melting point of about 240 ° C. Finally, Pb-37% Sn, which has a melting point of about 180 ° C, is used to electrically connect 202 and 60 and 212 and 60 electrically.
It joined using the soft brazing filler metal of. This was incorporated as a semiconductor module shown in FIG. The manufacturing method is the same as in the first embodiment.

(Embodiment 4) FIG. 5 shows a part of an IGBT substrate having a metal supporting plate of the same size as that of Embodiment 3. A heat-resistant insulating plate 7 made of aluminum oxide is placed on a metal support plate 10 made of pure Cu (purity 99.9%), and pure Cu (purity 9
99.9%) Conductor terminal 8 is mounted. Here, 10 and 7 were connected with an epoxy adhesive. Also, 7 and 8 were joined with a soft brazing metal material.

The IGBT module using the IGBT substrates shown in FIGS. 2, 4 and 6 manufactured by the above-mentioned joining was subjected to a thermal fatigue life cycle test by turning ON / OFF electric conduction, and the electric characteristics of the semiconductor element were confirmed. The life until deterioration due to generated heat, so-called thermal fatigue life was measured. The larger the number of cycles, the longer the life in actual use. The results are shown in Fig. 7. The figure shows the range of data variation and the average value. As can be seen from the figure, the conventional semiconductor device (FIG. 6 of Example 1) has a thermal fatigue life cycle of about 10 ³ cycles, whereas the present invention has the structure of FIG. 2 (Example 1). The semiconductor device showed an average value of about 10,000 cycles, and the semiconductor device having the structure of FIG. 4 (Example 3) showed an average value of about 30,000 cycles. As described above, it was proved that the thermal fatigue resistance is remarkably improved by appropriately using the hard brazing material and the soft brazing material as compared with the conventional joining using the soft brazing material.

The improved thermal fatigue resistance is due to the fact that the first joining with the hard solder has a high joining strength at the portion where the thermal deformation is most likely to occur and also has an excellent heat resistance. After that, by joining other parts with a soft solder of less than 450 ° C., a semiconductor device with small thermal deformation can be obtained.

The semiconductor device having the structure shown in FIG. 4 showed the best results because the structure was simplified and the amount of thermal deformation was the smallest accordingly.

Further, the semiconductor devices having the structures shown in FIGS. 3 and 5 also showed the thermal fatigue life characteristics which are almost the same as those of the semiconductor devices having the structures shown in FIGS. 2 and 4.

[0039]

As described above, according to the present invention,
Since a structure with low thermal fatigue can be maintained,
It is possible to obtain a semiconductor device having a significantly improved thermal fatigue life cycle due to ON / OFF.

[Brief description of drawings]

FIG. 1 is a sectional view of an IGBT module.

FIG. 2 is a schematic sectional view showing an embodiment of the present invention.

FIG. 3 is a schematic sectional view in which conductor terminals of the present invention are arranged.

FIG. 4 is a schematic sectional view of a simplified structure of the present invention.

FIG. 5 is a schematic sectional view in which conductor terminals of the present invention are arranged.

FIG. 6 is a schematic sectional view showing a conventional semiconductor.

FIG. 7 is a diagram showing the relationship between the semiconductor device having the present invention and the conventional structure and the number of thermal fatigue life cycles.

[Explanation of symbols]

1, 111: Metal support plate, 2, 21, 222: Heat resistant insulation plate, 3, 3
1, 333: intermediate metal plate, 4, 444: base metal plate, 5, 50, 555: semiconductor element, 6: brazing layer, 7: aluminum wire, 9, 10: sealing resin, 11: electrode, 12 pieces − 15, 150: Conductor metal 16: Heat-resistant insulating plate 17: Conductor terminal 18: Metal support plate 20, 210: Heat-resistant insulating plate, 201, 202, 211, 212: Metal layer

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H05K 7/20 B H01L 29/78 321 J (72) Inventor Masao Tsuruoka 3-chome, Saiwaicho, Hitachi, Ibaraki No. 1 Stock company Hitachi Ltd. Hitachi factory

Claims (7)

[Claims] 1. A plurality of heat-resistant insulating plates are arranged and joined on a metal supporting plate, and an intermediate metal plate having an area smaller than that of the heat-resistant insulating plate is arranged and joined on the heat-resistant insulating plate. In a semiconductor device in which a base metal plate is placed and joined on a plate, and a semiconductor element is placed and joined on the base metal plate, the melting temperature of the joining brazing material of the metal supporting plate is higher than that of the joining brazing material of the semiconductor element. A semiconductor device characterized by using a brazing material for bonding having a temperature higher than a melting temperature. 2. A plurality of heat-resistant insulating plates are arranged and joined on a metal supporting plate, and an intermediate metal plate having an area smaller than that of the heat-resistant insulating plate is arranged and joined on the heat-resistant insulating plate. In a semiconductor device in which a base metal plate is arranged and bonded on a plate, and a semiconductor element is arranged and bonded on the base metal plate, the semiconductor element is bonded by a soft brazing material having a melting point of less than 450 ° C., and the other melting point is 450. ℃
A semiconductor device characterized by being joined with the above hard brazing material. 3. A plurality of heat-resistant insulating plates are arranged and joined on a metal supporting plate, and an intermediate metal plate having an area smaller than that of the heat-resistant insulating plate is arranged and joined on the heat-resistant insulating plate. In a semiconductor device in which a base metal plate is arranged and bonded on a plate, and a semiconductor element is arranged and bonded on the base metal plate, the joint between the heat resistant insulating plate and the metal support plate is bonded by a brazing filler metal having a melting point of 450 ° C. or higher. A semiconductor device characterized by the above. 4. The semiconductor device according to claim 1, wherein the brazing filler metal having a melting point of 450 ° C. or higher is Cu, Ag, Z.
A semiconductor device comprising two or more components selected from the group consisting of n, Sn, P, Au, Ni, Cd, and Ti. 5. The semiconductor device according to claim 1, wherein the soft brazing filler metal having a melting point of less than 450 ° C. is Sn, Pb, S.
A semiconductor device comprising two or more kinds of components selected from the group consisting of b, Ag, In, Bi, Cd, Cu, Au and P. 6. The semiconductor device according to claim 1, wherein the joining portion is made of a hard brazing material having a melting point of 450 ° C. or more, and further hard brazing materials having different melting points are used. A semiconductor device characterized by bonding. 7. The semiconductor device according to claim 1, wherein a relay terminal of a metal conductor is arranged and bonded on the metal supporting plate and the heat resistant insulator by using an adhesive. Semiconductor device.