JPH07274069A - Picture input device - Google Patents

Abstract

PURPOSE:To provide a picture input device capable of performing a window processing in complete real time with simple constitution. CONSTITUTION:This picture input device is constituted of picture element groups 1-11-1-54 composed by arraying picture elements composed of CMD in a matrix, a vertical shift register 2 for controlling vertical selection lines 9-1-9-5 connected to the picture element groups arrayed in a row direction in common horizontal selection switches 3-1-3-46 for selecting the vertical selection lines 10-1-10-8 connected to the picture element groups arrayed in a columnar direction in common, a horizontal shift register 4, OR circuits 5-1-5-4 and changeover switches 6-11-6-43 for controlling the horizontal selection switches, output signal lines 11-1-11-3 connected through the horizontal selection switches to vertical signal lines, multipliers 7-1-7-3 for multiplying a coefficient with the picture element output of the output signal lines and an adder 8 for adding the output of the multipliers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device capable of performing window processing.

[0002]

2. Description of the Related Art (Prior art corresponding to claims 1 to 12)
In general, an image captured by an image input device is often converted into an electric signal and given to an external device by being one-dimensionally scanned and subjected to signal conversion such as image processing. For example, when noise removal or image enhancement of an input image signal is performed, convolution calculation is performed in a two-dimensional local area (window).

Now, assuming that an image composed of M × N pixels is picked up by the solid-state image pickup device, if the 3 × 3 convolution operation is applied to the image, the density value X (i , J) is subjected to a product-sum calculation process as shown in the following equation (1) to obtain an output Y (i, j). Y (i, j) = ΣWpq · X (i + p-2, j + q-2) (1) p, q = 1,2,3 (i = 1,2, ..., M; j = 1, 2, ..., N) where Wpq is a weighting coefficient. For example, in the case of noise removal, a value as shown in FIG. 30 and in the case of image enhancement as shown in FIG. The value is taken. In addition, this load factor is often rotationally symmetrical with respect to the center.

On the other hand, as a conventional method of performing such window processing, there is a method of using a structure as shown in FIG. That is, in this conventional example,
One-dimensional data obtained from the image input device 101 is converted into two delay lines 102-a and 102-b for one line,
The window processing is performed by supplying the 3 × 3 window processing circuit formed by the 3 × 3 delay elements 103a to 103i and performing the sum-of-products operation represented by the equation (1). However, this method requires two delay lines for one row, and thus has a problem that the configuration becomes complicated.

In order to solve such a problem, in Japanese Patent Laid-Open No. 57-95768, a non-destructive read-out image input device is used to simultaneously determine the density values of three vertical pixels. Those which are designed to be read out have been proposed. This has a structure as shown in FIG. 33. In this structure, the horizontal selection signal output from the horizontal scanning circuit 200 is supplied via the horizontal selection lines W1 to Wn.
The pixel cells P11 to Pmn capable of non-destructive reading are input to the control terminals to sequentially select each pixel cell in the horizontal direction. The erase signal is the erase signal generation circuit 20.
Each pixel cell continues to accumulate the signal charge until it is input to each pixel from 2 through the erase signal lines c1 to cm. The signal current corresponding to the signal charge accumulated in each pixel cell is, for example, in the first row of the pixel cell group, through the signal line b1 through any of the switches SW11, SW12, and SW13, and the signal line L1. , L2, L3. The same thing can be said for other lines. The timing of turning on and off each switch is shown in the timing chart of FIG. T is a scanning period for one row. In this way, three consecutive pixels in the vertical direction can be simultaneously selected. Then, the signals of the respective pixels selected in this way are transmitted to the signal processing unit 2
In 03, the delay elements 212 and 213, the multipliers 206 to 211, and the adders 204 and 205 are configured to perform window processing. Thus, in this method, window processing can be performed without using a delay line.

However, the above-mentioned Japanese Patent Laid-Open No. 57-9576.
In the image input device disclosed in Japanese Patent Publication No.
The two delay lines for one row as in the conventional example shown in FIG. 1 are not necessary, but instead, the pixel scanning in the horizontal direction is read from the pixel cell by the basic clock and is synchronized with the basic clock by the data selector. Since the signals are switched by using the above-mentioned method, it is necessary to increase the switching characteristics of the pixel cells, and the data selector requires a special circuit for sending data to the three signal lines. However, there is a problem that it is difficult to reduce and reduce the price.

As an attempt to solve such a problem, Japanese Patent Laid-Open No. 62-16685 discloses a method shown in FIG.
An image input device having a configuration as shown in (A) is proposed. Note that FIG. 35B is an internal configuration diagram of the image processing unit 301 in FIG. In this proposal, non-destructive readable pixels P11 to Pmn are arranged in a matrix to form a pixel cell 302, and a plurality of vertical signal lines are provided between the respective pixel columns, and these vertical signal lines are connected to the vertical signal lines. The output lines of the respective pixels are connected so as to have a predetermined relationship, and a plurality of consecutive pixels in the vertical direction are simultaneously read out so that window processing can be performed. Therefore, this structure is disclosed in JP-A-57-95.
Performing desired window processing with a relatively simple configuration without increasing the switching characteristics of pixel cells or requiring a special circuit for distributing data, as disclosed in Japanese Patent Publication No. 768-768. You can

(Prior Art Corresponding to Claim 13)
Japanese Patent Application Laid-Open No. Hei 4-
Japanese Patent No. 21281 proposes a structure shown in FIG. In FIG. 36, 401 is a horizontal scanning circuit, 4
02 is a vertical signal line, 403 is a reference line, 40
Reference numeral 4 is a read signal line. Generally, before reading the signal current, it is necessary to connect the vertical signal line to the reference line of the reference potential to perform the reset. If this operation is performed on all vertical signal lines at the same time,
When strong light is incident, an excess current flows in the reference line at the same time, and the reference potential rises, causing lateral smear. Therefore, in the proposal of the above publication, the connection of the vertical signal line to the reference line is configured such that one vertical signal line precedes the reading period by one bit or less than the number of horizontal pixels. There is. This makes it possible to prevent the signal currents from the vertical signal lines from flowing to the reference potential at the same time, and suppress the horizontal smear.

[0009]

However, as shown in FIG.
In the image input device disclosed in Japanese Patent Application Laid-Open No. 62-16685 shown in (A) and (B), the signal processing unit is complicated, and a delay element is required, so that it is not completely real time. Remains a problem. In particular, when the convolution processing circuit is provided on the same chip as the image sensor, it is necessary to form an A / D converter or a digital memory element or an analog memory element for forming the delay element, which is a semiconductor process or a semiconductor device. The drawback is that the design becomes complicated.

Further, Japanese Patent Laid-Open No. 4-2128 shown in FIG.
The lateral smear prevention mechanism disclosed in Japanese Patent No. 1
When applied to the above-mentioned conventional technique, there is a drawback that the circuit configuration becomes complicated and large in any case.

The present invention has been made to solve the above problems in the conventional image input apparatus, and is an image input apparatus having a simple and inexpensive structure and capable of performing window processing in perfect real time. The purpose is to provide.

The purpose of each invention described in each claim is as follows. That is, an object of each of the first and second aspects of the present invention is to provide an image input device having a simple and inexpensive structure and capable of performing window processing in perfect real time.

The object of the invention described in claim 3 is generated at the time of switching of the switch by performing the control of the horizontal selection switch necessary for achieving the object of the invention described in claim 2 within the horizontal blanking period. To reduce or eliminate the effect of switching noise on the video signal.

An object of each of the inventions of claims 4 and 5 is simple and inexpensive when the weighting factor to be multiplied on each pixel signal is vertically symmetrical with respect to the center on the window when performing the window processing. An object of the present invention is to provide an image input device configured to perform window processing in full real time.

The objects of the inventions described in claims 6, 7 and 8 are:
When the window processing is performed, when the weighting factor to be multiplied on each pixel signal is symmetrical with respect to the center on the window, the window processing can be performed in a simple and inexpensive structure and in complete real time. To provide the image input device.

It is an object of each of the inventions of claims 9, 10, 11 and 12 that, when the window processing is performed, when the weighting factor to be multiplied to each pixel signal is rotationally symmetric with respect to the center on the window, An object of the present invention is to provide an image input device having a simple and inexpensive structure and capable of performing window processing in complete real time.

The object of the invention as defined in claim 13 is to claim 1.
In the image input device according to the invention described in 2, the horizontal smear is prevented.

[0018]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a photoelectric conversion element capable of nondestructive readout while holding charges generated by light irradiation. A pixel portion which has pixels and is arranged in a matrix, a horizontal scanning circuit and a vertical scanning circuit including the horizontal selection switch for selecting the pixel, and an arbitrary pixel selected by the horizontal scanning circuit and the vertical scanning circuit. A means for simultaneously reading in parallel the signal of the pixel and signals of at least two or more pixels different from the central pixel located in a small area centered on the pixel, and simultaneously reading in parallel An image input device having means for performing window processing by using all of the read signals, and a relative positional relationship between a central pixel in the small area and all the pixels read simultaneously, Each pixel and the output signal line are connected so that a plurality of output signal lines for reading out all the pixels simultaneously in parallel always have the same correspondence relationship, and the same weighting factor is multiplied in the window processing means. The signals of the selected pixels are output to the same output signal line.

In the image input device having such a configuration, when signals of a plurality of pixels in a selected small area in the pixel portion formed by arranging pixels in a matrix are simultaneously read and further window processing is performed, Pixel signals with the same weighting factor multiplied by the pixel signals in the small area can be output to the same output signal line, and window processing can be performed in a simple configuration and in perfect real time. it can.

Each of the inventions described in claims 2 to 13 has the structure described in each claim, and the operation thereof is as follows. That is, according to the second aspect of the invention, similar to the first aspect of the invention, it is possible to perform the window processing in a completely real-time with a simple and inexpensive configuration. According to the third aspect of the present invention, by controlling the horizontal selection switch within the horizontal blanking period, it is possible to reduce or eliminate the influence of the switching noise generated when the switch is switched on the video signal. In the inventions according to claims 4 and 5, when performing window processing,
When the weighting factors to be applied to the pixels in the selected small area are vertically symmetrical with respect to the center of the window, the signals of the pixels with the same weighting factor are all output to the same output signal line. In addition, window processing can be performed in real time.

Further, in each of the inventions described in claims 6, 7 and 8,
When the window processing is performed and the weighting factors to be applied to the pixels in the selected small area are symmetrical with respect to the center of the window, the signals of the pixels with the same weighting factor are all the same output signal line. The window processing can be performed in real time with a simple configuration.
In each of the ninth, tenth, eleventh and twelfth aspects of the present invention, when the window processing is performed, when the load coefficient to be applied to the pixels in the selected small area is rotationally symmetric with respect to the center on the window, the load coefficient is obtained. Signals of pixels having the same value are all output to the same output signal line, and window processing can be performed with a simple configuration and in perfect real time. According to a thirteenth aspect of the present invention, in the image input device in which the horizontal scanning circuits are provided above and below the pixel portion, either one of the two upper and lower read signal lines connected to the vertical signal line is alternately connected to the reference line. By connecting the vertical signal line to the reference potential via the reference line before the vertical signal line is connected to the output signal line for reading the pixel signal, resetting and horizontal smear prevention function can be provided. .

[0022]

EXAMPLES The following is a description of examples of the present invention. Prior to that, the concept of the present invention will be described. An image input device according to the present invention is an image input device for performing window processing, which can simultaneously read signals of a plurality of pixels in a selected small area in parallel, and Output each pixel so that the relative positional relationship with all pixels read at the same time as the central pixel and the plurality of output signal lines for reading the selected plurality of pixels always have the same correspondence relationship. Signals of pixels which are connected to the signal line and which are multiplied by the same weighting factor in the window processing are connected to the same output signal line.

This structure will be described in detail with reference to FIGS. For example, the weighting factor for image enhancement is shown in FIG.
It is represented by the matrix shown in. 2A to 2I show modes in the case of performing image enhancement on the image signal of the solid-state imaging device including 5 × 5 pixels by using the weight matrix shown in FIG. . At this time, the pixels to be read out simultaneously are the central pixel and the left, right, upper and lower four pixels of the central pixel. There are two types of weighting factors, the central pixel and its vicinity. Here, the signal of the pixel on the i-th row and the j-th column is Qij
Then, for example, at time T1, as shown in FIG. 2A, the signal of the center selection pixel is Q22, and the signal Q22 is output to the output signal line A. In addition, Q12, Q21, Q23, and Q32 in the vicinity are all added and output signal line B
Is output to. Hereinafter, also at times T2 to T9, FIG.
Similar relationships are established as shown in (B) to (I). Here, focusing on, for example, the signal Q33 of the pixel of 3 rows and 3 columns, reading is performed at time T2, time T4, time T5, time T6, and time T8. That is, non-destructive readout of pixels is an essential element in the present invention. Furthermore, since the signals are added by reading the signals of a plurality of pixels to the same output signal line at the same time, it is convenient that the pixels can perform current reading.
Therefore, as a pixel, a photoelectric conversion element capable of non-destructive reading such as CMD and capable of reading current is effective. The read signal is processed by the signal processing unit shown in FIG. In this configuration example, the signal of the pixel output to the output signal line A is multiplied by the coefficient 5 by the multiplier C, and the signal of the pixel output to the output signal line B is multiplied by the coefficient (-1) by the multiplier D. Is loaded. Then, these signals are added by the adder E and output to the output terminal F as a video signal with image enhancement.

When the load coefficient is rotationally symmetric with respect to the center, the above object can be achieved by arranging the means for maintaining vertical symmetry and the means for maintaining left-right symmetry at the same time.

First, the case where the load coefficients are symmetrical will be described. A configuration example used in that case is shown in FIG.
In this configuration example, the horizontal shift register and the OR circuit play a role of controlling the horizontal selection switch so that the signals of the pixels to which the same weighting factor is multiplied can be output to the same output signal line in addition to the horizontal scanning of the pixels. It is supposed to be fulfilled. In this configuration example, in order to simplify the explanation, as shown in FIG. 4, pixels are arranged in one dimension in the horizontal direction. That is, in this configuration example, the pixels 1 (n-1) to 1 (n + 1) composed of nondestructive readable photoelectric conversion elements,
Horizontal selection switches 3-11 to 3-32 for selecting the signals read out in the horizontal direction, a horizontal shift register 4 for controlling the horizontal selection switches, and OR circuits 5 (n-1) to 5 (n +).
It is composed of 1). Then, in this configuration example, the signals of three pixels are read out at the same time, and the output A of the output signal line 11-1 is output.
The signal of the central pixel on the window is always output to the output B of the output signal line 11-2, and the signal of the pixel located symmetrically with respect to the central pixel is always output. This aspect is shown in FIG.

Next, the operation will be described based on the timing chart shown in FIG. From the horizontal shift register 4 ...
.PHI. (N-1), .PHI.n, .PHI. (N + 1) ... Pulses are sequentially output. Then, the OR circuits 5 (n-1) to 5
(N + 1) synthesizes these pulses and ... Ψ (n-
1), Ψn, Ψ (n + 1) ... Pulses are output.
Here, at the timing of Tn, Φn, Ψ (n−
Since 1) and Ψ (n + 1) are at high level, the horizontal selection switches 3-22, 3-11, and 3-31 are turned on. At this time, the signal of the pixel 1n is output as the output A to the output signal line 11-1 via the horizontal selection switch 3-22, and the pixel 1 (n-1) and the pixel 1 (n + 1) are respectively output from the horizontal selection switch 3-1. Output signal line 1 via -11 and 3-31
The output B is output to 1-2. Hereinafter, T (n-
1), T (n + 1), etc.
The above relationship holds. Therefore, the signals of the pixels located symmetrically with respect to the center selection pixel on the window are always output to the output signal line 11-2, and the signals of the center selection pixel are always output to the output signal line 11-1. . The horizontal scanning circuit unit having the horizontal shift register and the OR circuit is
Any structure can be used as long as it can output the pulses shown in the timing chart of FIG.

Next, the case where the load coefficients are vertically symmetrical will be described. At this time, the control signal ΦH1 plays a role of controlling the horizontal selection switch so that the signals of pixels having the same weighting factor are output to the same output signal line when the weighting factor on the window is vertically symmetrical. As an example of a configuration for performing such an operation, a configuration in which pixels are arranged one-dimensionally in the vertical direction as shown in FIG. 7 will be described. In this configuration example, the pixel 1 (n-
2) to 1 (n + 1), two vertical signal lines 10-1 and 10-2 connected to every other pixel, and a horizontal selection switch 3
-11 to 3-22, a vertical shift register 2 for reading in the vertical direction, and an inverter INV. The vertical shift register 2 is configured so that three pixels can be simultaneously selected and read out at the same time. Then, among the selected pixels, the output signal line 11-1
At the output A of, the signal of the center pixel on the window is
The signal of the pixel located vertically symmetrical with respect to the central pixel is always output to the output B of the output signal line 11-2.

The above operation mode is shown in FIG. Further, a timing chart of the control signals ΦH1 and / ΦH1 (negative logic of ΦH1) is shown in FIG. At timing T (n-1), pixels 1 (n-2) to 1n are selected. At this time, since / ΦH1 is at the high level, the horizontal selection switches 3-11 and 3-22 are turned on.
To the output signal line 11-2 via the pixel 11 (n-1)
Signal is output to the output signal line 11-1 via the horizontal selection switch 3-22. Subsequently, at the timing of Tn, the pixels 1 (n-1) to 1 (n + 1) are selected. At this time, since ΦH1 is at the high level, the horizontal selection switches 3-12 and 3-21 are turned on, and the pixel 1
The signals of (n-1) and pixel 1 (n + 1) are output to the output signal line 11-2 through the horizontal selection switch 3-12 and are output to the pixel 1n.
Signal is output to the output signal line 11-1 via the horizontal selection switch 3-21. The above relationship is established at any of the following timings. Therefore, the signals of the pixels vertically symmetrical with respect to the center selection pixel on the window are always output to the output signal line 11-2, and the signals of the center selection pixel are always output to the output signal line 11-1. There is.

Then, the combination of vertical symmetry and left-right symmetry results in rotational symmetry. In the present invention, the rotational symmetry can be maintained by configuring the means for maintaining the left-right symmetry and the means for maintaining the vertical symmetry at the same time. The above is a conceptual description of the present invention.

(First Embodiment) Next, a specific embodiment will be described. FIG. 10 is a circuit configuration diagram showing a first embodiment of the image input apparatus according to the present invention. For simplification of description, the number of pixels is 5 × 4, and the configuration is shown so that 3 × 3 window processing can be performed. The weighting factor is configured to be rotationally symmetrical with respect to the central pixel. That is, specifically, as shown in FIG. 11, pixels A, B, which correspond to the center, upper, lower, left, right, and four corners on the window,
The C pixel signal is configured to be multiplied by different weighting factors.

The image input apparatus according to this embodiment includes pixel groups 1-11 to 1-1-which are composed of photoelectric conversion elements capable of non-destructive reading.
54, a vertical shift register 2 for controlling reading in the vertical direction, horizontal selection switches 3-11 to 3-46 for selecting signals read in the horizontal direction, a horizontal shift register 4 for controlling the horizontal selection switch, and an OR circuit 5. -1 to 5-4 and changeover switches 6-11 to 6-43, multipliers 7-1 to 7-3 for multiplying a pixel output by a coefficient, and an adder 8 for adding outputs of the multipliers. In this embodiment, CMD is used as the photoelectric conversion element.

The OR circuits 5-1 to 5-4 receive the output from the horizontal shift register 4 and receive the changeover switch 6
-11 to 6-43 are horizontal shift register 4 and OR circuit 5
The outputs from -1 to 5-4 and the control signal ΦH1 are received and connected to the control terminals of the horizontal selection switches 3-11 to 3-46. The control terminals of the pixels are vertical selection lines 9-1 to 9-5.
Thus, each row is connected to the vertical shift register 2. The output terminals of the pixels 1-11, 1-31, 1-51 are connected to the vertical signal line 10-1, and the horizontal selection switch 3-1.
Pixels 1-2 are connected to output signal lines 11-1, 11-2, 11-3 via 1, 3-13, 3-15, respectively.
The output terminals of 1, 1-41 are connected to the vertical signal line 10-2, and output signal lines 11-1, 11-2, 11 via the horizontal selection switches 3-12, 3-14, 3-16, respectively.
-3 is connected. Pixels 1-12, 1-32, 1-
The output terminal of 52 is connected to the vertical signal line 10-3, and through the horizontal selection switches 3-21, 3-23, 3-25,
The output signal lines 11-1, 11-2 and 11-3 are respectively connected, the output terminals of the pixels 1-22 and 1-42 are connected to the vertical signal line 10-4, and the horizontal selection switches 3-22 and 3 are connected.
-24, 3-26 and output signal lines 11-
1, 11-2, 11-3 are connected. Pixel 1-1
The output terminals of 3, 1-33 and 1-53 are vertical signal lines 10-
5, the horizontal selection switches 3-31, 3-33,
Output signal lines 11-1 and 11 via 3-35, respectively.
-2, 11-3, the output terminals of the pixels 1-23, 1-43 are connected to the vertical signal line 10-6, and through the horizontal selection switches 3-32, 3-34, 3-36, The output signal lines 11-1, 11-2, and 11-3 are respectively connected. The output terminals of the pixels 1-14, 1-34, 1-54 are connected to the vertical signal line 10-7, and the horizontal selection switch 3
-41, 3-43, 3-45 are connected to the output signal lines 11-1, 11-2, 11-3, respectively, and the pixel 1
The output terminals of -24, 1-44 are connected to the vertical signal line 10-8, and horizontal selection switches 3-42, 3-44, 3-4.
6 through output signal lines 11-1, 11-2,
11-3 is connected. In this way, the output terminals of the pixels in each column are alternately connected to the two vertical signal lines.
The output signal lines 11-1 to 11-3 are connected to the multipliers 7-1 to 7-3, respectively, and the output terminals of the multipliers 7-1 to 7-3 are connected to the adder 8. In FIG. 10, 12-1 to 12-6 are output lines of the horizontal shift register 4, and 12-7 to 12-10 are OR circuits 5-1 to 5-.
4 output lines, 13-1 are changeover switches 6-11 to 6
-43 control line, 13-2 GND line, 14 adder 8
The output terminal of is shown.

Next, changeover switches 6-11 to 6-4
The configuration of No. 3 will be described. These changeover switches are switches for simultaneously realizing the above-mentioned means for maintaining the vertical symmetry and the means for maintaining the left-right symmetry. As long as it has two input terminals and two output terminals and the connection between the input and output terminals can be changed by a control signal input from the outside, as an example, (A) to FIG.
The structure shown in (C) is given. This configuration example includes input terminals a and b, output terminals c and d, a control terminal e, and analog switches 31 to 34. Control terminal e
When a high-level pulse is input to the input terminal a and the output terminal c and the input terminal b and the output terminal d are connected, respectively, when a low-level pulse is input, the input terminal a, the output terminal d and the input terminal d are input. The terminal b and the output terminal c are connected to each other.

Next, the operation of the first embodiment configured as described above will be described with reference to FIGS.
It will be described based on the timing charts shown in FIGS. In the timing chart, T0 to T8 are the first
Horizontal scanning period, T8 to T16 are second horizontal scanning periods,
T16 to T24 correspond to the third horizontal scanning period. When the vertical selection signals Φg1 to Φg5 are at the read level, the signal current corresponding to the charge accumulated in the pixel is ready to be read, and the signal can be read repeatedly as many times as long as the reset level is not applied. Is possible. When the read level and the reset level are not applied, the storage level is always set, and the photo-generated charges are stored in the storage section in each pixel. In this state, the pixel is off, No signal current flows.

Next, the signals output at each timing will be described with reference to the six types of window processing modes that can be performed within one frame period shown in FIGS. 17A to 17F. Note that in FIGS. 17A to 17F, the circle marks indicate the center selection pixel, and the hatched pixels indicate the pixel region selected for the window processing. First,
Times T3 to T4 will be described. This corresponds to the window processing state shown in FIG. Time T3
From ~ T4, the vertical selection signals Φg1, Φg2, Φg3 are at the read level, and the first to third rows of the pixel group are in the read state. At this time, Φa1, Φd1, Φc2,
Since Φf2, Φa3, and Φd3 are at the high level, the horizontal selection switches 3-11, 3-14, 3-23, 3-2
6, 3-31 and 3-34 are on. Therefore,
The output signal line 11-1 includes horizontal selection switches 3-11 and 3
Through −31, pixels 1-11, 1-31, 1-13,
The signal current of 1-33 is output. This is the signal of the pixel corresponding to C in FIG. 11 on the window. Also,
The output signal line 11-2 has horizontal selection switches 3-14 and 3
-23, 3-34 through pixels 1-21, 1-12,
The signal currents 1-32 and 1-23 are output. this is,
On the window, it is the signal of the pixel corresponding to B in FIG. Finally, the signal current of the photoelectric conversion element 1-22 is output to the output signal line 11-3 via the horizontal selection switch 3-26. This is the signal of the pixel corresponding to A in FIG. 11 on the window. A corresponds to the center selected pixel on the window and is indicated by a circle in FIG.

Next, the signals output at the timings T4 to T5 will be described. This corresponds to the window processing state shown in FIG. Time T4
At to T5, the vertical selection signals Φg1, Φg2, and Φg3 are at the read level, and the first to third rows of the pixel group are in the read state. At this time, Φa2, Φd2, Φc
3, Φf3, Φa4, Φd4 are High level,
Horizontal selection switches 3-21, 3-24, 3-33, 3-
36, 3-41, 3-44 are on. Therefore, the horizontal selection switch 3-2 is connected to the output signal line 11-1.
Pixels 1-12, 1-32, 1-
The signal currents of 14 and 1-34 are output. This is the signal of the pixel corresponding to C in FIG. 11 on the window.
The output signal line 11-2 has a horizontal selection switch 3-2.
Pixels 1-22,1-via 4,3-33,3-44
The signal currents 13, 1-33, 1-24 are output. This is the signal of the pixel corresponding to B in FIG. 11 on the window. Finally, the signal current of the photoelectric conversion element 1-23 is output to the output signal line 11-3 via the horizontal selection switch 3-36. This is shown in Figure 11 on the window.
It is the signal of the pixel corresponding to A. A corresponds to the center selected pixel on the window and is indicated by a circle in FIG. 17B.

Hereinafter, T11 to T12, T12 to T13,
The same relationship is established at any time of T19 to T20 and T20 to T21. This is shown in FIG.
(C), (D), (E), and (F) of FIG. In this way, the signals of the pixels positioned rotationally symmetrically with respect to the center selection pixel on the window at any timing are output to the same output signal line.

Then, the signal current output to the output signal line 11-1 is input to the multiplier 7-1 and is multiplied by γ there. Similarly, the signal current output to the output signal line 11-2 is input to the multiplier 7-2 and is multiplied by β there. Similarly, the signal current output to the output signal line 11-3 is input to the multiplier 7-3 and is multiplied by α there. And adder 8
Then, the signal currents output from the multipliers 7-1 to 7-3 are all added and output to the output terminal 14. In this way, the video signal is output while being multiplied by the weighting factor depending on the predetermined position on the window.

Since the switching timing of the control signal ΦH1 is during the horizontal retrace line period, the switching noise generated when the switch is switched is not mixed in the video signal.

At times T1 to T2, Φa1,
Horizontal selection switches 3-11 and 3 because Φd1 is at high level
-14 is on. At this time, the vertical selection signal Φg1,
Since Φg2 and Φg3 are at high level, the first to third rows of the pixel group
A row is selected, and the signal currents of the pixels 1-11 and 1-31 are output via the horizontal selection switch 3-11.
-1, and the signal current of the pixel 1-21 is output to the output signal line 11-2 via the horizontal selection switch 3-14. As described above, since only the signal currents of the three pixels are output at the same time, the window processing described above cannot be performed. Further, at times T2 to T3, only signals of 6 pixels are output at the same time, and similarly window processing cannot be performed. Other than this, the times T5 to T
7, T9 to T11, T13 to T15, T17 to T19,
It occurs in the period of T21 to T23. However, in actual use, there is no problem because any of such periods can be cut as an extension of the horizontal blanking period.

As described above, in this embodiment, window processing can be performed in real time without using any delay element or delay line. Further, the signal processing unit does not have a complicated structure as shown in Japanese Patent Laid-Open No. 62-16685, and it can be relatively easily manufactured on-chip or off-chip.

(Second Embodiment) Next, a second embodiment will be described. FIG. 18 shows a second image input device according to the present invention.
It is a circuit block diagram which shows an Example. The same or corresponding members as those in the first embodiment shown in FIG. 10 are designated by the same reference numerals. Also in this embodiment, the number of pixels is 5 × 4.
Thus, it is configured so that 3 × 3 window processing can be performed. Then, as in the first embodiment, the weighting factor is configured to be rotationally symmetrical with respect to the central pixel. That is, specifically, as shown in FIG. 19, the pixel signals of the pixels A, B, C, and D corresponding to the center, top, bottom, left, and right corners on the window are respectively multiplied by different weighting factors. There is. There are six types of window processing that can be performed within one frame period, as shown in (A) to (F) of FIG.

The image input apparatus of this embodiment selects nondestructive read-out pixel groups 1-11 to 1-54, a vertical shift register 2 for controlling vertical read-out, and a signal read out in the horizontal direction. Horizontal selection switches a1 to p4, a horizontal shift register 4 for controlling the horizontal selection switches, and OR
It is composed of circuits 5-1 to 5-4 and an inverter 16, multipliers 7-1 to 7-4 for multiplying a pixel output by a coefficient, and an adder 8 for adding outputs of the multipliers. Note that FIG.
17-1 is a control signal line of the horizontal selection switch to which the control signal ΦH1 for switching to one horizontal scanning period is applied, and 17-2 is a control signal line for applying the control signal ΦH1 via the inverter 16.

The OR circuits 5-1 to 5-4 receive the output from the horizontal shift register 4 and receive the horizontal selection switch j.
It is connected to the control terminals of 1 to j4, 11 to 14, p1 to p4. In addition, the horizontal selection switch b1
The control terminals of b4, d1 to d4, f1 to f4 and h1 to h4 are directly connected to the horizontal shift register 2. Further, the horizontal selection switches a1 to a4, c1 to c4, e1.
e4, g1 to g4, i1 to i4, k1 to k4, m1 to m
4, o1 to o4 are controlled by the control signal ΦH1. The control terminals of the pixels are vertical selection lines 9-1 to 9-5.
Thus, each row is connected to the vertical shift register 2. The output terminals of the pixels 1-11, 1-31, 1-51 are connected to the vertical signal line 10-1, and are connected via the horizontal selection switches a1 and b1, e1 and f1, i1 and j1, m1 and n1.
Output signal lines 11-1, 11-2, 11-3, 1 respectively
1-4, the output terminals of the pixels 1-21 and 1-41 are connected to the vertical signal line 10-2, and the horizontal selection switch c
1 and d1, g1 and h1, k1 and l1, o1 and p1 through output signal lines 11-1, 11-2 and 11-, respectively.
3, 11-4. Pixels 1-12, 1-3
The output terminals of 2, 1-52 are connected to the vertical signal line 10-3, and output signal lines 11- via the horizontal selection switches a2 and b2, e2 and f2, i2 and j2, m2 and n2, respectively.
1, 11-2, 11-3, 11-4, and the output terminals of the pixels 1-22, 1-42 are vertical signal lines 10-4.
, Horizontal selection switches c2 and d2, g2 and h
The output signal lines 11-1, 11-2, 11-3, and 11-4 are connected via 2, k2 and l2, o2, and p2, respectively. The output terminals of the pixels 1-13, 1-33, 1-53 are connected to the vertical signal line 10-5 and output via the horizontal selection switches a3 and b3, e3 and f3, i3 and j3, m3 and n3, respectively. Signal lines 11-1, 11-2, 11-
3, 11-4, the output terminals of the pixels 1-23, 1-43 are connected to the vertical signal line 10-6, and horizontal selection switches c3 and d3, g3 and h3, k3 and l3, o3 and p3.
Via the output signal lines 11-1, 11-2, 1
It is connected to 1-3 and 11-4. Pixels 1-14, 1
The output terminals of -34, 1-54 are connected to the vertical signal line 10-7, and horizontal selection switches a4 and b4, e4 and f4, i.
4 and j4, m4 and n4 through output signal line 1
The output terminals of the pixels 1-24, 1-44 are connected to the vertical signal lines 10-8.
, Horizontal selection switches c4 and d4, g4 and h
4, k4 and l4, o4 and p4 are connected to the output signal lines 11-1, 11-2, 11-3 and 11-4, respectively. In this way, the output terminals of the pixels in each column are alternately connected to the two vertical signal lines. The output signal lines 11-1 to 11-4 are respectively connected to the multipliers 7-1 to 7-4.
The output terminals of the multipliers 7-1 to 7-4 are connected to the adder 8.

The second embodiment is different from the first embodiment in that the first embodiment controls the horizontal selection switch 3 by the changeover switch 6 as shown in FIG. 20B. On the other hand, in the second embodiment, as shown in FIG. 20A, the horizontal selection switch 3 has a two-stage configuration in series,
One of the switches 3 is controlled by a horizontal scanning circuit having an OR circuit, and the other horizontal selection switch is controlled by a control signal ΦH1 for switching to one horizontal scanning period, so that window processing can be performed similarly to the first embodiment. It is the point that is configured.

The second embodiment is configured as described above, and is the same as the first embodiment in that a specific pixel on the window is always multiplied by the same weighting factor and output. However, unlike the first embodiment, the types of pixels to which the same weighting factor is applied on the window are four types A, B, C and D as shown in FIG. As a result, a variety of image processes can be performed as compared with the first embodiment.

Next, the operation of the image input apparatus of the second embodiment having the above-mentioned structure will be described with reference to the timing chart shown in FIG. In this timing chart, time T0 to T8 is the first horizontal scanning period, and T8 to T8.
16 corresponds to the second horizontal scanning period, and T16 to T24 correspond to the third horizontal scanning period. When the vertical selection signals Φg1 to Φg5 are at the read level, the signal current corresponding to the charge stored in the pixel is ready to be read, and at the reset level, the stored charge is reset and the pixel is Return to the initial state. As long as this reset level is not applied, the signal can be read out any number of times. When the read level and the reset level are not applied, the storage level is always set, and the photo-generated charges are stored in the storage section in each pixel. In this state, the pixel is off, No signal current flows.

First, the signals output from time T3 to T4 will be described. This corresponds to the window processing state shown in FIG. At times T3 to T4, the vertical selection signals Φg1, Φg2, and Φg3 are at the read level, and the first to third rows of the pixel group are in the read state. At this time, since the control signal ΦH1 is at the high level, the horizontal selection switches o1 to o4, i1 to i4, g1 to g4 whose control terminals are connected to the control signal line 17-1 are connected.
a1 to a4 are on. And Φs3, Φ11, Φ13
Is high level, the horizontal selection switches b2, d2, f
2, h2 and j1, l1, n1, p1 and j3, l3
n3 and p3 are on. Therefore, the output signal line 1
The signal currents of the pixels 1-11 and 1-31 are supplied to 1-3 through the horizontal selection switches j1 and i1, and the signal currents of the pixels 1-13 and 1-33 are supplied through the horizontal selection switches j3 and i3. Is output. This is D in Figure 19 on the window
It is the signal of the corresponding pixel.

Further, the signal current of the pixel 1-21 is supplied to the output signal line 11-4 via the horizontal selection switches p1 and o1, and the signal current of the pixel 1-21 is supplied via the horizontal selection switches p3 and o3 to the pixel 1-.
The signal current of 23 is output. This is the signal of the pixel corresponding to C in FIG. 19 on the window. Further, the signal currents of the pixels 1-12 and 1-32 are output to the output signal line 11-1 via the horizontal selection switches a2 and b2.
This is the signal of the pixel corresponding to B in FIG. 19 on the window. In addition, the signal current of the pixel 1-23 is output to the output signal line 11-2 via the horizontal selection switches h2 and g2. This is the signal of the pixel corresponding to A in FIG. 19 on the window. A corresponds to the center selection pixel on the window.

Next, the signals output from time T4 to T5 will be described. This corresponds to the window processing state shown in FIG. From time T4 to T5, the vertical selection signals Φg1, Φg2, and Φg3 are at the read level, and the first to third rows of the photoelectric conversion element group are in the read state. At this time, since the control signal ΦH1 is at the high level, the horizontal selection switches o1 to o4, i1 to i4, g1 whose control terminals are connected to the control signal line 17-1
~ G4, a1 to a4 are on. And Φs4, Φ
Since 12 and Φ14 are high level, horizontal selection switch b3
d3, f3, h3 and j2, 12, n2, p2 and j
4, 14, n4 and p4 are on. Therefore, the signal currents of the pixels 1-12 and 1-32 are supplied to the output signal line 11-3 via the horizontal selection switches j2 and i2, and the signal currents of the pixels 1-12 and 1-32 are supplied through the horizontal selection switches j4 and i4.
The signal current of 34 is output. This is the signal of the pixel corresponding to D in FIG. 19 on the window.

Further, the signal current of the pixel 1-22 is applied to the output signal line 11-4 via the horizontal selection switches p2 and o2, and the signal current of the pixel 1-22 is applied via the horizontal selection switches p4 and o4 to the pixel 1-.
24 signal currents are output. This is the signal of the pixel corresponding to C in FIG. 19 on the window. Further, the signal currents of the pixels 1-13 and 1-33 are output to the output signal line 11-1 via the horizontal selection switches a3 and b3.
This is the signal of the pixel corresponding to B in FIG. 19 on the window. The signal current of the pixel 1-23 is output to the output signal line 11-2 via the horizontal selection switches h3 and g3. This is the signal of the pixel corresponding to A in FIG. 19 on the window. A corresponds to the center selection pixel on the window.

Hereinafter, T11 to T12, T12 to T13,
The same relationship is established at any time of T19 to T20 and T20 to T21. This is shown in FIG.
(C), (D), (E), and (F) of FIG. In this way, the signals of the pixels positioned rotationally symmetrically with respect to the center selection pixel on the window at any timing are output to the same output signal line.

Then, the signal current output to the output signal line 11-1 is input to the multiplier 7-1 and is multiplied by β there. Similarly, the signal current output to the output signal line 11-2 is input to the multiplier 7-2 and is multiplied by α there. Similarly, the signal current output to the output signal line 11-3 is input to the multiplier 7-3 and is multiplied by δ there. Similarly, the signal current output to the output signal line 11-4 is input to the multiplier 7-4 and is multiplied by γ there. Then, the adder 8 adds all the signal currents output from the multipliers 7-1 to 7-4 and outputs the result to the output terminal 14. In this way, the video signal is output while being multiplied by the weighting factor depending on the predetermined position on the window.

Since the timing of switching the pulse of the control signal ΦH1 is during the horizontal blanking period, noise generated when the pulse is switched is not mixed in the video signal.

At times T1 and T2, the first to third rows of the pixel group are selected because the vertical selection signals Φg1, Φg2 and Φg3 are at the high level. At this time, since Φ11 is at the high level and the control signal ΦH1 is at the high level, the signal currents of the pixels 1-11 and 1-31 are output to the output signal line 11-3 via the horizontal selection switches i1 and j1. Then, the signal current of the pixel 1-21 is output to the output signal line 11-4 via the horizontal selection switches o1 and p1.
As described above, since only the signal currents of the three pixels are output at the same time, the window processing described above cannot be performed. Further, at times T2 to T3, only signals of 6 pixels are output at the same time, and similarly window processing cannot be performed. Other than this, at times T5 to T7,
T9 to T11, T13 to T15, T17 to T19, T2
It occurs in the period of 1 to T23. However, in actual use, there is no problem because any of such periods can be cut as an extension of the horizontal blanking period.

As described above, the present embodiment has the same effect as that of the first embodiment, and, in comparison with the first embodiment, the pixel group 1
The number of MOS transistors required for the horizontal scanning unit per column is very small, and it can be relatively easily manufactured. Further, when the Laplacian processing is performed when the pixel pitches of the upper, lower, left and right sides are different, the weighting factors for the upper, lower, left and right pixels with respect to the center must be set to different values. Such a case cannot be dealt with in the first embodiment, but can be dealt with in the present embodiment.

(Third Embodiment) Next, a third embodiment will be described. FIG. 22 shows a third image input device according to the present invention.
It is a circuit block diagram which shows an Example. The same or corresponding members as those in the first embodiment shown in FIG. 10 are designated by the same reference numerals. Also in this embodiment, in order to simplify the description, the number of pixels is 5 × 4, and 3 × 3 window processing can be performed. The weighting factor is configured to be rotationally symmetrical with respect to the central pixel. That is, specifically, as shown in FIG. 23, the pixel signals of the pixels A, B, C, and D corresponding to the center, top, bottom, left, right, and four corners on the window are respectively multiplied by different weighting factors. There is. Also in this embodiment, 1
The window processing that can be performed within the frame period is shown in FIG.
There are 6 types as shown in (A) to (F) of 7.

The difference between this embodiment and the first embodiment is that the pixels on the left and right and above and below the center selection pixel on the window are
The different weighting factors are applied to the output signal. That is, as shown in FIG. 23, four weighting factors of α, β, γ, and δ are respectively multiplied to the signals of four types of pixels of A, B, C, and D.

The image input apparatus of this embodiment selects nondestructive read-out pixel groups 1-11 to 1-54, a vertical shift register 2 for controlling vertical read-out, and signals read out in the horizontal direction. Horizontal selection switches 3-11 to 3-
48, horizontal shift register 4 for controlling the horizontal selection switch, OR circuits 5-1 to 5-4, and changeover switch 6-
11 to 6-42, multiplier 7 for multiplying the coefficient in the pixel output
-1 to 7-4, and an adder 8 that adds the outputs of the multipliers.

The OR circuits 5-1 to 5-4 receive the output from the horizontal shift register 4, and the changeover switches 6-11 to 6-42 include the horizontal shift register 4 and the OR circuits 5-1 to 5-4. Of the horizontal selection switches 3-11 to 3-48.

The control terminals of the pixels are vertical selection lines 9-1 to 9-.
5, each row is connected to the vertical shift register 2. The output terminals of the pixels 1-11, 1-31, 1-51 are connected to the vertical signal line 10-1, and the horizontal selection switch 3-
Output signal lines 11-1, 11-2, 11-3, 11-4 via 11, 3-13, 3-15, 3-17, respectively.
, The output terminals of the photoelectric conversion elements 1-21 and 1-41 are connected to the vertical signal line 10-2, and through the horizontal selection switches 3-12, 3-14, 3-16, 3-18, Output signal lines 11-1, 11-2, 11-3, 11 respectively
-4 is connected. Pixels 1-12, 1-32, 1-
The output terminal of 52 is connected to the vertical signal line 10-3, and horizontal selection switches 3-21, 3-23, 3-25, 3-27.
Via the output signal lines 11-1, 11-2, 1
1-3, 11-4, and pixels 1-22, 1-
The output terminal of 42 is connected to the vertical signal line 10-4, and horizontal selection switches 3-22, 3-24, 3-26, 3-28.
Via the output signal lines 11-1, 11-2, 1
It is connected to 1-3 and 11-4.

The output terminals of the pixels 1-13, 1-33, 1-53 are connected to the vertical signal line 10-5, and the horizontal selection switches 3-31, 3-33, 3-35, 3-37 are used. ,
Output signal lines 11-1, 11-2, 11-3, 1 respectively
1-4, the output terminals of the pixels 1-23 and 1-43 are connected to the vertical signal line 10-6, and the horizontal selection switches 3-32, 3-34, 3-36, and 3-38. hand,
Output signal lines 11-1, 11-2, 11-3, 1 respectively
It is connected to 1-4. Pixels 1-14, 1-34, 1
The output terminal of -54 is connected to the vertical signal line 10-7, and horizontal selection switches 3-41, 3-43, 3-45, 3-4.
7, output signal lines 11-1, 11-2,
11-3 and 11-4, and pixels 1-24 and 1
The output terminal of -44 is connected to the vertical signal line 10-8, and the horizontal selection switches 3-42, 3-44, 3-46, 3-4.
8 through output signal lines 11-1, 11-2,
It is connected to 11-3 and 11-4. In this way, the output terminals of the pixels in each column are alternately connected to the two vertical signal lines. The output signal lines 11-1 to 11-4 are connected to the multipliers 7-1 to 7-4, respectively, and the multiplier 7-1
7-4 are connected to the adder 8.

Next, the operation of the image input apparatus of the third embodiment constructed as described above will be explained based on the timing charts shown in FIGS. In this timing chart, times T0 to T8 are the first horizontal scanning period, T
8 to T16 correspond to the second horizontal scanning period, and T16 to T24 correspond to the third horizontal scanning period. When the vertical selection signals Φg1 to Φg5 are at the read level, the signal current corresponding to the charges accumulated in the pixel is ready to be read,
At the reset level, the accumulated charge is reset,
The pixel returns to the initial state. As long as this reset level is not applied, the signal can be read out any number of times. When the read level and the reset level are not applied, the storage level is always set, and the photo-generated charges are stored in the storage section in each pixel. In this state, the pixel is off, No signal current flows.

First, the signals output at times T3 to T4 will be described. This corresponds to the window processing state shown in FIG. At times T3 to T4, the vertical selection signals Φg1, Φg2, and Φg3 are at the read level, and the first to third rows of the pixel group are in the read state. At this time, since Φc1, Φa2, and Φc3 are at the high level, the horizontal selection switches 3-11, 3-1
4, 3-25, 3-28, 3-31, 3-34 are on. Therefore, the output signal line 11-1 is connected to the pixels 1-11, 3-11, 3-31 via the horizontal selection switches 3-11, 3-31.
Signal currents 1-31, 1-13, and 1-33 are output. This is the signal of the pixel corresponding to D in FIG. 23 on the window. In addition, the pixel 1-2 is connected to the output signal line 11-2 via the horizontal selection switches 3-14 and 3-34.
Signal currents 1 to 1-23 are output. This is the signal of the pixel corresponding to C in FIG. 23 on the window. The output signal line 11-3 has a horizontal selection switch 3-25.
The signal currents of the pixels 1-12 and 1-32 are output via the. This is the signal of the pixel corresponding to B in FIG. 23 on the window. Finally, the signal current of the pixel 1-22 is output to the output signal line 11-4 via the horizontal selection switch 3-28. This is shown in Figure 23 on the window.
It is the signal of the pixel corresponding to A. A corresponds to the center selected pixel on the window, and corresponds to the circled portion in (A) of FIG.

Next, the signals output at the timings T4 to T5 will be described. This corresponds to the window processing state shown in FIG. Time T4
At ~ T5, the vertical selection signals Φg1, Φg2, Φg3 are at the read level, and the first to third rows of the pixel group are in the read state. At this time, Φc2, Φa3, Φc4,
Is at high level, the horizontal selection switch 3-
21, 3-24, 3-35, 3-38, 3-41, 3-
44 is on. Therefore, the output signal line 11-1
, The signal currents of the pixels 1-12, 1-32, 1-14, 1-34 are output via the horizontal selection switches 3-21, 3-41. This is D in Fig. 23 in the window.
It is the signal of the corresponding pixel. Also, the output signal line 11-2
, The signal currents of the pixels 1-22 and 1-24 are output via the horizontal selection switches 3-24 and 3-44. This is the signal of the pixel corresponding to C in FIG. 23 on the window. The signal currents of the pixels 1-13 and 1-33 are output to the output signal line 11-3 via the horizontal selection switch 3-35. This is the signal of the pixel corresponding to B in FIG. 23 on the window. Finally, the output signal line 11
-4 through the horizontal selection switch 3-38 to the pixel 1-
The signal current of 23 is output. This is the signal of the pixel corresponding to A in FIG. 23 on the window. A corresponds to the center selected pixel on the window, and corresponds to the circled portion in FIG.

Hereinafter, T11 to T12, T12 to T13,
The same relationship is established at any time of T19 to T20 and T20 to T21. This is shown in FIG.
(C), (D), (E), and (F) of FIG. In this way, at any timing, the signals of the pixels positioned rotationally symmetrically with respect to the center selection pixel on the window are output to the same output signal line.

Then, the signal current output to the output signal line 11-1 is input to the multiplier 7-1 and is multiplied by δ there. Similarly, the signal current output to the output signal line 11-2 is input to the multiplier 7-2 and is multiplied by γ there. Similarly, the signal current output to the output signal line 11-3 is input to the multiplier 7-3 and is multiplied by β there. Similarly, the signal current output to the output signal line 11-4 is input to the multiplier 7-4 and is multiplied by α there. Then, the adder 8 adds all the signal currents output from the multipliers 7-1 to 7-4 and outputs the result to the output terminal 14. In this way, the video signal is output while being multiplied by the weighting factor depending on the predetermined position on the window.

Since the pulse of the control signal ΦH1 is switched during the horizontal blanking period, noise generated when the pulse is switched is not mixed in the video signal.

At times T1 and T2, Φc1 is
Horizontal selection switches 3-11 and 3-14 for high level
Is on. At this time, the vertical selection signals Φg1, Φg2,
Since Φg3 is at the high level, the first to third rows of the pixel group are selected, so that the signal currents of the pixels 1-11 and 1-31 are output through the horizontal selection switch 3-11.
The signal current of the pixel 1-21 is output to the output signal line 11-2 via the horizontal selection switch 3-14. As described above, since only the signal currents of the three pixels are simultaneously output, the window processing described above cannot be performed. Further, at times T2 to T3, only signals of 6 pixels are output at the same time, and similarly window processing cannot be performed. Other than this, the times T5 to T7, T9 to T11, T13 to T15, T17 to.
It occurs in the period of T19, T21 to T23. However, in actual use, there is no problem because any of such periods can be cut as an extension of the horizontal blanking period.

This embodiment has the same effect as that of the first embodiment, and unlike the first embodiment, the weighting factors for the upper and lower and left and right pixels with respect to the center can be set to different values. Laplacian processing can be performed even when the pitch is different. Although the same thing can be done in the second embodiment, in the second embodiment, when the signal current of the pixel flows from the vertical signal line to the output signal line, there are two horizontal selection switches through which the signal current passes. Therefore, the number of the present embodiment is small. For this reason, it is possible to suppress the variation in the gain of the signal current, which is a problem in the amplification type image pickup device, which occurs when the signal current passes through the horizontal selection switch. Also,
Since the number of horizontal selection switches that must be driven by each signal output terminal of the horizontal shift register and each output terminal of the OR circuit is as many as four per one output terminal in the second embodiment, a buffer circuit is provided for each output terminal. However, since the number of horizontal selection switches for each output terminal is two in this embodiment, the buffer and the like described above are not required.

(Fourth Embodiment) Next, a fourth embodiment will be described. FIG. 26 shows a fourth example of the image input device according to the invention.
It is a circuit block diagram which shows an Example. The same or corresponding members as those in the first embodiment shown in FIG. 10 are designated by the same reference numerals. Also in this embodiment, the number of pixels is 5 × 4.
Thus, it is configured so that 3 × 3 window processing can be performed. Then, as in the first embodiment, the weighting factor is configured to be rotationally symmetrical with respect to the central pixel. That is, specifically, as shown in FIG. 27, the pixel signals of the pixels A, B, and C corresponding to the center, top, bottom, left, and right of the window are multiplied by different weighting factors. Then, as shown in FIGS. 17A to 17F, there are six types of window processing that can be performed within one frame period.

Further, in this embodiment, two horizontal scanning circuits are provided on the upper and lower sides, and one horizontal shift register is provided for each, so that reading is performed alternately in the vertical direction for each horizontal scanning period. Then, the horizontal shift register belonging to the horizontal scanning circuit for reading outputs a pulse for reading the pixel, and the other shift registers output a pulse for resetting a vertical signal line described later. When one horizontal scan is completed, the role of each horizontal scan circuit is switched,
The pulses output from each horizontal shift register are also interchanged.

Although omitted in the first to third embodiments, generally, in the xy address type solid-state image pickup device, a reset function for setting the vertical signal line to the reference potential before reading the signal current of the pixel. is necessary. In the first to third embodiments, in addition to the configuration shown in each embodiment, a function as shown in, for example, Japanese Patent Laid-Open No. 4-21281 must be added. Can be reset by connecting one of the read signal lines arranged above and below the pixel group to the reference potential.
no need to do that. Therefore, the structure is simple. At the same time, this embodiment also has a horizontal smear prevention function disclosed in Japanese Patent Laid-Open No. 4-212181.

This embodiment differs from the first to third embodiments in that
As described above, the read signal lines 21-1a, 21-3a and 21-1b, 21 are provided above and below the pixel group, respectively.
-3b is arranged, and the read signal line is output signal line 11-1 via connection changeover switches 22-1 to 22-6.
˜11-3. In addition, the image input device according to the present embodiment is provided with the non-destructive read-out pixel group 1
-11 to 1-54, a vertical shift register 2 that controls reading in the vertical direction, and horizontal selection switches 3-11 to 44, 15-11 that select signals read in the horizontal direction.
15-44, horizontal shift registers 4-a and 4-b for controlling the horizontal selection switches, and OR circuits 5-1 to 5-4.
5-5 to 5-8, connection changeover switches 22-1 to 22-6 for switching connection between read signal lines and output signal lines arranged above and below the pixel group, and a multiplier 7 for multiplying a coefficient in pixel output. −1 to 7-3, an adder 8 that adds the outputs of the multipliers, and a GND 2 that is connected to the reference line 23 and serves as a reference potential when the vertical signal line is reset.
It is composed of 4. In FIG. 26, reference numeral 25 indicates a control line of the connection changeover switch.

The OR circuits 5-1 to 5-4 receive the output from the horizontal shift register 4-a and receive the horizontal selection switches 3-13, 3-14, 3-23, 3-24, 3-3.
3, 3-34, 3-43, 3-44 are connected to the control terminals, and horizontal selection switches 3-11, 3-12, 3-21,
Control terminals 3-22, 3-31, 3-32, 3-41, 3-42 are directly connected to the horizontal shift register 4-a. Further, the OR circuits 5-5 to 5-8 receive the output from the horizontal shift register 4-b and receive the horizontal selection switch 15
-11,15-12,15-21,15-22,15-
31, 15-32, 15-41, 15-42 are connected to the control terminals, and horizontal selection switches 15-13, 15-1
4,15-23,15-24,15-33,15-3
The control terminals of 4, 15-43, 15-44 are directly connected to the horizontal shift register 4-b.

The control terminals of the pixels are vertical selection lines 9-1 to 9-.
5, each row is connected to the vertical shift register 2. The output terminals of the pixels 1-11, 1-31, 1-51 are connected to the vertical signal line 10-1, and the horizontal selection switch 3-
Read signal lines 21-2a, 21-3a, 21- via 12, 3-14, 15-12, 15-14, respectively.
2b, 21-1b, and photoelectric conversion elements 1-21,
The output terminal of 1-41 is connected to the vertical signal line 10-2,
Horizontal selection switches 3-11, 3-13, 15-11, 1
Read signal lines 21-1 through 5-13.
a, 21-2a, 21-3b, 21-2b. The output terminals of the pixels 1-12, 1-32, 1-52 are connected to the vertical signal line 10-3, and the horizontal selection switch 3-
Read signal lines 21-2a, 21-3a, 21- via 22, 3-24, 15-22, 15-24, respectively.
2b, 21-1b, and pixels 1-22, 1-
The output terminal of 42 is connected to the vertical signal line 10-4, and horizontal selection switches 3-21, 3-23, 15-21, 15-.
Read signal lines 21-1a, 2
It is connected to 1-2a, 21-3b, 21-2b.

The output terminals of the pixels 1-13, 1-33, 1-53 are connected to the vertical signal line 10-5, and the horizontal selection switches 3-32, 3-34, 15-32, 15-34 are used. , Read signal lines 21-2a, 21-3a,
21-2b, 21-1b, and pixels 1-23, 1
The output terminal of -43 is connected to the vertical signal line 10-6, and the horizontal selection switches 3-31, 3-33, 15-31, 15 are connected.
Read signal lines 21-1a,
It is connected to 21-2a, 21-3b, 21-2b. The output terminals of the pixels 1-14, 1-34, and 1-54 are connected to the vertical signal line 10-7, and the horizontal selection switch 3-4.
Read signal lines 21-2a, 21-3a, and 21-2 via 2, 3-44, 15-42, and 15-44, respectively.
b, 21-1b, and pixels 1-24, 1-4
The output terminal of No. 4 is connected to the vertical signal line 10-8, and the horizontal selection switches 3-41, 3-43, 15-41, 15-4.
3 through read signal lines 21-1a and 21-1
-2a, 21-3b, 21-2b.

In this way, the output terminals of the pixels in each column are 2
The vertical signal lines are connected alternately. The read signal lines 21-1a and 21-1b are connected to the output signal line 11-1 via the connection changeover switches 22-5 and 22-6, respectively.
Alternatively, the read signal lines 21-2a and 21-2b are connected to either the reference line 23 or the output signal line 11-2 or the reference line 23 via the connection changeover switches 22-3 and 22-4, respectively. The read signal lines 21-3a and 21-3b are connected to either the output signal line 11-3 or the reference line 23 via the connection changeover switches 22-1 and 22-2, respectively. And the output signal line 11-1
11-11 are connected to the multipliers 7-1 to 7-3, respectively, and the multipliers 7-1 to 7-3 are connected to the adder 8.

Further, each connection changeover switch 22-1 to 2-2
2-6 are controlled by the control signal ΦH1. In each switch, when the control signal ΦH1 is High, the terminal i and the terminal k of each switch are set, and when the control signal ΦH1 is Low, the terminal j and the terminal k are set.
However, they are connected to each other.

Next, the operation will be described based on the timing charts of this embodiment shown in FIGS. 28 and 29. In this timing chart, times T0 to T8 are the first horizontal scanning period, T8 to T16 are the second horizontal scanning period, and T1.
6 to T24 correspond to the third horizontal scanning period. When the vertical selection signals Φg1 to Φg5 are at the read level, the signal current corresponding to the charge stored in the pixel is ready to be read, and at the reset level, the stored charge is reset and the pixel is Return to the initial state. As long as this reset level is not applied, the signal can be read out any number of times. When the read level and the reset level are not applied, the storage level is always set, and the photo-generated charges are stored in the storage section in each pixel. In this state, the pixel is off, No signal current flows.

First, from time T3 within the first horizontal scanning period.
The signal output at T4 will be described. This corresponds to the window processing state shown in FIG. At this time, since the vertical selection signals Φg1, Φg2, and Φg3 are at the read level, the first to third rows of the pixel group are selected. Since Φs13, Φ11, and Φ13 are at the high level, the horizontal selection switches 3-21, 3-22,
3-13, 3-14, 3-33, and 3-34 are on. At this time, since the control signal ΦH1 is at High level,
Readout signal lines 21-1a, 21-2a, 21-3a
Are connection changeover switches 22-5 and 22-, respectively.
Output signal lines 11-1, 11-
2, 11-3 are connected. Therefore, the pixel 1-1 is connected to the output signal line 11-3 through the horizontal selection switches 3-14 and 3-34 and the connection changeover switch 22-1.
Signal currents 1, 1-31, 1-13, and 1-33 are output. This is the signal of the pixel corresponding to C in FIG. 27 on the window. In addition, the pixels 1-21 and 1- are connected to the output signal line 11-2 through the horizontal selection switches 3-13, 3-22 and 3-33 and the connection changeover switch 22-3.
Signal currents 12, 1-32, and 1-23 are output. This is the signal of the pixel corresponding to B in FIG. 27 on the window. The signal current of the pixel 1-22 is output to the output signal line 11-1 via the horizontal selection switch 3-21 and the connection changeover switch 22-5. This is the signal of the pixel corresponding to A in FIG. 27 on the window.

Next, from time T4 within the first horizontal scanning period.
The signal output at T5 will be described. This corresponds to the window processing state shown in FIG.
At this time, since the vertical selection signals Φg1 to Φg3 are at the read level, the first to third rows of the pixel group are selected. Then, since Φs14, Φ12, and Φ14 are at the high level, the horizontal selection switches 3-31, 3-32, 3
-23, 3-24, 3-43 and 3-44 are on. At this time, since the control signal ΦH1 is at High level,
Readout signal lines 21-1a, 21-2a, 21-3a
Are connection changeover switches 22-5 and 22-, respectively.
Output signal lines 11-1, 11-
2, 11-3 are connected. Therefore, the pixel 1-1 is connected to the output signal line 11-3 through the horizontal selection switches 3-24 and 3-44 and the connection changeover switch 22-1.
Signal currents 2, 1-32, 1-14, and 1-34 are output. This is the signal of the pixel corresponding to C in FIG. 27 on the window. In addition, the pixels 1-22, 1- are connected to the output signal line 11-2 via the horizontal selection switches 3-23, 3-32, 3-43 and the connection changeover switch 22-3.
The signal currents 13, 1-33, 1-24 are output. This is the signal of the pixel corresponding to B in FIG. 27 on the window. The signal current of the pixel 1-23 is output to the output signal line 11-1 via the horizontal selection switch 3-31 and the connection changeover switch 22-5. This is the signal of the pixel corresponding to A in FIG. 27 on the window.

Next, time T11 in the second horizontal scanning period.
The signals output at T12 will be described. This corresponds to the window processing state shown in FIG. At this time, since the vertical selection signals Φg2 to Φg4 are at the read level, the second to fourth rows of the pixel group are selected. Since Φs23, Φ21, Φ23 are at the high level, the horizontal selection switches 15-23, 15-
24, 15-11, 15-12, 15-31, 15-3
2 is on. At this time, since the control signal ΦH1 is at low level, the read signal lines 21-1b and 21-2
b and 21-3b are connection changeover switches 22 respectively.
-6, 22-4, 22-2 through the output signal line 11-
1, 11-2, 11-3 are connected. Therefore, the horizontal selection switch 15-1 is connected to the output signal line 11-3.
The signal currents of the pixels 1-21, 1-41, 1-23, and 1-43 are output via 1, 15-31 and the connection changeover switch 22-2. This is the signal of the pixel corresponding to C in FIG. 27 on the window. Further, the output signal line 11-2 has horizontal selection switches 15-12 and 15-2.
Signal currents of the pixels 1-31, 1-22, 1-42, and 1-33 are output via 3, 15-32 and the connection changeover switch 22-4. This is the signal of the pixel corresponding to B in FIG. 27 on the window. The signal current of the pixel 1-32 is output to the output signal line 11-1 via the horizontal selection switch 15-24 and the connection changeover switch 22-6. This is the signal of the pixel corresponding to A in FIG. 27 on the window.

As described above, the connection changeover switch is switched every horizontal scanning, and the horizontal scanning circuits arranged above and below the pixel group alternately read out, thereby achieving the above object. Hereinafter, T12 to T13, T19 to T2
The same relationship is established at any time of 0 and T20 to T21. This is (D) of FIG.
This corresponds to the window processing states shown in (E) and (F).
In this way, at any timing, the signals of the pixels positioned rotationally symmetrically with respect to the center selection pixel on the window are output to the same output signal line.

Then, the signal current output to the output signal line 11-1 is input to the multiplier 7-1 and is multiplied by α there. Similarly, the signal current output to the output signal line 11-2 is input to the multiplier 7-2 and is multiplied by β there. Similarly, the signal current output to the output signal line 11-3 is input to the multiplier 7-3 and is multiplied by γ there. And adder 8
Then, the signal currents output from the multipliers 7-1 to 7-3 are all added and output to the output terminal 14. In this way, the video signal is output while being multiplied by the weighting factor depending on the predetermined position on the window.

Since the control signal ΦH1 for controlling the connection changeover switch is switched during the horizontal retrace line period, the video signal does not include switching noise generated when the switch is switched.

At times T1 and T2, Φ11 is
Horizontal selection switches 3-13 and 3-14 for high level
Is on. At this time, the vertical selection signals Φg1, Φg2,
Since Φg3 is at the high level, the first to third rows of the pixel group are selected, so that the horizontal selection switch 3-13
The signal current of the pixel 1-21 is output to the read signal line 21-2a, and the pixel 1- is output via the horizontal selection switch 3-14.
The signal currents 11 and 1-31 are read signal lines 21-3a.
Is output to. As described above, since only the signal currents of the three pixels are output at the same time, the window processing described above cannot be performed. Further, at times T2 to T3, only signals of 6 pixels are output at the same time, and similarly window processing cannot be performed. Other than this, the times T5 to T7, T9 to T11, T13 to T15, T17 are also included.
It also occurs during the period from T19 to T21 to T23. But,
In actual use, there is no problem because any of such periods can be cut as an extension of the horizontal blanking period.

Further, this embodiment has a function of preventing lateral smear. This is done by connecting the vertical signal line to the reference potential prior to the read period. This operation will be described based on the timing charts shown in FIGS. 28 and 29. In this embodiment, the number of bits of the pulse for resetting the vertical signal line is 5 bits. At times T1 and T2, since Φ11 is at the high level, the vertical signal line 10-1 passes through the horizontal selection switch 3-14,
The signals of the pixels 1-11 and 1-31 are output to the read signal line 21-3a. In the period T0 to T1 corresponding to the period before the output, since Φ21 is at the high level, the vertical signal line 10-1 is connected to the read signal line 21-2b via the horizontal selection switch 15-12. At this time, since the control signal ΦH1 is at the high level, the read signal line 21
-2b is connected to the reference line 23 via the connection changeover switch 22-4. Therefore,
The vertical signal line 10-1 is connected to the GND 24 and reset to the reference potential.

Similarly, at times T1 and T2, since φ11 is at the high level, the vertical signal line 10-2 is connected to the horizontal selection switch 3
-13 through the read signal line 21-2a to the pixel 1-
21 signal is output. In the period T0 to T1, which is the period before the output, since Φ21 is at the high level,
The vertical signal line 10-2 is connected to the read signal line 21-3b via the horizontal selection switch 15-11. At this time,
Since the control signal ΦH1 is at the high level, the read signal line 21-3b is connected to the reference line 23 via the connection changeover switch 22-2. Therefore, the vertical signal line 10-2 is connected to the GND 24 and reset to the reference potential. As described above, all the vertical signal lines are grounded before the period in which the pixel reading is performed.
By being connected to 24, resetting is performed.

In the first horizontal scanning period, the read signal lines 21-1b to 21-3b are connected to the reference line 2
3 is connected. In addition, in the second horizontal scanning period, the read signal lines 21-1 a to 21-3 a are connected to the reference line 23. The number of bits of the preceding pulse can be any number larger than 3 and smaller than the number of horizontal pixels. As a result, the reset period can be adjusted appropriately, and horizontal smear can be prevented.

In the first to third embodiments, Japanese Patent Laid-Open No. 4-21281 is used.
In order to provide the horizontal smear prevention function disclosed in the publication, the circuit shown in FIG. 36 must be newly added in any of the embodiments, but it is not necessary to add a new circuit in the fourth embodiment. .

Further, as a matter of course, this embodiment has the same effect as that of the first embodiment, and moreover, the configuration of the switch per column of the pixel group is simpler than that of the first embodiment, so that the design and manufacture are performed. Has a feature that can be easily performed.

Thus, in any of the embodiments,
The present invention is disclosed in Japanese Patent Application Laid-Open No. Sho 62-62 shown in FIGS.
In comparison with the one proposed in the publication No. -16685,
It can be seen that the signal processor is significantly simplified. For example, while three adders are required in FIGS. 35A and 35B, only one is required in the present invention.

In each of the above-described embodiments, the number of pixels is set to 5 × 4 for simplification of description, but it goes without saying that the present invention can be applied to the case of more pixels. . Further, in each of the above-mentioned embodiments, the image input device based on the 3 × 3 window processing has been described, but it goes without saying that the present invention is based on the 4 × 4 window processing and above. It can also be applied to the image input device described above. When the present invention is configured to perform m × m (m> 3) window processing, the number of vertical signal lines between each pixel column is (m−1). In this case, the number of vertical signal lines can be less than (m-1) in consideration of the symmetry of the weighting factor on the window.

Further, in each of the above-described embodiments, CM is used as a pixel.
Although the one using a photoelectric conversion element with D in mind is shown, the present invention also applies to an image input device using an amplification type image pickup element such as SIT, FGA, AMI, and BASIS as a pixel.
The same applies.

[0096]

As described above on the basis of the embodiments,
According to the present invention, desired window processing can be performed without using a delay line or delay element, without requiring a special circuit for distributing data, and without having a more complicated signal processing unit. It can be easily done in complete real-time with a simple and inexpensive configuration. Further, in the present invention, since the window processing is performed in analog, A / A required when performing digital processing
The D converter, digital memory device, etc. are unnecessary and consume less power. Further, even when the convolution processing circuit is provided on the same chip as the image sensor, the semiconductor process or the design of the semiconductor becomes easier as compared with the conventional technique. Further, it is possible to obtain an effect that a lateral smear preventing function can be added, for example.

Next, the effects of the invention described in each claim are listed as follows. The effects of the invention described in claims 1 and 2 are that window processing can be performed in a completely real time with a simple and inexpensive configuration. The effect of the invention described in claim 3 is that by performing the control of the horizontal selection switch necessary for achieving the object of the invention described in claim 2 within the horizontal retrace line period, the switching noise generated when the switch is switched is reduced. That is, the influence on the video signal can be reduced or eliminated. Claims 4 and 5
The effect of the invention described is that, when the window processing is performed, when the weighting factor to be multiplied on each pixel signal is vertically symmetrical with respect to the center on the window, the window processing is simple and inexpensive and complete real-time window processing is performed. That is what you can do. The effects of the inventions according to claims 6, 7 and 8 are a simple and inexpensive structure when the weighting factor to be multiplied to each pixel signal when performing the window processing is symmetrical with respect to the center on the window. Moreover, it is possible to perform window processing in completely real time.
The effects of the inventions set forth in claims 9, 10, 11 and 12 are simple and inexpensive when the weighting factor to be multiplied to each pixel signal is rotationally symmetric with respect to the center on the window when the window processing is performed. It is possible to perform window processing in a configuration and in full real time. Claim 1
The effect of the invention described in claim 3 is that horizontal smear can be prevented in the image input device according to claim 12.

[Brief description of drawings]

FIG. 1 is a diagram showing a weight matrix used when performing image enhancement in image processing of an image input apparatus.

FIG. 2 is a diagram showing an output mode of pixel signals when image enhancement is performed using the weight matrix shown in FIG.

FIG. 3 is a diagram showing a signal processing unit when image enhancement is performed using the weight matrix shown in FIG.

FIG. 4 is a circuit configuration diagram showing a basic configuration of an image input device capable of outputting the signals of pixels to which the same weighting factor is multiplied to the same output signal line when the weighting factor is symmetrical.

5 is a diagram showing an output mode of pixel signals in the image input device shown in FIG.

6 is a timing chart for explaining the operation of the image input device shown in FIG.

FIG. 7 is a circuit configuration diagram showing a basic configuration of an image input device capable of outputting signals of pixels to which the same weighting factor is multiplied to the same output signal line when the weighting factor is vertically symmetrical.

8 is a diagram showing an output mode of pixel signals in the image input device shown in FIG.

9 is a timing chart for explaining the operation of the image input device shown in FIG.

FIG. 10 is a circuit configuration diagram showing a first embodiment of the image input device according to the invention.

FIG. 11 is a diagram showing a relationship between pixels and a weighting factor when performing 3 × 3 window processing in the first embodiment.

12 is a diagram showing a configuration and a connection mode of the changeover switch in FIG.

FIG. 13 is a circuit configuration diagram in which symbols of control signals of respective parts are entered in the first embodiment shown in FIG. 10.

14 is a timing chart for explaining the operation of the first embodiment shown in FIG.

15 is a timing chart for explaining the operation of the first exemplary embodiment shown in FIG.

16 is a timing chart for explaining the operation of the first embodiment shown in FIG.

FIG. 17 is a diagram showing six window processing modes that can be performed within one frame period in the first, second, third, and fourth embodiments shown in FIGS. 10, 18, 22, and 26. is there.

FIG. 18 is a circuit configuration diagram showing a second embodiment.

FIG. 19 is a diagram showing a relationship between pixels and a weighting factor when performing 3 × 3 window processing in the second embodiment.

FIG. 20 is a partial circuit configuration diagram showing a difference between the second embodiment and the first embodiment.

FIG. 21 is a timing chart for explaining the operation of the second embodiment.

FIG. 22 is a circuit configuration diagram showing a third embodiment.

FIG. 23 is a diagram showing a relationship between pixels and a weighting factor when performing 3 × 3 window processing in the third embodiment.

FIG. 24 is a timing chart for explaining the operation of the third embodiment.

FIG. 25 is a timing chart for explaining the operation of the third embodiment.

FIG. 26 is a circuit configuration diagram showing a fourth embodiment.

FIG. 27 is a diagram showing a relationship between pixels and weighting factors when performing 3 × 3 window processing in the fourth embodiment.

FIG. 28 is a timing chart for explaining the operation of the fourth embodiment.

FIG. 29 is a timing chart for explaining the operation of the fourth embodiment.

[Fig. 30] Fig. 30 is a diagram showing a weight matrix used for noise removal in image processing.

FIG. 31 is a diagram showing a weight matrix used in the case of image enhancement in image processing.

[Fig. 32] Fig. 32 is a diagram illustrating a conventional configuration example for performing window processing in an image input device.

[Fig. 33] Fig. 33 is a diagram illustrating another conventional configuration example in which window processing is performed in the image input device.

34 is a timing chart for explaining the operation of the configuration example shown in FIG. 33.

[Fig. 35] Fig. 35 is a diagram showing still another example of the conventional configuration for performing window processing in the image input device.

FIG. 36 is a diagram showing a conventional image signal readout circuit having a horizontal smear prevention function.

[Explanation of symbols]

1-11 to 1-54 Pixel 2 vertical shift register 3-11 to 3-48, a1 to a4, b1 to b4, c1 to c
4, d1-d4, e1-e4, f1-f4, g1-g
4, h1 to h4, i1 to i4, j1 to j4, k1 to k
4, l1 to l4, m1 to m4, n1 to n4, o1 to o
4, p1 to p4 horizontal selection switch 4, 4-a, 4-b horizontal shift register 5-1 to 5-8 OR circuit 6-11 to 6-43 changeover switch 7-1 to 7-4 multiplier 8 adder 9-1 to 9-5 Vertical selection line 10-1 to 10-8 Vertical signal line 11-1 to 11-4 Output signal line 12-1 to 12-6, 12-11 to 12-16 Output of horizontal shift register Line 12-7 to 12-10, 12-17 to 12-20 Output line of OR circuit 13-1 Control line for changeover switch 13-2 GND line 14 Output terminal of adder 15-11 to 15-44 Horizontal selection switch 16 Inverters 17-1, 17-2 Control signal lines 21-1a to 21-3b Readout signal lines 22-1 to 22-6 Connection changeover switch 23 Reference line 24 GND 25 Connection changeover switch control line

Claims (13)

[Claims] 1. A pixel portion in which photoelectric conversion elements capable of non-destructive readout while holding electric charges generated by light irradiation are used as pixels, and the pixels are arranged in a matrix, and a pixel portion for selecting the pixels. A horizontal scanning circuit and a vertical scanning circuit including a horizontal selection switch, a signal of an arbitrary pixel selected by the horizontal scanning circuit and the vertical scanning circuit, and the central pixel located in a small area centered on the pixel An image input device comprising: a means for simultaneously reading in parallel signals of at least two or more different pixels; and a means for performing window processing by using all the signals simultaneously read out in parallel, The relative positional relationship between the central pixel in the small area and all the pixels read simultaneously and the plurality of output signal lines for simultaneously reading all the pixels in parallel are always in the same pair. Each pixel and the output signal line are connected in a corresponding relationship, and the signals of the pixels to which the same weighting factor is multiplied in the window processing means are output to the same output signal line. An image input device characterized by. 2. The image input device according to claim 1, wherein the connection between the pixel and the output signal line is configured to be controlled by the horizontal selection switch. 3. The image input device according to claim 2, wherein the horizontal selection switch is configured to be controlled within a horizontal blanking period. 4. Among a plurality of pixels other than the central pixel read out in the small area, signals of pixels vertically symmetrical with respect to the center in the small area are read out to the same output signal line. The image input device according to any one of claims 1 to 3, wherein the image input device is configured as follows. 5. A horizontal scanning circuit including the horizontal selection switch includes a horizontal shift register, and a control circuit to which an output of the horizontal shift register is input and which is controlled by a control signal which switches every horizontal scanning period, The image input device according to claim 4, wherein the horizontal selection switch is configured to be driven by the control circuit. 6. Among a plurality of pixels other than the central pixel read out in the small area, signals of pixels symmetrically positioned with respect to the center in the small area are read out to the same output signal line. The image input device according to any one of claims 1 to 3, wherein the image input device is configured as follows. 7. A horizontal scanning circuit including the horizontal selection switch includes a horizontal shift register and a control circuit controlled by the horizontal shift register, and the horizontal selection switch is driven by the horizontal shift register and the control circuit. 7. The image input device according to claim 6, wherein the image input device is configured as described above. 8. The image input device according to claim 7, wherein the control circuit is an OR circuit. 9. Among a plurality of pixels other than the central pixel read out in the small area, signals of pixels located rotationally symmetrically with respect to the center in the small area are read out to the same output signal line. The image input device according to any one of claims 1 to 3, wherein the image input device is configured as follows. 10. A horizontal scanning circuit including the horizontal selection switch, a horizontal shift register, an OR circuit that receives an output of the horizontal shift register, an output of the horizontal shift register, and an output of the OR circuit, 10. The image input device according to claim 9, further comprising a control circuit controlled by a control signal that switches every horizontal scanning period, and the horizontal selection switch is driven by the control circuit. . 11. A horizontal scanning circuit including the horizontal selection switch includes a horizontal shift register and an OR circuit that receives the output of the horizontal shift register as an input, and the horizontal selection switch has a two-stage configuration in series. 10. The one horizontal selection switch is driven by a horizontal shift register and an OR circuit, and the other horizontal selection switch is driven by a control signal that switches every horizontal scanning period. Image input device. 12. The image input device according to claim 1, wherein horizontal scanning circuits including horizontal selection switches are provided above and below the pixel portion, and the reading operation is alternately performed vertically for each horizontal scanning period. The image input device according to claim 1. 13. In an image input device in which horizontal scanning circuits including the horizontal selection switch are provided above and below a pixel portion, a vertical signal line commonly connected to pixels arranged in a column direction of the pixel portion, and Two sets of read signal lines connected to the vertical signal lines through the upper and lower horizontal selection switches and means for switching and connecting the two sets of read signal lines to the output signal line and the reference line to which the reference potential is applied 13. The vertical signal line is connected to the reference signal line to reset the vertical signal line before the vertical signal line is connected to the output signal line in order to read the pixel signal, so that the horizontal smear can be prevented. The image input device described.