JPH07240740A - Fm multiplexing broadcasting receiver for mobile object - Google Patents

Abstract

PURPOSE:To obtain the error correction decoder for an FM multiplexing broadcasting receiver of mobile object which is capable of making the most of effective data and improving a decoding probability. CONSTITUTION:When the vertical correction of the data parts of all the packets is OK, the data parts are masked not so as to be rewritten in the horizontal correction of the second time and the only error correction of the parity part is performed. When the horizontal correction of the second time is OK, only a first NG flag is superscribed. The CRC check result of the horizontal correction of the second time is on a second NG flag. Further, when a frame synchronizing data output is transferred to a CPU 41 after the horizontal correction of the second time, the first NG flag and the second NG flag are transferred with each packet data. As a result, in a CPU 41, the decision of an OK packet or an NG packet can be made based on the error correction decoding result of the only data part in addition to the error correction decoding result of the whole of the packets.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile FM multiplex broadcast receiver, and more particularly to an error correction decoder of a receiver used for mobile FM multiplex broadcast standardized by the Japan Broadcasting Corporation (NHK). It is a thing.

Mobile FM multiplex broadcasting is a method in which data such as character information is multiplexed with normal FM broadcasting and provided to listeners. For example, an FM radio is provided with a liquid crystal display to display character information separate from FM broadcasting, or it is used in a car navigation device to provide traffic information such as traffic jam conditions.

[0003]

2. Description of the Related Art FIG. 2 shows a frame structure of multiplexed data in mobile FM multiplex broadcasting. Data of mobile FM multiplex broadcasts that are transmitted synchronously can be decoded by majority logic (2
72,190) It has a frame structure product coded by a shortened difference set cyclic code.

One frame is composed of 272 (block) columns (packets). Each packet is 288 bits, and the 16-bit BIC (Block
Identify Code), a 190-bit data portion, and an 82-bit parity portion. At the end of the data part, a 14-bit cyclic code (CRC; Cyclic Red)
undancy Check) is attached.

There are four types of BICs, BIC1 to BIC4, and their arrangements are determined in correspondence with block numbers. That is, BIC1 is defined for packets of 13 blocks with block numbers 1 to 13, and BIC2 is defined for packets of 13 blocks with block numbers 137 to 149. For packets of 123 blocks with block numbers 14 to 136 and 150 to 272, BIC3 is defined for packets of data blocks 1 to 190, and BIC4 is defined for packets of parity blocks 1 to 82.

A conventional error correction decoder for decoding data having such a frame structure is provided with a frame buffer and a data error correction circuit. And FIG.
Each packet transmitted from the outside in synchronization with the packet having the frame structure shown in FIG.
90 and the parity blocks 1 to 82 are rearranged and stored in the frame buffer. That is, in the frame structure shown in FIG. 2, parity blocks 1 to 82 are inserted and arranged in the middle of data blocks 1 to 190.
On the other hand, in the frame buffer, the data blocks 1-190 are arranged in numerical order and then the parity blocks 1-82 are arranged in numerical order. Therefore, in the same manner as the parity part is provided on the right side of the bit string (that is, the packet) when the frame buffer is viewed in the horizontal direction, the parity is provided below the bit row when the frame buffer is viewed in the vertical direction. Block 1
~ 82 are provided. That is, the parity blocks 1 to 82 collected at the bottom of the frame buffer
Each bit row except for BIC4 of
It functions as a parity for each 90 bit row.

One frame (272
When packets of (block) are stored, the error correction circuit performs data error correction in the order of first horizontal correction → vertical correction → second horizontal correction.

In the first horizontal correction, each packet is sequentially read from the frame buffer. Then, according to the parity part of each packet, error correction is performed on the data part and the parity part of the packet. Here, since the parity portion is 82 bits and the data portion is 190 bits, it is possible to correct an error of at least 8 bits and a maximum of 15 bits in the packet.

Next, with respect to the packet for which the error correction has been performed, the syndrome check is performed on the parity part and the CRC check is performed on the CRC. Specifically, a syndrome register and a CRC register are provided in the error correction circuit, the parity part is taken into the syndrome register, and the CRC is taken into the CRC register. As a result, if all the bits (82 bits) of the syndrome register are “OK”, it means that the error has been corrected to the level where the error cannot be detected by the syndrome check.
Correction is OK). On the other hand, "N
If there is even one bit of "G", it means that an error has been detected by the syndrome check (this is BEST
Correction NG). If all bits (14 bits) of the CRC register are "OK", it means that the error has been corrected to the level where the CRC check cannot detect an error (this is called CRC check OK). on the other hand,
If there is at least one "NG" bit in the CRC register,
An error is detected by the CRC check (this is called CRC check NG).

When the BEST correction is OK and the CRC check is OK (this is called the first horizontal correction OK), the error-corrected packet is transferred to the frame buffer and stored in the frame buffer. The packet is erased and replaced with the packet after error correction. On the other hand, BEST correction NG or CRC check NG
At this time (this is called the first horizontal correction NG), the packet for which error correction has been performed is not transferred to the frame buffer, and the original packet stored in the frame buffer is retained as it is. Here, the information of the first horizontal correction OK or NG (1 horizontal check bit) is stored as an NG flag in the area for the horizontal check bit provided in the right end portion (right side of each packet) of the frame buffer. . That is, in the case of the first horizontal correction NG, the NG flag is set.

Subsequently, the packet after the first horizontal correction is transferred and output to the CPU together with the corresponding NG flag. CP
In U, a packet in which the NG flag is not set (a packet in which the first horizontal correction is OK) is treated as a valid packet (OK packet), and a packet in which the NG flag is set (1
The packet of the second lateral correction NG) is treated as an invalid packet (NG packet). Then, the CPU performs processing according to the content of the data portion of the OK packet, and the character information and the like is displayed on the liquid crystal display or the like.

The above processing is repeated for each packet,
First horizontal correction and C for all packets of one frame
If the frame synchronization is established at the time when the transfer output to the PU is completed, then the vertical correction is performed. Here, the frame synchronization is determined by whether or not the BICs 1 to 4 are regularly arranged.

In vertical correction, each bit row of data blocks 1-190 and parity blocks 1-82 is sequentially read from the frame buffer. Then, each bit of the packet of the first horizontal correction OK is masked by referring to the NG flag so that the error correction is performed only for each bit of the packet of the first horizontal correction NG. Then, according to each bit row except the BIC4 of the parity blocks 1 to 82,
Data blocks 1-190 and parity blocks 1-
Error correction is performed on each bit line of 82. Here, since there are 82 parity blocks and 190 data blocks, at least 8 bits in the bit rows of the data blocks 1-190 and parity blocks 1-82 and 15 bits at the maximum, as in the first horizontal correction. Errors can be corrected.

Next, for the bit rows of the data blocks 1-190 and the parity blocks 1-82 for which error correction has been performed, a syndrome check is performed for each bit row of the parity blocks 1-82. Then, as in the case of the first horizontal correction, OK or NG of the BEST correction is determined.

As a result, when the BEST correction is OK (this is called vertical correction OK), the bit rows of the data blocks 1-190 and the parity blocks 1-82 for which error correction has been performed are transferred to the frame buffer, and the frame buffer is transferred. The original bit line stored in the buffer is erased and replaced with the bit line after error correction. On the other hand, in the case of BEST correction NG (this is referred to as vertical correction NG), the error-corrected bit line is not transferred to the frame buffer, and the original bit line stored in the frame buffer is retained as it is. It Here, the vertical correction OK or NG information (1 bit vertical check bit) is stored in the vertical check bit area provided at the lower end of the frame buffer (below the parity block 82).

When the above processing is repeated for each bit row of the data blocks 1-190 and the parity blocks 1-82 and the vertical correction is completed, the second horizontal correction is then performed. In the second horizontal correction, each packet is sequentially read from the frame buffer. Then, referring to the NG flag (horizontal check bit) and the vertical check bit so that only the vertically corrected NG bit is corrected for the first horizontally corrected NG packet, according to the parity part of each packet,
Error correction is performed on the data portion and the parity portion of the packet. In other words, in the second horizontal correction, only 1 bit for the first horizontal correction NG and vertical correction NG is 1
The same error correction as the lateral correction is performed.

Next, with respect to the packet for which error correction has been performed, as in the first horizontal correction, a syndrome check is performed on the parity portion and a CRC check is performed on the CRC.

When the BEST correction is OK and the CRC check is OK (the second horizontal correction is OK), the error-corrected packet is transferred to the frame buffer, and the original packet stored in the frame buffer is erased. And is replaced with the packet after error correction. On the other hand, BE
When ST correction NG or CRC check NG (second horizontal correction NG), the error-corrected packet is not transferred to the frame buffer, and the original packet stored in the frame buffer is retained as it is. . Here, the information of the second horizontal correction OK or NG is overwritten on the NG flag. That is, even if the first horizontal correction is NG, if the second horizontal correction is OK, the horizontal check bit indicating OK is stored in the NG flag. In other words, the NG flag set by the first horizontal correction is cleared by the second horizontal correction.

The above processing is repeated for each packet 1
When the second horizontal correction is completed for all the packets of the frame, all the packets of one frame are processed by the CPU with
Is output as frame synchronization data output to. CP
In U, similarly to after the first horizontal correction, processing according to the valid frame synchronization data output is performed based on the NG flag, and character information or the like is displayed on the liquid crystal display or the like.

These processes are repeated for each frame. In this way, the data is output to the CPU twice after the first horizontal correction and after the second horizontal correction because the time required for completing the second horizontal correction for all the packets of one frame is about This is because it is relatively long, 5 seconds. In other words, the data output after the second horizontal correction can be output only at intervals of about 5 seconds, so if you want to output data at a shorter time interval, the accuracy of data error correction is sacrificed slightly. Therefore, the data output after the first horizontal correction is used.

[0021]

[Problems to be Solved by the Invention] First horizontal correction and 2
In the second horizontal correction, OK or NG of horizontal correction is determined for all 272 bits of the packet excluding the BIC (that is, for the entire packet including the data portion and the parity portion). Therefore, even if the error correction of the data part is completely performed, the lateral correction N is applied to the packet for which the error correction of the parity part is not sufficiently performed.
It is determined to be G and the NG flag is set (that is,
A lateral check bit indicating NG is stored in the NG flag). That is, such a packet is treated as an NG packet by the CPU. In other words, for such a packet, the validity of the data portion is not utilized.

As described above, in the conventional error correction decoder, there is a packet that is treated as an NG packet even though the data portion is valid, and as a result, the CPU
There was a problem that the decoding probability seen from the side was low.

For example, there is a packet in which the parity part contains many errors but the data part contains few errors. For such a packet, the first horizontal correction is determined to be horizontal correction NG, and the NG flag is set. However, since the data portion contains almost no error, the error of the data portion is completely corrected in the next vertical correction. However, since the parity part contains a large number of errors, the vertical part cannot sufficiently correct the error in the parity part. Due to the error remaining in the parity part, the horizontal correction is determined to be NG even in the subsequent second horizontal correction, and the NG flag remains set.

The present invention has been made to solve the above problems, and its object is to correct errors in a mobile FM multiplex broadcast receiver capable of improving decoding probability by utilizing effective data. It is to provide a decoder.

[0025]

The invention according to claim 1 has a frame structure product coded by a majority decision logically decodable (272,190) shortened difference set cyclic code, and each packet constituting the frame. Is composed of a data portion and a parity portion, and a packet which is a bit string in which the frame is viewed laterally by the first horizontal correction for the data structure of the mobile FM multiplex broadcasting in which the cyclic code is added to each packet. Error correction is performed for each
A flag indicating whether or not the error correction in each packet is complete is output together, and then the error is corrected for each bit row when the frame is viewed vertically in the vertical correction, and then the second horizontal correction is performed. The error correction is performed only on the uncorrectable packet at the first horizontal correction, and when the second horizontal correction is completed for all the packets, the frame synchronization data output of all the packets for which the error correction has been completed and the In a mobile FM multiplex broadcast receiver equipped with an error correction decoder that outputs together with a flag indicating whether or not the error correction is complete, when the data portion of all packets is completely corrected and decoded during vertical correction, In the second horizontal correction, error correction is not performed on the data part of each packet, only error correction is performed on the parity part, and when the second horizontal correction is completed for all packets, pari The error correction decoder that outputs both the frame synchronization data output of which all packets are error-corrected packets and the second flag indicating the check result of the cyclic code of the error-corrected packets are provided. And

The invention described in claim 2 is, in the invention described in claim 1, a judgment means for judging whether or not the data portions of all packets have been completely corrected and decoded at the time of vertical correction.
Vertical correction is performed after the first horizontal correction, and if the data portions of all packets are completely corrected and decoded during vertical correction, the subsequent 2
By the error correction method that only corrects the error in the parity part without correcting the error in the data part of each packet in the second horizontal correction, and whether the error correction in the error correction device is complete by the syndrome check and the cyclic code check. And a flag generating means for generating a second flag only by checking the cyclic code when the data part of all packets is completely corrected and decoded at the time of vertical correction. The summary will be given.

According to a third aspect of the invention, in the first aspect of the invention, one is set for each of the frame buffer storing each packet for one frame and the packet or bit line read from the frame buffer. Horizontal correction,
A vertical correction and a second horizontal correction are sequentially performed, and an error correction circuit that determines whether the error correction is complete by syndrome check and cyclic code check, and a vertical check bit that is the determination result of whether the vertical correction is complete are stored. First
Data of all packets in accordance with the vertical check bit stored in the first memory and the second memory in which the flag, which is the determination result of the first horizontal correction and the second horizontal correction, is stored, and the vertical check bit stored in the first memory. A vertical check bit determination circuit for determining whether or not a portion has been completely corrected and decoded, and when the data portion of all packets has been completely corrected and decoded,
A third memory in which the second flag is stored is provided, and when the data portions of all the packets are completely corrected and decoded at the time of vertical correction, the error correction circuit performs the second horizontal correction on the data portion of each packet. The main point is to perform error correction of the parity part without performing error correction.

A fourth aspect of the present invention is based on the third aspect of the invention, wherein the second flag is overwritten on the flag stored in the second memory. According to a fifth aspect of the present invention, in the third aspect of the invention, at least one of the first to third memories is incorporated into the frame buffer.

[0029]

According to the first aspect of the invention, even for a packet in which the error correction of the data part is completely performed but the error correction of the parity part is not sufficiently performed, the data part can be utilized. it can. Therefore, no packet is treated as invalid even though the data portion is valid, and as a result, the decoding probability seen from the output side can be improved.

According to the second aspect of the invention, when the flag generating means completely corrects and decodes the data portions of all the packets at the time of vertical correction, the second flag is generated only by checking the cyclic code.

According to the third aspect of the present invention, the vertical check bit determination circuit determines whether or not the data portions of all packets have been completely corrected and decoded during vertical correction. When the data portions of all the packets have been completely corrected and decoded, the second flag generated according to the cyclic code check in the second horizontal correction by the error correction circuit is stored in the third memory.

According to the invention described in claim 4, since the second flag is overwritten on the flag stored in the second memory, the third memory can be omitted and the third memory can be controlled. Since it is not necessary to do so, the structure of the receiver can be simplified.

According to the fifth aspect of the invention, the structure of the receiver can be simplified by incorporating at least one of the first to third memories in the frame buffer.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below with reference to FIG. FIG. 1 shows the circuit configuration of the error correction decoder of this embodiment. The error correction decoder according to the present embodiment includes a frame buffer 1, a data error correction circuit 2, a vertical check bit determination circuit 3, and a vertical and horizontal check bit selection transfer circuit 4, and these circuits 1 to 4 are controlled. It is controlled by a control signal from the circuit 5.

The error correction circuit 2 is provided with a normal correction determination circuit section 21, a syndrome check circuit section 22 and a CRC check circuit section 23. The normal correction determination circuit unit 21 refers to the vertical check bits and the horizontal check bits transferred from the vertical / horizontal check bit selection transfer circuit 4, and determines whether or not the error correction circuit 2 has performed normal error correction. Syndrome check circuit unit 22
Performs the syndrome check described below. The CRC check circuit unit 23 performs a CRC check described later.

Each packet transmitted from the outside in synchronization with the packet in the frame structure shown in FIG. 2 is stored in the frame buffer 1 with the data blocks 1 to 190 and the parity blocks 1 to 82 rearranged. In the frame buffer 1, data blocks 1 to 19 are provided at the upper part.
An area 11 for storing 0 is provided, and an area 12 for storing parity blocks 1 to 82 is provided below the area 11. Further, the data portion of the packet is stored in the left side portion of the frame buffer 1, and the parity portion is stored in the right side portion 13.

The AND circuit 31 compares the syndrome check result of the syndrome check circuit unit 22 and the CRC check result of the CRC check circuit unit in the first horizontal correction.
Is sent to the frame buffer 1 as information (1 horizontal check bit B) of the first horizontal correction OK or NG. At this time, the AND circuit 31 functions as a 2-input AND. The horizontal check bit B is the horizontal check bit B provided at the right end of the frame buffer 1.
It is stored in the areas 15 and 16 for use as an NG flag.

Further, the normal correction judgment result, the syndrome check result and the CRC check result of the normal correction judgment circuit section 21 in the second horizontal correction are passed through the AND circuit 31 and the information of the second horizontal correction OK or NG (horizontal check bit). B) is sent to the frame buffer 1. At this time, the AND circuit 31 functions as a 3-input AND.
Then, the horizontal check bit B is overwritten on the NG flag of the area 15.

When the NG flag set in the area 15 is the first NG flag and the NG flag set in the area 16 is the second NG flag, both the first and second NG flags are set in the case of the first lateral correction NG. It will be. If the first horizontal correction is NG but the second horizontal correction is OK, the horizontal check bit B indicating OK is stored in the first NG flag, and the first NG flag set in the first horizontal correction is the second horizontal correction. It will be unloaded with a correction.

The normal correction determination result in the vertical correction and the syndrome check result are sent to the frame buffer 1 as vertical correction OK or NG information (1 bit vertical check bit A) via the AND circuit 32. Then, the vertical check bit A is stored in the vertical check bit area 14 provided at the lower end of the frame buffer 1.

The vertical check bit determination circuit 3 is provided in the area 14
Of the 272 vertical check bits A stored in, all 0 to 189 bits corresponding to the data portion are “O”.
K ”(that is, the data portion of all packets is vertically corrected O
K) is determined.

The determination result of the vertical check bit determination circuit 3 and the CRC check result in the second horizontal correction are A
It is sent to the frame buffer 1 as a 1-bit horizontal check bit C via the ND circuit 33. Then, the horizontal check bit C is sent to the area 16 which is the area for the horizontal check bit B and the area for the horizontal check bit C, and is overwritten on the second NG flag set in the area 16 by the first horizontal correction. It That is, even if the first horizontal correction is NG, if 0 to 189 bits of the vertical check bits A are all “OK” (the data portion of all packets is vertical correction OK), the second NG flag indicates OK. The horizontal check bit C is stored, and the second NG flag set by the first horizontal correction is cleared by the second horizontal correction.

As will be described later, the vertical / horizontal check bit selection transfer circuit 4 selects an appropriate bit from the 272-bit first NG flag (horizontal check bit B) and vertical check bit A in vertical correction and second horizontal correction, respectively. Then, the data is transferred to the error correction circuit 2.

Next, the operation of this embodiment thus constructed will be described. One frame (2
(72 blocks) of packets are stored, the error correction circuit 2 performs data error correction in the order of first horizontal correction → vertical correction → second horizontal correction.

In the first horizontal correction, each packet is sequentially read from the frame buffer 1. Then, according to the parity part of each packet, error correction is performed on the data part and the parity part of the packet. Next, with respect to the packet for which error correction has been performed, the syndrome check is performed on the parity part and the CRC check is performed on the CRC. That is,
A syndrome register is provided in the syndrome check circuit unit 22, and a C register is provided in the CRC check circuit unit 23.
An RC register is provided, the parity part is loaded into the syndrome register, and the CRC is loaded into the CRC register. Then, as in the conventional case, the BEST correction is OK or NG, and the CRC check is OK or NG.
Is determined.

As a result, when the BEST correction is OK and the CRC check is OK (the first horizontal correction is OK), the error-corrected packet is transferred to the frame buffer, and the original packet stored in the frame buffer is changed. It is erased and replaced with the packet after error correction. On the other hand, B
In the case of EST correction NG or CRC check NG (first horizontal correction NG), the error-corrected packet is not transferred to the frame buffer, and the original packet stored in the frame buffer is retained as it is. .

The syndrome check result (BEST correction OK or NG) and the CRC check result (CRC check OK or NG) in the first horizontal correction are AND.
The horizontal check bit B (first horizontal correction O
(K or NG information), which is stored in the area 15 as a first NG flag and in the area 16 as a second NG flag.

Subsequently, the packet after the first horizontal correction is transferred and output to the CPU 41 together with the corresponding first NG flag. The CPU 41 treats the packet in which the first NG flag is not set (first horizontal correction OK packet) as a valid packet (OK packet), and invalidates the packet in which the first NG flag is set (first horizontal correction NG packet). It handles as a packet (NG packet). And CP
In U41, processing is performed according to the content of the data portion of the OK packet, and character information and the like are displayed on the liquid crystal display or the like.

The above processing is repeated for each packet,
First horizontal correction and C for all packets of one frame
If the frame synchronization is established at the time when the transfer output to the PU 41 is completed, then the vertical correction is performed. Each area 1
In 5 and 16, the horizontal check bit B is sequentially written in the direction of the arrow α.

In vertical correction, the vertical / horizontal check bit selection transfer circuit 4 uses the first NG flag (horizontal check bit B).
To the "OK" bit and transferred to the error correction circuit 2.

In the vertical correction, the data blocks 1-190 and the parity blocks 1-82 are extracted from the frame buffer 1.
Each bit row of is sequentially read. Then, each bit of the packet of the first horizontal correction OK is masked by referring to the first NG flag from the vertical / horizontal check bit selection transfer circuit 4 so that the error correction is performed only for each bit of the packet of the first horizontal correction NG. To be done. Then, according to each bit row of the parity blocks 1 to 82 excluding the BIC4, error correction is performed on each bit row of the data blocks 1 to 190 and the parity blocks 1 to 82.

Next, for the bit rows of the data blocks 1-190 and the parity blocks 1-82 for which error correction has been performed, a syndrome check is performed for each bit row of the parity blocks 1-82. Then, as in the case of the first horizontal correction, OK or NG of the BEST correction is determined.

As a result, when the BEST correction is OK (vertical correction is OK), the error-corrected data blocks 1 to
The bit lines of 190 and the parity blocks 1 to 82 are transferred to the frame buffer 1, and the original bit line stored in the frame buffer 1 is erased and replaced with the bit line after error correction. On the other hand, in the case of BEST correction NG (vertical correction NG), the error-corrected bit line is not transferred to the frame buffer 1, and the original bit line stored in the frame buffer is retained as it is.

The normal correction judgment circuit section 21 refers to the first NG flag from the vertical and horizontal check bit selection transfer circuit 4,
It is determined whether the error correction circuit 2 has performed normal error correction. The normal correction judgment result and the syndrome check result become a vertical check bit A (information of vertical correction OK or NG) via the AND circuit 32 and are stored in the area 14.

When the vertical correction is completed by repeating the above processing for each bit row of the data blocks 1-190 and the parity blocks 1-82, the second horizontal correction is then performed. In the area 14, the vertical check bits A are sequentially written in the arrow β direction.

The vertical check bit determination circuit 3 determines whether or not 0 to 189 bits corresponding to the data portion of the 272 vertical check bits A stored in the area 14 by the vertical correction are all "OK". To do. That is, all 0 to 189 bits of the vertical check bit A are "O.
If it is “K”, it means that the data portion of all the packets is vertical correction OK.

When the data portion of all the packets is vertical correction OK, the data portion of each packet is masked so as not to be rewritten in the second horizontal correction. for that reason,
Error correction of the data part becomes impossible, and only the parity part can be corrected. On the other hand, the vertical check bit A 0
When there is even one "NG" bit in 189 bits (when the data portion of all packets is not vertical correction OK), in the second horizontal correction, all 272 bits of the packet (data Part and parity part).

In the second horizontal correction, the vertical / horizontal check bit selection / transfer circuit 4 selects the “OK” bit from the first NG flag (horizontal check bit B) and the vertical check bit A and transfers it to the error correction circuit 2.

In the second horizontal correction, each packet is sequentially read from the frame buffer 1. Then, the first NG flag (horizontal check bit B) and the vertical check bit A from the vertical / horizontal check bit selection transfer circuit 4 are referred to so that only the vertically corrected NG bit is corrected for the first horizontally-corrected NG packet. . Then, when the data portion of all the packets is vertical correction OK, error correction is performed only on the parity portion of the packet according to the parity portion of each packet. On the other hand, if the data portion of all the packets is not vertical correction OK, error correction is performed on the data portion and the parity portion of the packet according to the parity portion of each packet. That is, in the second horizontal correction, when the data portion of all the packets is vertical correction OK, the error correction similar to the first horizontal correction is performed only for the bits of the first horizontal correction NG and the vertical correction NG in the parity portion. If the data portion of all the packets is not vertical correction OK, the same error correction as the first horizontal correction is performed on the bits of the first horizontal correction NG and the vertical correction NG of the data portion and the parity portion.

Next, with respect to the packet for which the error correction has been performed, as in the first horizontal correction, the syndrome check is performed on the parity part and the CRC check is performed on the CRC. Then, the BEST correction is OK or NG, and the CRC check is OK or NG.
Is determined.

As a result, when the BEST correction is OK and the CRC check is OK (the second horizontal correction is OK), the error-corrected packet is transferred to the frame buffer, and the original packet stored in the frame buffer is changed. It is erased and replaced with the packet after error correction. On the other hand, B
In the case of EST correction NG or CRC check NG (second horizontal correction NG), the error-corrected packet is not transferred to the frame buffer, and the original packet stored in the frame buffer is retained as it is. .

The normal correction judging circuit section 21 refers to the first NG flag and the vertical check bit B from the vertical / horizontal check bit selection / transfer circuit 4 and judges whether or not the error correction circuit 2 has performed normal error correction. The determination result of the vertical check bit determination circuit 3 and the CRC check result in the second horizontal correction become the horizontal check bit C via the AND circuit 33 and overwrite the second NG flag set in the area 16 in the first horizontal correction. To be done.

The syndrome check result and the CRC check result in the second horizontal correction are the AND circuit 3
It becomes a horizontal check bit B (information of the second horizontal correction OK or NG) via 1 and is overwritten on the first NG flag of the area 15 set by the first horizontal correction.

The above processing is repeated for each packet and 1
When the second horizontal correction is completed for all the packets of the frame, all the packets of one frame are transferred and output to the CPU 41 as the frame synchronization data output together with the first NG flag and the second NG flag.

The CPU 41 determines each packet of the frame synchronization data output according to the first NG flag and the second NG flag as follows. A packet in which the first NG flag is not set; a packet in which the error correction of the data part and the packet part is completely performed. A packet for which the first NG flag is not set does not have the second NG flag set.

The first NG flag is set, but the second NG
Unflagged packet; a packet in which the error correction of the data part has been completed but the error correction of the parity part has not been completed sufficiently.

A packet in which the first NG flag and the second NG flag are set together; a packet in which error correction of both the data portion and the parity portion has not been sufficiently performed. Then, the CPU 41 treats the above and as an OK packet and treats as an NG packet. Then, the CPU 41 performs processing according to the content of the data portion of the OK packet, and the character information and the like are displayed on the liquid crystal display or the like. When the CPU 41 requires a packet in which the error correction of the entire packet including the parity part is completely performed, only the above is treated as an OK packet and NG and
Treat as a packet.

These processes are repeated for each frame. As described above, in the present embodiment, when the data portion of all the packets is vertical correction OK, the data portion is masked so as not to be rewritten in the second horizontal correction, and only the error correction of the parity portion is performed. And the second horizontal correction O
In the case of K, only the first NG flag is overwritten. The CRC check result of the second horizontal correction is overwritten on the second NG flag. Here, if the CRC check of the second horizontal correction is OK, it is extremely unlikely that the data portion of the packet contains an error due to an error correction during vertical correction, and the error correction of the data portion has been completely performed. Can be regarded as a thing. Furthermore, when the frame synchronization data output is transferred to the CPU 41 after the second horizontal correction, the first NG flag and the second NG flag are transferred together with each packet data. As a result, the CPU 41 can determine the OK packet or the NG packet based on the error correction decoding result of only the data portion in addition to the error correction decoding result of the entire packet.

Therefore, according to this embodiment, it is possible to utilize the data portion of a packet in which the error portion of the data portion is completely corrected but the error portion of the parity portion is not sufficiently corrected. Therefore, there are no packets treated as NG packets even though the data portion is valid, and as a result, the decoding probability viewed from the CPU 41 side can be improved. Further, after the second horizontal correction, the first NG flag is also transferred and output in addition to the second NG flag. Therefore, even if the CPU 41 needs a packet in which the error correction of the entire packet including the parity portion is completely performed, Can correspond to.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) The process in the error correction circuit 2 is performed not by hardware but by software. For example,
The syndrome check and CRC check are performed by software without using the syndrome register and CRC register. Further, the error correction processing and the processing in the normal correction judgment circuit unit 21 are performed by software. 2) Replace the functions of the AND circuits 31 to 33 and the vertical check bit determination circuit 3 with software.

3) The areas 14 to 16 are not provided in the frame buffer 1, but are provided in a memory different from the frame buffer 1. Normally, even if one frame of packet is stored in the frame buffer 1, there is still a free area, so that free area can be used as each of the areas 14 to 16. However, if there is no free area in the frame buffer 1, a memory may be provided separately from the frame buffer 1 and the areas 14 to 16 may be stored in the memory.

4) Omit the first NG flag. Then, the packet after the first horizontal correction is transferred and output to the CPU 41 together with the corresponding second NG flag. Also, after the second horizontal correction, only all packets of one frame and the second NG flag are C
Transfer output to PU41. In the CPU 41, the packet in which the second NG flag is not set is set to O
It is treated as a K packet, and a packet in which the second NG flag is set is treated as an NG packet. In this case, CP
On the U41 side, there is a drawback that the error correction decoding result of the entire packet cannot be known, but on the other hand, there is an advantage that the configuration can be simplified because the first NG flag and its control are not required.

By the way, in the above embodiment, each of the regions 14 to
The first to third memories are configured by 16, respectively. The determination means is composed of the area 14 and the vertical check bit determination circuit 3, the error correction means is composed of the error correction circuit 2, and the flag generation means is composed of the error correction circuit 2 and the AND circuits 31 to 33.

[0074]

As described above in detail, according to the present invention, it is possible to provide an error correction decoder for a mobile FM multiplex broadcasting receiver capable of improving the decoding probability by utilizing effective data. .

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment embodying the present invention.

FIG. 2 is a configuration diagram showing a frame configuration of multiplexed data in mobile FM multiplex broadcasting.

[Explanation of symbols]

 1 frame buffer 2 error correction circuit 3 vertical check bit determination circuit 14 to 16 area

Claims (5)

[Claims] 1. A majority-logic decodable (272,190) shortened difference set cyclic code having a frame structure product coded, and each packet constituting the frame consists of a data part and a parity part. For the data structure of mobile FM multiplex broadcasting in which a cyclic code is added to
First, in the first horizontal correction, error correction is performed for each packet that is a bit string when the frame is viewed in the horizontal direction, and the error-corrected packet and a flag indicating whether the error correction in each packet is complete are output together. Then, the vertical correction is performed to correct the error for each bit row when the frame is viewed in the vertical direction, and then the second horizontal correction is performed to correct the error only for the packet that cannot be corrected at the first horizontal correction. When the second horizontal correction is completed for all the packets, the error of the method of outputting the frame synchronization data output which is all the error-corrected packets and the flag indicating whether or not the error correction in each packet is complete In a mobile FM multiplex broadcast receiver equipped with a correction decoder, if the data portion of all packets is completely corrected and decoded at the time of vertical correction, the data of each packet is corrected by the second horizontal correction. Only the error correction of the parity part is performed without performing the error correction of the part, and when the second horizontal correction is completed for all the packets, the parity part is the frame synchronization data output of all the packets whose error is corrected, and the error corrected Mobile FM multiplex broadcast receiver including an error correction decoder that outputs together with a second flag indicating the check result of the cyclic code of the packet. 2. A determination means for determining whether or not the data portions of all packets have been completely corrected and decoded at the time of vertical correction, and a vertical correction is performed after the first horizontal correction so that the data portions of all packets are completely corrected at the time of vertical correction. If it is corrected and decoded to, the following 2
In the second horizontal correction, the error correction means that only corrects the error in the parity part without correcting the error in the data part of each packet, and whether the error correction of the error correction means is complete by the syndrome check and cyclic code check And a flag generating means for generating a second flag only by checking the cyclic code when the data part of all packets is completely corrected and decoded at the time of vertical correction. The mobile FM multiplex broadcast receiver according to claim 1. 3. A frame buffer (1) for storing each packet for one frame, and a first horizontal correction, a vertical correction, and a second horizontal correction for the packet or bit line read from the frame buffer (1). The error correction circuit (2) that performs correction sequentially to determine whether the error correction is complete by the syndrome check and the check of the cyclic code and the vertical check bit (A) that is the result of the determination whether the vertical correction is complete are stored. A first memory (14) and a second memory (15) that stores a flag that is a determination result of whether the first horizontal correction and the second horizontal correction are complete.
And a vertical check bit determination circuit (3) for determining whether or not the data portions of all packets have been completely corrected and decoded according to the vertical check bits (A) stored in the first memory (14), and A third memory (1) in which the second flag is stored when the data portion is completely corrected and decoded.
6), and when the data portion of all packets is completely corrected and decoded at the time of vertical correction, the error correction circuit (2) does not perform error correction of the data portion of each packet in the second horizontal correction and the parity portion 2. The mobile FM multiplex broadcast receiver according to claim 1, wherein only the error correction of the above is performed. 4. The mobile FM multiplex broadcast receiver according to claim 3, wherein the second flag is a second memory (1
A mobile FM multiplex broadcast receiver characterized in that the flag stored in 5) is overwritten. 5. The mobile FM multiplex broadcast receiver according to claim 3, wherein at least one of the first to third memories (14 to 16) is incorporated in the frame buffer (1). Mobile FM multiplex broadcast receiver.