JPH07231085A - Tunnel transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To provide a transistor utilizing tunnel phenomenon which can be highly integrated, speeded up, and multi-functional. CONSTITUTION:The item is provided with a first semiconductor 2 of one conductivity type, a separation layer 3 consisting of a low-impurity concentration semiconductor, and a degenerated second semiconductor 4 with a conductivity type opposite to that of the first semiconductor 2 on a substrate 1. Therefore, a degenerated third semiconductor 5 with the same conductivity type as that of the first semiconductor 2, an insulation layer 6 consisting of a material with a wider forbidden band than that of the third semiconductor 5, and a gate electrode 7 on the insulation layer 6 are provided on the exposed surface of the second semiconductor 4 from the first semiconductor 2 and a ohmic junction is formed on the first semiconductor 2 and the second semiconductor 4 in a drain electrode 8 and a source electrode 9.

Description

Detailed Description of the Invention

[0001]

The present invention relates to high integration, high speed operation,
The present invention relates to a transistor using a tunnel phenomenon that can be multifunctional.

[0002]

2. Description of the Related Art A new tunnel transistor has been proposed which utilizes the tunneling phenomenon of an inversion layer on the surface of a semiconductor and has an operating principle different from that of an ordinary Si MOSFET or bipolar transistor. This device is described in, for example, S. Banerjee et al., IEEE by Bannersey et al.
Electron Device Lett. , EDL
-8, p. 347, 1987). This transistor positively utilizes the tunnel effect which becomes a problem in the limit of miniaturization of MOSFET,
Enables high integration.

FIG. 2 shows a schematic diagram of the structure of a conventional tunnel transistor. The transistor includes a substrate 1, a degenerate first semiconductor 2 having one conductivity type, a degenerate second semiconductor 4 having an opposite conductivity type to the first semiconductor, a first semiconductor 2 and a second semiconductor 4. 2 semiconductor 4 and insulating layer 6 on the substrate 1
A gate electrode 7 on the insulating layer 6, a drain electrode 8 forming ohmic contact with the first semiconductor 2, and a source electrode 9 forming ohmic contact with the substrate 1. Here, the substrate 1 has the same conductivity type as the second semiconductor 4 and has a low concentration of impurities.

The operation of this conventional transistor is performed by the substrate 1
The ^p - -Si, the first semiconductor 2 n ⁺ -Si, p ⁺ -Si the second semiconductor 4, n-type polysilicon SiO _2, the gate electrode 7 on the insulating layer 6, the drain electrode 8 and the source electrode An example using Al for 9 will be described. Here, the source electrode 9 is at earth potential, and a positive voltage is applied to the drain electrode. In between the source and the drain in this state, p ^-
The drain current does not flow because it is in the reverse bias state of the −n ⁺ diode. Now, when a sufficiently large positive voltage is applied to the gate electrode, p ⁻ −Si under the gate electrode is applied.
An inversion layer is formed on the surface of the substrate and electrons are induced. Also, an inversion layer is formed on the p ⁺ -Si surface. Here, since the impurity concentration is high, the electric field strength of the surface inversion layer is increased, and electrons are tunneled from the valence band of p ⁺ -Si to the conduction band of the surface inversion layer. The electrons flow to n ⁺ -Si through the inversion layer on the surface of the substrate. p ⁺ supply of electrons to the -Si valence band p than the source electrode ^- so is through -Si substrate, the result becomes a current flows that between the source and drain electrodes as. Therefore, this conventional device operates as a transistor.

[0005]

This conventional tunnel transistor is based on the principle of controlling the tunnel current between the second semiconductor containing a high concentration of impurities and the inversion layer on the surface thereof. In some cases, the impurity concentration of the second semiconductor cannot be made too high for formation, and a large tunnel current cannot be obtained. Further, as a characteristic, similarly to the conventional transistor, there is a problem that the current changes monotonously with the voltage, which makes it difficult to perform multifunctional operation.

An object of the present invention is to solve the problems of the conventional tunnel transistor and to provide a tunnel transistor capable of high integration, high speed operation, and multi-function operation.

Another object of the present invention is to provide a method of manufacturing such a tunnel transistor.

[0008]

According to another aspect of the present invention, there is provided a tunnel transistor comprising: a first semiconductor having one conductivity type on a substrate; a separation layer made of a semiconductor having a low impurity concentration; and a conductivity type opposite to the first semiconductor. And a degenerate third semiconductor having the same conductivity type as the first semiconductor on the exposed surface of the first semiconductor to the second semiconductor. No. 3, which has an insulating layer made of a material having a bandgap wider than that of the semiconductor, and an electrode on the insulating layer.
The semiconductor and the second semiconductor each have a pair of electrodes forming an ohmic junction.

According to the method of manufacturing a tunnel transistor of the present invention, a first semiconductor having one conductivity type, a separation layer made of a semiconductor having a low impurity concentration, and a conductivity type opposite to the first semiconductor are provided on a substrate. A step of stacking a second semiconductor which has been degenerated, a step of exposing the first semiconductor, the separation layer, and the second semiconductor;
A degenerate third semiconductor having the same conductivity type as that of the semiconductor, an insulating layer made of a material having a wider band gap than the third semiconductor, and an electrode on the insulating layer,
And a step of forming a pair of electrodes forming ohmic junctions on the first semiconductor and the second semiconductor, respectively.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments.

FIG. 1 is a schematic view showing the layer structure of an embodiment of the present invention. In FIG. 1, the same numbers as those in FIG. 2 are equivalent to those in FIG. 2 and perform the same functions. This tunnel transistor has a degenerate structure having a first semiconductor 2 having one conductivity type, a separation layer 3 made of a semiconductor having a low impurity concentration, and a conductivity type opposite to the first semiconductor 2 on a substrate 1. A degenerate third semiconductor 5 having the same conductivity type as that of the first semiconductor 2 on the exposed surface of the first semiconductor 2 to the second semiconductor 4; An insulating layer 6 made of a material having a wider band gap than the semiconductor 5 of 3;
It has a gate electrode 7 on the insulating layer 6, and has a drain electrode 8 and a source electrode 9 that form ohmic junctions with the first semiconductor 2 and the second semiconductor 4, respectively.

The separation layer 3 is made of a semiconductor having a low impurity concentration that prevents a tunnel current from directly flowing between the first semiconductor 2 and the second semiconductor 4. As shown in FIG. 1, the third semiconductor 5 is formed over the second semiconductor surface through the separation layer 3 exposed from the first semiconductor surface, and the insulating layer 6 and the gate electrode 7 are formed thereon. Has been done.

[0013] The operation of the tunnel transistor, ^p on the substrate 1 - -Si, the first semiconductor 2 n ⁺ -S
i, n ^-- Si for the separation layer 3, and p ⁺ -S for the second semiconductor 4.
i, the third semiconductor 5 has n ⁺ -Si, and the insulating layer 6 has Si.
A case where O ₂ , n-type polysilicon is used for the gate electrode 7, and Al is used for the drain electrode 8 and the source electrode 9 will be described.

When the source electrode 9 is set to the ground potential and a positive voltage is applied to the drain electrode 8, the first semiconductor (n ⁺ −
A reverse bias is applied between the Si) 2 and the second semiconductor (p ⁺ -Si) 4. Therefore, no current flows through the separation layer 3. However, the third semiconductor (n ⁺ -Si) 5 is the first
Contacting the semiconductor 2 and the second semiconductor 4 of the above, the n ⁺ −n ⁺ ohmic junction between the first semiconductor 2 and the third semiconductor 5 and the third semiconductor 5 and the second semiconductor 4 are formed. A large current flows between the source and drain through the p ⁺ -n ⁺ tunnel junction between the two. Now, when a negative voltage is applied to the gate electrode 7, the third semiconductor (n ⁺ −
The electrons of Si) 5 are driven away, and the depletion layer extends from the insulating layer / third semiconductor interface. When the gate voltage is increased in the negative direction so that the depletion layer from the insulating layer / third semiconductor interface overlaps with the depletion layer extending from the second semiconductor / third semiconductor interface, The overlap between the valence band and the conduction band of the third semiconductor 5 is reduced, and the tunnel current from the second semiconductor 4 to the third semiconductor 5 is reduced. When the gate voltage is extremely large in the negative direction, this tunnel current stops flowing and the current between the source and drain becomes zero. As described above, in the device of the present invention, a large drain current can be controlled by the gate voltage.

In the tunnel transistor of the present invention, since the potential of the second semiconductor surface is not directly controlled by the gate voltage, the carrier concentration of the second semiconductor 4 can be increased as much as possible and the tunnel current can be easily increased. . Thus, the tunnel transistor of the present invention can solve the conventional problems.

In the above description of the operating principle of the present invention,
Although only the case where the source-drain is reverse biased is described, this is true even when the forward bias is small at the rising voltage or less. In this case, the differential negative resistance characteristic which is characteristic of the tunnel diode (Esaki diode) is controlled, and the operation as a functional element is realized.

Next, a method of manufacturing the tunnel transistor of this embodiment will be described using the same material as that described above.

First, as shown in FIG. 3, n ⁺ —Si (first semiconductor 2), n ⁻ —Si (separation layer 3), and acceptor concentration of 10 are formed on the p ⁻ −Si substrate 1 by molecular beam epitaxy. P ⁺ -Si (second semiconductor 4) of ¹⁹ cm ⁻³ or more is formed. At this time, the thickness of the separation layer 3 is at least several tens of nm so that a tunnel current does not flow between n ⁺ -Si / p ⁺ -Si. Next, as shown in FIG. 4, n ⁻ −Si (separation layer 3) and n ⁺ −Si (first semiconductor 2) are exposed by etching.

Next, as shown in FIG. 5, the exposed surface is again subjected to molecular beam epitaxy so that the donor concentration is 10 ¹⁹ cm.
^-3 or more and n ⁺ -Si (third thickness of several nm to several tens nm)
Forming a semiconductor 5). Further, the surface thereof is thermally oxidized to form SiO ₂ (insulating layer 6), and the n-type polysilicon 10 is formed on the SiO ₂ .

Next, as shown in FIG.
The 0 / insulating layer 6 / third semiconductor 5 layer is etched into the shape of the gate electrode 7.

Next, as shown in FIG. 7, the drain electrode 8 and the source electrode 9 are formed on the first semiconductor 2 and the second semiconductor 4 by Al vapor deposition, respectively, to complete the device.

In the embodiment described here, the depletion type device in which the drain current flows without applying the gate voltage has been described. However, the current does not flow without applying the gate voltage. It is also possible to make an enhancement type in which drain current flows. At this time, it is necessary to make the thickness of the third semiconductor layer thinner than that of the depletion type.

In the above-mentioned embodiments of the present invention, only Si was shown as a semiconductor material, but these layers are made of Ge and Ga.
It is obvious that the present invention can be applied to other semiconductors such as As, InP, InGaAs, GaSb and InAs. Further, these first to third semiconductors may be not only a homojunction made of the same kind of semiconductor but also a heterojunction made of different kinds of semiconductors. Here, SiO ₂ is used as the insulating layer.
However, a semiconductor material having a wider band gap than other insulators such as Si ₃ N ₄ and AlN and the first to third semiconductors (for example, GaP for Si and AlGa for GaAs) is used.
AlGaSb, InG for As, GaSb and InAs
InAs and InP for aAs) may be used.

Another embodiment of the present invention using a semiconductor heterojunction is one using a GaAs / AlGaAs system. The substrate 1 is semi-insulating GaAs, the first semiconductor 2 is n ⁺ -GaAs, the separation layer 3 is n ⁻ -GaAs, and the second semiconductor is n ⁻ -GaAs.
P ⁺ -GaAs the semiconductor 4, n ⁺ the third semiconductor 5 -
The structure of the present invention can be realized by using GaAs, i-Al _0.6 Ga _0.4 As for the insulating layer 6, Al for the gate electrode 7, and Au for the drain electrode 8 and the source electrode 9. Since this material system is a direct transition type semiconductor, the probability of band-to-band tunneling is high, and a tunnel current larger than that of Si system is obtained.

In the embodiment shown here, the n-type semiconductor is used for the first semiconductor and the third semiconductor and the p-type semiconductor is used for the second semiconductor, but the first semiconductor and the third semiconductor are used. It is obvious that the same function can be obtained by the reverse structure using the p-type semiconductor and the n-type semiconductor as the second semiconductor.

[0026]

In the tunnel transistor of the present invention, since a large tunnel current can flow, high speed operation is possible. Further, since the negative resistance characteristic appears, it can be used as a functional element.

The tunnel transistor of the present invention enables ultra-high integration and ultra-high-speed operation and multifunctional operation.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a tunnel transistor of one embodiment of the present invention.

FIG. 2 is a schematic sectional view of a conventional tunnel transistor.

FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

5 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

FIG. 6 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

[Explanation of symbols]

 1 Substrate 2 First Semiconductor 3 Separation Layer 4 Second Semiconductor 5 Third Semiconductor 6 Insulating Layer 7 Gate Electrode 8 Drain Electrode 9 Source Electrode

Claims (5)

[Claims] 1. A first semiconductor having one conductivity type on a substrate, a separation layer made of a semiconductor having a low impurity concentration, and a degenerate second semiconductor having a conductivity type opposite to that of the first semiconductor. A laminated structure including a semiconductor, the first semiconductor to the second semiconductor
A degenerate third semiconductor having the same conductivity type as the first semiconductor on the exposed surface of the semiconductor, an insulating layer made of a material having a wider band gap than the third semiconductor, and an electrode on the insulating layer. A tunnel transistor having a pair of electrodes forming ohmic junctions in the first semiconductor and the second semiconductor, respectively. 2. A first semiconductor having one conductivity type, a separation layer made of a semiconductor having a low impurity concentration, and a second degenerate semiconductor having a conductivity type opposite to that of the first semiconductor on a substrate. A laminated structure including a semiconductor, the first semiconductor to the second semiconductor
A degenerate third semiconductor having the same conductivity type as the first semiconductor on the exposed surface of the first semiconductor, and the first, second and third semiconductors.
A semiconductor having a forbidden band width wider than that of the first semiconductor, an electrode on the layer of the fourth semiconductor, and a pair of electrodes forming ohmic junctions with the first semiconductor and the second semiconductor, respectively. A tunnel transistor having. Wherein the substrate is ^p - -Si, the first semiconductor n ⁺ -Si, the separation layer is ⁿ - -Si, the second semiconductor p ⁺ -Si, said third semiconductor The tunnel transistor according to claim 1, wherein n ⁺ -Si and the insulating layer are SiO ₂ . 4. The substrate is semi-insulating GaAs, the first
Is n ⁺ -GaAs, and the separation layer is n ^-- GaA
s, the second semiconductor is p ⁺ -GaAs, the third semiconductor is n ⁺ -GaAs, and the insulating layer is i-Al _0.6 Ga.
The tunnel transistor according to claim 1, wherein the tunnel transistor is _0.4 As. 5. A first semiconductor having one conductivity type, a separation layer made of a semiconductor having a low impurity concentration, and the first semiconductor on a substrate.
Stacking a degenerate second semiconductor having a conductivity type opposite to that of the semiconductor, exposing the first semiconductor, the separation layer, and the second semiconductor, and exposing the exposed surface. Forming a degenerate third semiconductor having the same conductivity type as the first semiconductor, an insulating layer made of a material having a bandgap wider than that of the third semiconductor, and an electrode on the insulating layer. And a step of forming a pair of electrodes for forming ohmic junctions on the first semiconductor and the second semiconductor, respectively.