JPH07225673A - Arithemetic unit - Google Patents

Abstract

PURPOSE:To reduce the amount of hardwares to be added and to efficiently perform arithmetic operations at the time of performing division by using a DSP. CONSTITUTION:This unit is provided with the arithmetic and logic circuit 4 of (n) bits capable of controlling whether to perform addition or subtraction by signals indicating the positive/negative of an arithmetic result performed one before, the register 2 of (n) bits for tentatively storing the output data at the arithmetic and logic circuit 4, the register 1 of (n) bits for outputting a divisor to the arithmetic and logic circuit 4, (n) stages of shift register 5 for successively storing the signals indicating the positive/negative of the arithmetic result of the arithmetic and logic circuit 4 and a shifter 3 for shifting the data of the register 2 to left for one bit, inserting the data of the most significant bit of the shift register 5 to a least significant bit and performing output to the arithmetic and logic circuit 4. The shitter conventionally provided with the bit length of 2n is replaced with the shifter 3 provided with an (n) bit length and the shift register 5 provided with the bit length of (n).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit inside a digital signal processor for performing division.

[0002]

2. Description of the Related Art In recent years, a digital signal processor (abbreviated as DSP hereinafter) has been attracting attention as a processor for use in equipment such as a mobile phone in response to the movement of introducing a digital system into the field of mobile communication. There is.

In such digital mobile communication, the DSP consumes less power in order to prolong the operating time when used with a battery, and the processing for executing a complicated application program such as a voice codec. Improvement of ability is required. Also, low price is required.

In DSP, division may be performed using the off-the-row method (eg, DSP56116 Dig.
ital Signal Processor Use
r's Manual MOTOROLA INC, 1
990). Hereinafter, an example of an arithmetic unit that divides n-bit data, which is a predetermined plurality of bits, by n-bit data by the release method will be described with reference to the schematic block diagram shown in FIG.

In FIG. 3, reference numeral 101 denotes a register having a length of n bits, which holds a divisor. 102 is 2
It is a register having an n-bit length, in which the upper n bits hold 0 and the lower n bits hold the dividend. Reference numeral 103 denotes a shifter that shifts the data in the register 102 to the left by one bit. First, 0 is inserted in the least significant bit, and thereafter, a signal obtained by inverting the positive / negative signal of the operation result is inserted, and the upper n bits are set. It outputs to the arithmetic logic operation circuit 104 described later, and outputs the lower n bits to the lower part of the register 102. 104 is a register 101 and a shifter 1
03 is an arithmetic logic operation circuit having an n-bit length, performing addition or subtraction in accordance with a signal indicating whether the register 102 is positive or negative, and outputting the operation result to the upper n bits of the register 102.

The arithmetic unit configured as described above will be described in more detail below along with its division operation.

First, the arithmetic logic operation circuit 104 determines whether the data held in the register 102 is positive or negative. Next, the data held in the register 102 is shifted to the left by 1 bit by the shifter 103. At this time, 0 is first inserted in the least significant bit, and thereafter, a signal obtained by inverting the positive and negative signals of the operation result is inserted. The upper n bits of the shift result are output to the arithmetic logic operation circuit 104. The lower n bits of the shift result are output to the register 102. Next, if the value of the register 102 determined as described above is negative, the register 101
Value and the output of the shifter 103 are arithmetic logic operation circuit 104
Add with. If the value of the register 102 determined as described above is non-negative, the arithmetic logic operation circuit 104 subtracts the value of the register 101 from the output of the shifter 103. The above operation is repeated (n-1) times, and finally, whether the register 102 is positive or negative is judged. When the value is negative, 0 is hit in the lowest order of the register 102, and when it is non-negative, 1 is set. As a result,
The quotient is stored in the lower n bits of the register 102.

[0008]

However, in the arithmetic unit of the above conventional example, the shifter 103 needs to have a bit length of 2n, and the shifter 103 to the register 10 is required.
The hardware becomes large because a path to 2 is required. This large hardware causes the DSP to be expensive and has many parts to operate, which causes a problem of high power consumption.

Further, since whether the arithmetic logic operation circuit 104 performs addition or subtraction is controlled by a signal indicating whether the data held in the register 102 is positive or negative, the control is complicated. A large amount of hardware is required to realize this complicated control, and the large amount of hardware causes a problem of high power consumption because the DSP is expensive and many parts operate.

The present invention solves the above-mentioned conventional problems, and is capable of executing the division method by the open-ended method with a small amount of hardware. Therefore, it is possible to provide a low-cost and low-power-consumption arithmetic unit. The purpose is.

[0011]

The technical means of the present invention for achieving the above object is to control whether addition or subtraction is performed by a signal indicating the plus or minus of the operation result performed immediately before. A plurality of predetermined n-bit arithmetic operation means, first storage means for temporarily storing output data of the arithmetic operation means, and n-bit second output means for outputting operation data to the arithmetic operation means. The storage means, an n-stage shift register for sequentially storing a signal indicating whether the arithmetic result of the arithmetic operation means is positive or negative, and the data of the first storage means are left-shifted by 1 bit and the least significant bit of the shift register is stored. And a shifter for inserting the data of the most significant bit and outputting it to the arithmetic operation means.

Another technical means of the present invention for achieving the above object is an arithmetic operation means for performing addition of n bits, which are predetermined plural bits, and a first storage means for temporarily storing output data of the arithmetic operation means. Memory means, second and third memory means for storing operation data, and a signal indicating whether the arithmetic result of the arithmetic operation means is positive or negative, to select one of the second and third data means. Selecting means for outputting to the input of the arithmetic operation means, a shift register for sequentially storing a signal indicating whether the operation result of the arithmetic operation means is positive or negative, and the data in the first storage means is left-shifted by 1 bit to the maximum. A shifter for inserting the data of the most significant bit of the shift register into the lower bits and outputting the data to the arithmetic operation means.

In each of the above technical means, a register can be used as the storage means and a multiplexer can be used as the selection means.

[0014]

Therefore, according to the present invention, since the shift register sequentially stores the positive and negative data output from the arithmetic operation means and inserts the data of the most significant bit into the least significant bit of the shifter, it is conventionally 2n bits. N long shifter
It can be replaced with a shifter having a bit length of n and a shift register having a bit length of n. This makes it possible to reduce the size of the shifter and eliminate the path from the shifter to the first storage means.

Further, since the divisor is stored on one side of the second and third storage means and the two's complement of the divisor is stored on the remaining side, the arithmetic operation means always performs addition only and supplies the supplied data. The selection means selects with a sign indicating whether the calculation result is positive or negative. As a result, the arithmetic operation means always have the same operation,
Control becomes easy.

[0016]

【Example】

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing an arithmetic unit according to the first embodiment of the present invention. In FIG. 1, 1 is a register having a bit length of n and connected to an arithmetic logic operation circuit 4 described later, and holds a divisor. Reference numeral 2 is a register having a bit length of n, the input of which is an output of an arithmetic logic operation circuit 4 which will be described later, and which is connected to a shifter 3 which will be described later. Reference numeral 3 is a shifter for shifting the data in the register 2 to the left by 1 bit and inserting the data of the nth stage of the shift register 5 described later into the least significant bit. 4 is an arithmetic logic operation circuit having a bit length of n,
If the data in register 2 is negative, addition is performed, if non-negative, subtraction is performed, and the operation result is stored in register 2. In addition, a signal indicating whether the operation result is positive or negative is input to the shift register 5 described later. The signal indicating whether the operation result is positive or negative serves as a signal for controlling whether the next instruction performs addition or subtraction. Reference numeral 5 is a shift register having n stages, to which a signal indicating whether the operation result output from the arithmetic logic operation circuit 4 is positive or negative is input, the nth stage is connected to the shifter 3, and the shifter 3 is shifted left by 1 bit. When is executed, data is inserted in the least significant bit. The shift register 5 initially holds the dividend.

The arithmetic unit configured as described above will be described in more detail below along with its division operation.

(1) First, when the data supplied from the register 2 is shifted to the left by 1 bit, the value of the least significant bit of the shift register 5 is inserted into the least significant bit.

Since 0 is initially stored in the register 2 and left-shifted by 1 bit and the most significant bit of the shift register 5 is inserted in the least significant bit, it is always non-negative.

(2) Next, the arithmetic logic operation circuit 4 subtracts the value of the register 1 from the output of the shifter 3.

(3) Next, if the operation result of (2) above is non-negative, the shift register 5 shifts by inserting 1, that is, an inverted sign bit. On the other hand, if the operation result of (2) above is negative, the shift register 5 shifts by inserting 0, that is, an inverted sign bit.

(4) Next, when the shifter 3 shifts the data supplied from the register 2 to the left by one bit, the value of the most significant bit of the shift register 5 is inserted into the least significant bit.

(5) Next, if the previous operation result is non-negative, the value of the register 5 and the output of the shifter 3 are subtracted by the arithmetic logic operation circuit 4. On the other hand, if the previous operation result is negative, the arithmetic logic operation circuit 4 adds the value of the register 5 and the output of the shifter 3. This addition result is saved in the register 2.

(6) Next, if the operation result of (5) above is non-negative, the shift register shifts by inserting 1, that is, an inverted version of the sign bit. On the other hand, the above (5)
If the result of the operation is negative, the shift register shifts by inserting 0, that is, the inverted sign bit.

(7) The operations (4), (5) and (6) are repeated (n-2) times. (8) Finally, the arithmetic logic operation circuit 4 determines whether the register 2 is positive or negative. When the register 2 is negative, 0 is set in the lowest order of the register 2, and when it is nonnegative, 1 is set.

The division can be executed as described above, and the quotient is stored in the shift register 5.

In the conventional example, a shifter having a bit length twice the data bit length of the divisor / dividend was required, but according to this embodiment, a shifter 3 having a data bit length of the divisor / dividend is used.
In addition, the direct path from the shifter 3 to the register 2 can be eliminated.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic block diagram showing an arithmetic unit according to the second embodiment of the present invention. As shown in FIG. 2, the present embodiment is characterized in that a multiplexer 7 for selecting the outputs of the registers 1 and 6 according to the positive / negative judgment result of the register 2 is provided.

In the first embodiment, the sign of the preceding operation is judged and the arithmetic logic operation circuit 4 is judged according to the judgment result.
Is adding or subtracting. In the present embodiment, first, the register 1 has a divisor and the register 6 has a divisor 2
Stores the complement of. The difference is that the arithmetic logic operation circuit 4 always performs addition by controlling the multiplexer 7 that selects according to the sign of the previous operation.

Since the other parts are the same as those in the first embodiment, the same parts are designated by the same reference numerals and the description thereof will be omitted.

In the above configuration, the operation different from that of the first embodiment will be described below.

In the step (5), if the previous operation result is negative, the multiplexer 7 selects and outputs the register 1 holding the divisor, and the arithmetic logic operation circuit 4 sets the value of the register 1 and the shifter. And the output of 3 are added. On the other hand, in the step (5), if the previous operation result is non-negative, the multiplexer 7 selects the register 6 holding the 2's complement of the divisor and outputs it. The value and the output of the shifter 3 are added (that is, the subtraction is performed).

In the present embodiment, the arithmetic logic operation circuit 4
Since the addition is always performed, the hardware configuration becomes easy.

[0036]

As described above, according to the present invention, it is possible to reduce the size of the shifter and eliminate the direct path from the shifter to the register. Therefore, division can be performed with small hardware. As a result, the operating portion becomes smaller and the power consumption can be reduced.

Further, if the arithmetic operation means always add, the control circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing an arithmetic unit according to a second embodiment of the present invention.

FIG. 3 is a schematic block diagram showing a conventional arithmetic unit.

[Explanation of symbols]

 1 register 2 register 3 shifter 4 arithmetic logic operation circuit 5 shift register 6 register 7 multiplexer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoaki Minanda 2-45, Hikosancho, Kanazawa, Ishikawa Prefecture Matsushita Communication Kanazawa Research Institute

Claims (2)

[Claims] 1. An arithmetic operation unit of n bits, which is a predetermined plurality of bits, can be controlled by performing addition or subtraction according to a signal indicating the positive or negative of the operation result performed immediately before, and this arithmetic operation. First storing the output data of the means
Storage means, an n-bit second storage means for outputting operation data to the arithmetic operation means, an n-stage shift register for sequentially storing a signal indicating whether the operation result of the arithmetic operation means is positive or negative, An arithmetic unit provided with a shifter for shifting the data in the memory means 1 to the left by 1 bit, inserting the data of the most significant bit of the shift register into the least significant bit, and outputting the data to the arithmetic operation means. 2. Arithmetic operation means for performing addition of n bits which are a predetermined plurality of bits, first storage means for temporarily storing output data of the arithmetic operation means, and second and third for storing operation data. Storage means, selection means for selecting one of the data stored in the second and third storage means by a signal indicating whether the arithmetic result of the arithmetic operation means is positive or negative, and outputting the selected data to the input of the arithmetic operation means. A shift register for sequentially storing a signal indicating whether the arithmetic result of the arithmetic operation means is positive or negative, and the data in the first storage means are left-shifted by 1 bit, and the data of the most significant bit of the shift register is inserted into the least significant bit. An arithmetic unit comprising a shifter for outputting to the arithmetic operation means.