JPH07221242A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07221242A
JPH07221242A JP6010732A JP1073294A JPH07221242A JP H07221242 A JPH07221242 A JP H07221242A JP 6010732 A JP6010732 A JP 6010732A JP 1073294 A JP1073294 A JP 1073294A JP H07221242 A JPH07221242 A JP H07221242A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
semiconductor element
heat dissipation
dissipation plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6010732A
Other languages
Japanese (ja)
Other versions
JP2713141B2 (en
Inventor
Sadayuki Moroi
定幸 諸井
Kaoru Sonobe
薫 園部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6010732A priority Critical patent/JP2713141B2/en
Publication of JPH07221242A publication Critical patent/JPH07221242A/en
Application granted granted Critical
Publication of JP2713141B2 publication Critical patent/JP2713141B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To improve heat dissipation characteristics of a semiconductor device, thin it by reducing the height dimension, and exclude the deformation of an outer lead. CONSTITUTION:The semiconductor device is constituted as follows; the back of a semiconductor element 1 is bonded to a heat dissipating plate 4 in a plastic molded semiconductor device, a lead 2 is bonded to the heat dissipating plate 4 via an electrically insulating layer 5 on the same surface as the bonding surface of the heat dissipating plate 4 to the semiconductor element 1, and the outer lead 3 of the lead 2 is bent and bonded to a surface different from the bonding surface of the heat dissipating plate 4 to the semiconductor element 1 via an electrically insulating layer 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

【0002】[0002]

【従来の技術】一般に、半導体装置の放熱性の向上は、
半導体装置に要求される性能条件の一つとして極めて重
要である。従来の放熱性を改善した半導体装置の例とし
ては、例えば、特公昭61−77350号公報により提
案されている半導体装置が知られている。図3(a)お
よび(b)は、上記特公昭61−77350号公報によ
り提案されている半導体装置の平面図および断面図であ
る。図3(a)および(b)に示されるように、本従来
例においては、耐熱性があり且つ電気絶縁性があって接
着剤として機能する電気絶縁層5を介して、リード2と
放熱板4が結合されており、当該放熱板4の上面には半
導体素子1が搭載されている。そして、所定のワイヤボ
ンディングが施された後に、半導体素子1および放熱板
4が内包されるように、樹脂封止領域6を介して所定形
状に樹脂封止成形されている。また、外部リード3は、
通常半導体装置下方にL字型またはガルウィング形状等
に成形されており、この外部リード3の先端部は固定さ
れないままの状態となっている。
2. Description of the Related Art In general, the improvement of heat dissipation of a semiconductor device is
It is extremely important as one of the performance conditions required for semiconductor devices. As an example of a conventional semiconductor device having improved heat dissipation, for example, a semiconductor device proposed by Japanese Patent Publication No. 61-77350 is known. 3A and 3B are a plan view and a sectional view of a semiconductor device proposed by the above Japanese Patent Publication No. 61-77350. As shown in FIGS. 3A and 3B, in the conventional example, the lead 2 and the heat sink are provided via the electric insulating layer 5 which has heat resistance and electric insulation and functions as an adhesive. 4 are combined, and the semiconductor element 1 is mounted on the upper surface of the heat dissipation plate 4. Then, after the predetermined wire bonding is performed, the semiconductor element 1 and the heat dissipation plate 4 are resin-sealed and molded in a predetermined shape via the resin sealing region 6 so as to be included therein. The external lead 3 is
Usually, it is formed in the lower part of the semiconductor device in an L-shape or a gull wing shape, and the tips of the external leads 3 are left unfixed.

【0003】[0003]

【発明が解決しようとする課題】上述した従来の半導体
装置(特公昭61−77350号公報により提案されて
いる半導体装置)においては、半導体素子1において発
生する熱量は放熱板4に伝達され、更に放熱板4に接合
されているリード2を介して、外部リード3からプリン
ト基板に伝達されて放熱する方法がとられている。これ
により、前記特公昭61−77350号公報により提案
されている半導体装置の放熱特性は、通常の放熱板を持
たない半導体装置よりも放熱特性が改善されるものとさ
れている。
In the above-described conventional semiconductor device (semiconductor device proposed by Japanese Patent Publication No. 61-77350), the amount of heat generated in the semiconductor element 1 is transmitted to the heat dissipation plate 4, and further, A method is adopted in which heat is transferred from the external leads 3 to the printed board via the leads 2 joined to the heat dissipation plate 4 to radiate heat. As a result, the heat dissipation characteristics of the semiconductor device proposed by Japanese Patent Publication No. Sho 61-77350 are improved as compared with the semiconductor device without the usual heat dissipation plate.

【0004】しかしながら、半導体装置各部の温度分布
を比較してみると、外部リード3の温度は、半導体素子
部よりも30〜40°Cも低い値であり、未だ十分な放
熱作用が行われているとは言い得ない状態となっている
という問題があり、また、樹脂封止に当っては、半導体
素子1および放熱板4は、そのまま樹脂封止領域6内に
内包される構造となっているために、半導体装置全体の
高さを縮小化して薄型化することが困難であるという欠
点がある。
However, comparing the temperature distribution of each part of the semiconductor device, the temperature of the external lead 3 is 30 to 40 ° C. lower than that of the semiconductor element part, and a sufficient heat radiating action is still not performed. However, there is a problem in that it cannot be said that the semiconductor element 1 and the heat dissipation plate 4 are included in the resin sealing region 6 as they are. Therefore, it is difficult to reduce the height of the entire semiconductor device to make it thinner.

【0005】更に、外部リード3の形状が、半導体装置
の下方に曲げられている状態となっているために、何ら
かの外力により外部リード3が容易に変形してしまうと
いう欠点がある。
Further, since the external lead 3 is bent downward in the semiconductor device, the external lead 3 is easily deformed by some external force.

【0006】[0006]

【課題を解決するための手段】第1の発明の半導体装置
は、樹脂封止型半導体装置において、半導体素子の裏面
と放熱板とを接合し、当該放熱板の前記半導体素子との
接合面と同一面上において、当該放熱板に第1の電気絶
縁層を介してリードを接合するとともに、当該リードの
外部導出リードを折り曲げて、所定の第2の電気絶縁層
を介して前記放熱板の半導体素子との接合面とは異なる
面に接合する構造を有することを特徴としている。
According to a first aspect of the present invention, there is provided a semiconductor device in a resin-sealed semiconductor device, wherein a back surface of a semiconductor element and a heat radiating plate are joined to each other, and a joining surface of the heat radiating plate to the semiconductor element is joined. On the same surface, a lead is joined to the heat dissipation plate via a first electric insulation layer, and an external lead of the lead is bent, and a semiconductor of the heat dissipation plate is interposed via a predetermined second electric insulation layer. It is characterized in that it has a structure to be bonded to a surface different from the bonding surface with the element.

【0007】また、第2の発明の半導体装置は、樹脂封
止型半導体装置において、半導体素子の上面と放熱板と
を第1の電気絶縁層を介して接合し、当該放熱板の前記
第1の電気絶縁層との接合面と同一面上において、当該
放熱板に第2の電気絶縁層を介してリードを接合すると
ともに、当該リードの外部導出リードを折り曲げて、第
3の電気絶縁層を介して、前記半導体素子の裏面に当該
半導体素子が外部に露出する状態において接合する構造
を有することを特徴としている。
The semiconductor device of the second invention is, in the resin-sealed semiconductor device, the upper surface of the semiconductor element and the heat dissipation plate are joined via a first electrical insulating layer, and the first heat dissipation plate is bonded. On the same surface as the joint surface with the electric insulating layer, the lead is joined to the heat dissipation plate via the second electric insulating layer, and the lead-out lead of the lead is bent to form the third electric insulating layer. It is characterized in that it has a structure in which the semiconductor element is bonded to the back surface of the semiconductor element in a state where the semiconductor element is exposed to the outside.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0009】図1は本発明の第1の実施例を示す断面図
である。図1に示されるように、本実施例は、半導体素
子1と、リード2と、外部リード3と、放熱板4と、電
気絶縁層5および7と、樹脂封止領域6と、ボンデンィ
ングワイヤ8とを備えて形成されている。本実施例によ
る半導体装置の製造に当っては、まず、リード2の下面
と放熱板4とをポリイミド等の電気的絶縁層5および7
を介して接合したフレームを用い、半導体素子1を、前
記放熱板4の上面、即ちリード2と同一の面上に搭載す
る。そして所定のワイヤボンディングを施した後に、放
熱板4が表面に露出する状態となるような形状に樹脂封
止成形を行う。次に、外部リード3の成形に当っては、
当該外部リード3の先端部が放熱板4と重なるように半
導体装置の下面まで折り曲げて、ポリイミド等の電気的
絶縁層5を介して接合固定する。このように手順により
半導体装置を形成することにより、半導体素子1に発生
する熱量は、外部に露出されている放熱板4に伝達され
て放熱され、更に放熱板4と接合されているリード2お
よび外部リード3を介して、半導体装置の内外部より効
率的に放熱されて、著しい放熱特性の改善を図ることが
できる。且つ、本実施例においては、上述のように、放
熱効果を改善するために、放熱板4が外部に露出された
構成となっているため、半導体装置全体の高さ寸法を
1.0mm以下にして形成することが可能となり、当該
半導体装置の薄型化を図ることができる。更に、本実施
例においては、外部リード3の先端が半導体装置に固定
された構造となっているために、特に多ピン構造の半導
体装置の場合には、外部リードが変形するという問題を
防止することができるという利点がある。
FIG. 1 is a sectional view showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, the semiconductor element 1, the lead 2, the external lead 3, the heat dissipation plate 4, the electrical insulating layers 5 and 7, the resin sealing region 6, and the bonding wire. And 8 are formed. In manufacturing the semiconductor device according to the present embodiment, first, the lower surface of the lead 2 and the heat dissipation plate 4 are electrically connected to the electrically insulating layers 5 and 7 such as polyimide.
The semiconductor element 1 is mounted on the upper surface of the heat dissipation plate 4, that is, on the same surface as the leads 2 by using a frame bonded via the. Then, after performing a predetermined wire bonding, resin sealing molding is performed in such a shape that the heat dissipation plate 4 is exposed on the surface. Next, when molding the external leads 3,
The outer leads 3 are bent to the lower surface of the semiconductor device so that the tip portions of the outer leads 3 overlap with the heat dissipation plate 4, and bonded and fixed via an electrically insulating layer 5 such as polyimide. By forming the semiconductor device by the procedure as described above, the amount of heat generated in the semiconductor element 1 is transferred to the heat radiating plate 4 exposed to the outside to radiate the heat, and the leads 2 and Through the external leads 3, heat is efficiently dissipated from inside and outside of the semiconductor device, so that remarkable heat dissipation characteristics can be improved. In addition, in this embodiment, since the heat dissipation plate 4 is exposed to the outside in order to improve the heat dissipation effect as described above, the height dimension of the entire semiconductor device is set to 1.0 mm or less. It is possible to reduce the thickness of the semiconductor device. Further, in this embodiment, since the tip of the external lead 3 is fixed to the semiconductor device, the problem that the external lead is deformed is prevented especially in the case of a semiconductor device having a multi-pin structure. There is an advantage that you can.

【0010】次に、図2は、本発明の第2の実施例を示
す断面図である。図2に示されるように、本実施例は、
構成要件としては前述の第1の実施例の場合と同様であ
り、半導体素子1と、リード2と、外部リード3と、放
熱板4と、電気絶縁層5、7および9と、樹脂封止領域
6と、ボンディングワイヤ8とを備えて形成されてい
る。しかしながら、本実施例による半導体装置の製造に
当っては、まず、リード2の上面に電気絶縁層5を介し
て放熱板4を接合したリードフレームを用い、半導体素
子1の上面と放熱板4の下面を電気的絶縁層5を介して
接合する。この場合に、放熱板4と電気絶縁層5には、
半導体素子1上の電極およびリード先端間をワイヤボン
ディングすることかできるように、予めスリットをあけ
ておく。そして所定のワイヤボンディングを施した後
に、半導体素子1の裏面が外部に露出するように、所定
の形状に樹脂封止成形を行って樹脂封止領域6を形成し
て、前述の第1の実施例と場合と同様に、外部リード3
を成形・接合する。本実施例の場合には、半導体素子1
自体が外部に露出されているために、当該半導体装置の
放熱効果は更に改善される。また、ボンディングワイヤ
8の高さは、略放熱板上面と同一になり、第1の実施例
と比較して、更に0.1mm程度、半導体装置全体の高
さを低くすることができる。
Next, FIG. 2 is a sectional view showing a second embodiment of the present invention. As shown in FIG. 2, in this embodiment,
The constitutional requirements are the same as in the case of the above-mentioned first embodiment, and the semiconductor element 1, the lead 2, the external lead 3, the heat sink 4, the electric insulating layers 5, 7 and 9, and the resin sealing It is formed by including a region 6 and a bonding wire 8. However, in manufacturing the semiconductor device according to the present embodiment, first, a lead frame in which the heat dissipation plate 4 is bonded to the upper surface of the lead 2 via the electrical insulating layer 5 is used, and the upper surface of the semiconductor element 1 and the heat dissipation plate 4 are formed. The lower surface is joined via the electrically insulating layer 5. In this case, the heat dissipation plate 4 and the electric insulation layer 5 are
Slits are formed in advance so that wire bonding can be performed between the electrodes on the semiconductor element 1 and the tips of the leads. Then, after performing a predetermined wire bonding, a resin sealing region 6 is formed by performing resin sealing molding in a predetermined shape so that the back surface of the semiconductor element 1 is exposed to the outside, and the first embodiment described above is performed. External lead 3 as in the example and case
Molding and joining. In the case of the present embodiment, the semiconductor device 1
Since the semiconductor device itself is exposed to the outside, the heat dissipation effect of the semiconductor device is further improved. Further, the height of the bonding wire 8 is substantially the same as the upper surface of the heat sink, and the height of the entire semiconductor device can be further reduced by about 0.1 mm as compared with the first embodiment.

【0011】[0011]

【発明の効果】以上説明したように、本発明は、半導体
素子の裏面または上面/裏面と放熱板とを接合し、当該
放熱板の半導体素子接合面と同一面に対して、電気絶縁
層を介してリードを接合するとともに、当該リードの外
部導出リードを折り曲げて、前記放熱板の半導体素子と
の接合面とは異なる面、または半導体素子の裏面に電気
絶縁層を介して接合する構造とすることにより、従来の
半導体装置の放熱特性に比較して30〜60%の改善を
得ることができるという効果があり、更に、半導体装置
全体の高さ寸法を、従来よりも0.2〜0.3mm程度
低い値に設計することができるという効果がある。ま
た、外部リード先端が接合、固定化されるために、リー
ド変形不良を著しくて低減することができるという効果
がある。
As described above, according to the present invention, the back surface or the top surface / back surface of the semiconductor element is joined to the heat sink, and the electrical insulating layer is provided on the same surface as the semiconductor element joining surface of the heat sink. The leads are joined together via the leads, and the lead-out leads of the leads are bent so that the leads are joined to the surface different from the joining surface of the heat dissipation plate with the semiconductor element or the back surface of the semiconductor element via the electrical insulating layer. As a result, there is an effect that an improvement of 30 to 60% can be obtained as compared with the heat dissipation characteristics of the conventional semiconductor device, and further, the height dimension of the entire semiconductor device is 0.2 to 0. There is an effect that it can be designed to a value as low as about 3 mm. Further, since the tips of the external leads are bonded and fixed, there is an effect that lead deformation defects can be significantly reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】従来例を示す平面図および断面図である。FIG. 3 is a plan view and a cross-sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 リード 3 外部リード 4 放熱板 5、7、9 電気絶縁層 6 樹脂封止領域 8 ボンデンィグワイヤ 1 Semiconductor Element 2 Lead 3 External Lead 4 Heat Sink 5, 7, 9 Electric Insulation Layer 6 Resin Sealing Area 8 Bonding Wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 樹脂封止型半導体装置において、半導体
素子の裏面と放熱板とを接合し、当該放熱板の前記半導
体素子との接合面と同一面上において、当該放熱板に第
1の電気絶縁層を介してリードを接合するとともに、当
該リードの外部導出リードを折り曲げて、所定の第2の
電気絶縁層を介して前記放熱板の半導体素子との接合面
とは異なる面に接合する構造を有することを特徴とする
半導体装置。
1. In a resin-sealed semiconductor device, a back surface of a semiconductor element and a heat dissipation plate are joined together, and the heat dissipation plate is provided with a first electrical conductor on the same surface as the joining surface of the heat dissipation plate with the semiconductor element. A structure in which a lead is joined via an insulating layer, and the lead-out lead of the lead is bent to be joined to a surface of the heat dissipation plate different from a joining surface with the semiconductor element via a predetermined second electric insulating layer. A semiconductor device comprising:
【請求項2】 樹脂封止型半導体装置において、半導体
素子の上面と放熱板とを第1の電気絶縁層を介して接合
し、当該放熱板の前記第1の電気絶縁層との接合面と同
一面上において、当該放熱板に第2の電気絶縁層を介し
てリードを接合するとともに、当該リードの外部導出リ
ードを折り曲げて、第3の電気絶縁層を介して、前記半
導体素子の裏面に当該半導体素子が外部に露出する状態
において接合する構造を有することを特徴とする半導体
装置。
2. A resin-encapsulated semiconductor device, wherein the upper surface of a semiconductor element and a heat sink are joined together via a first electrical insulating layer, and the heat sink is joined to the first electrical insulating layer. On the same surface, the lead is joined to the heat dissipation plate via the second electric insulation layer, and the lead-out lead of the lead is bent, and is attached to the back surface of the semiconductor element via the third electric insulation layer. A semiconductor device having a structure in which the semiconductor element is joined in a state of being exposed to the outside.
JP6010732A 1994-02-02 1994-02-02 Semiconductor device Expired - Lifetime JP2713141B2 (en)

Priority Applications (1)

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JP6010732A JP2713141B2 (en) 1994-02-02 1994-02-02 Semiconductor device

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Application Number Priority Date Filing Date Title
JP6010732A JP2713141B2 (en) 1994-02-02 1994-02-02 Semiconductor device

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JPH07221242A true JPH07221242A (en) 1995-08-18
JP2713141B2 JP2713141B2 (en) 1998-02-16

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104086A (en) * 1997-05-20 2000-08-15 Nec Corporation Semiconductor device having lead terminals bent in J-shape
JP2009289770A (en) * 2008-05-27 2009-12-10 Koa Corp Resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104086A (en) * 1997-05-20 2000-08-15 Nec Corporation Semiconductor device having lead terminals bent in J-shape
JP2009289770A (en) * 2008-05-27 2009-12-10 Koa Corp Resistor

Also Published As

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