JPH07218593A - Semiconductor diagnostic circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor diagnostic circuit by which a circuit to be tested can be diagnosed at high frequency clock. CONSTITUTION:A semiconductor diagnostic circuit is provided with a PLL(phase lock loop) circuit 11 to generate high frequency clocks, an ordering resistor 13 to send orders synchronously with the clocks, a circuit 16 to be tested which carries out the orders and sends the results synchronously with the clocks, and a data compressing apparatus 17 to receive and compress the results sent out of the circuit to be tested 16 synchronously with the clocks and to send the compressed results. The circuit is also provided with an AND gate 12 to control the supply of the clocks to the circuit 16 to be tested and the data compressing apparatus 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor diagnostic circuit,
In particular, the present invention relates to a circuit suitable for diagnosing an integrated circuit including a PLL (PHASE LOCK LOOP) circuit.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional configuration for diagnosing an integrated circuit incorporating a PLL circuit. Here, the integrated circuit includes a PLL circuit 11, a selector 31, a circuit under test 32, an input / output buffer 33, an input terminal 34, and an output terminal 35.

A test signal for switching the output between the normal mode and the test mode is input to the selector 31. In the normal mode, the clock CLK1 output from the PLL circuit 11 is input to the circuit under test 32 via the selector 31. In the test mode, the clock CLK2 is input from the external terminal 34 and the selector 3
1 is input to the circuit under test 32. The reason why such switching is necessary is that the clock CLK1 generated in the PLL circuit 11 is asynchronous with various signals externally input to the circuit under test 32 in the test mode, and the general-purpose tester uses the clock CLK1. The inability to carry out the test.

[0004]

However, the conventional diagnostic technique has the following two problems.

First, there is a problem that the clock CLK2 input from the external terminal 34 has a lower frequency than the clock CLK1 generated by the PLL circuit 11. PL
The L circuit 11 is capable of converting a reference clock input from the outside into a high frequency, for example, 50 MH.
Higher frequencies above z are possible. However, the clock CLK2 generated by the general-purpose tester is generally 20 to 4
The frequency is as low as 0 MHz. Therefore, the diagnosis can be made only at a frequency lower than the clock CLK1 used in the normal mode, and it is not possible to appropriately determine whether the product is a non-defective product.

Second, the circuit under test 32 operates with the high-frequency clock CLK1, but the large capacity input / output buffer 33 does not operate. Therefore, even if a high-frequency clock is applied to the circuit under test 32 to be operated, the result cannot be taken out from the external output terminal 35 via the input / output buffer 33.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor diagnostic circuit capable of diagnosing a circuit under test with a high frequency clock used in a normal mode.

[0008]

A semiconductor diagnostic circuit according to the present invention is provided with a clock generating means for generating a clock of a higher frequency by receiving a reference clock from the outside, and a clock generating means for synchronizing with the clock generated by the clock generating means. An instruction output means for outputting an instruction, a circuit under test for executing the instruction output from the instruction output means and outputting a result thereof in synchronization with the clock generated by the clock generating means, and the tested circuit. Data compression means for outputting the result output from the test circuit in synchronization with the clock generated by the clock generation means and outputting the compression result, the instruction output means, the circuit under test, and the data compression Clock supply control means for controlling the supply of the clock to the means.

Here, the instruction output means may be constituted by a pseudo random pattern generation means which receives the clock generated by the clock generation means and generates and outputs a pseudo random instruction.

Alternatively, in another semiconductor diagnostic circuit of the present invention, a clock generating means for generating a clock of a higher frequency by inputting a reference clock from the outside, and an address synchronized with the clock generated by the clock generating means. , A memory circuit for outputting prewritten data in synchronization with the clock generated by the clock generating means based on the address output from the address counter, and an output by the memory circuit. Data compression means for receiving the data and compressing in synchronization with the clock generated by the clock generation means and outputting a compression result, and supplying the clock to the address counter, the memory circuit and the data compression means. And a clock supply control means for controlling.

[0011]

A clock is generated from the clock generation means, an instruction is output from the instruction output means in synchronization with this clock, the circuit under test executes the instruction in synchronization with the clock and outputs the result, and the data compression means is provided. Compresses and outputs this result. Further, the clock supply control means controls the supply of clocks to the instruction storage means, the circuit under test, and the data compression means according to the start and stop of the test. In this way, the circuit under test can be diagnosed using the high frequency clock generated by the clock generating means. Even if there is a circuit that does not operate with a high-frequency clock in the periphery, diagnosis can be performed using the result of compression by the data compression means, so the presence of such a circuit does not hinder the diagnosis. It is also possible to give a command to the command output means and control the operation of the clock supply control means by using a low frequency clock. Therefore, diagnosis can be performed using a general inexpensive tester or the like that cannot generate a high frequency clock.

When the instruction output means is constituted by the pseudo random pattern generation means, a clock is given to this means to generate a pseudo random instruction, which is given to the circuit under test.

When diagnosing the storage circuit, an address is output from the address counter in synchronization with the clock, data is output from the storage circuit in synchronization with the clock based on this address, and the data is compressed by the data compression means. Is output. Also in this case, the storage circuit can be diagnosed by using the high-frequency clock generated by the clock generating means.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The semiconductor diagnostic circuit according to the first embodiment is
Circuit under test 16, PLL circuit 11, input / output buffer 1
9, selectors 14, 15 and 18, instruction register 1
3, an AND gate 12, and a data compressor 17.

The circuit under test 16 is an object of diagnosis, and is operated by being supplied with a high frequency clock CLK output from the PLL circuit 11 in the normal mode.

The instruction register 13 stores a test sequence.

The selectors 14, 15 and 18 are supplied with a test signal and switch outputs between the normal mode and the test mode.

The data compressor 17 compresses and sequentially outputs the data sequentially output from the circuit under test 16 in synchronization with the clock CLK.

The first embodiment having the above construction operates as follows.

The test signal is logic "0" in the normal mode. When this test signal is input to the selectors 14, 15 and 18, the signal output from the input terminal A is output.

In the normal mode, the clock CLK output from the PLL circuit 11 is input to the input terminal A of the selector 15 and to the circuit under test 16 and the data compressor 17. In this mode, the clock CLK is not supplied to the instruction register 13. External data is input to the input terminal A of the selector 14 and given to the circuit under test 16 via the selector 14 to perform normal operation. The data output from the circuit under test 16 is input to the input terminal A of the selector 18, supplied to the input / output buffer 19 via the selector 18, and then output to the outside.

In the test mode, the test signal of logic "1" is input to the selectors 14, 15 and 18, and the signal input from the input terminal B is output.

At the start of the test, the test start signal STAR
T becomes logic "1" and is input to the AND gate 12. At this point, the test end signal / STOP output from the instruction register 13 is logic "1". As a result, the clock CL output from the PLL circuit 11
K is input to the instruction register 13 and is ANDed.
It is input to the input terminal B of the selector 15 via the gate 12. The clock CLK input to the selector 15 is input to the circuit under test 16 and the data compressor 17.

The instruction register 13 stores the test sequence in advance, and the instruction is input to the input terminal B of the selector 14 step by step in synchronization with the input clock CLK. This instruction is output from the selector 14 and given to the circuit under test 16. The circuit under test 16 operates based on the given instruction, and the output from the test circuit 16 is input to the data compressor 17. The data compressor 17 compresses the data in synchronization with the clock CLK and inputs the compressed data to the input terminal B of the selector 18. This compressed data is sent to the input / output buffer 19 via the selector 18.
And is output to the outside.

The instruction register 13 outputs a test end signal / STOP of logic "0" to the AND gate 12 when all the instructions are completed. The output from the AND gate 12 is fixed to logic "0", and the clock CLK output from the PLL circuit 11 is used for the instruction register 13, the circuit under test 16,
The data compressor 17 is no longer supplied and the test ends.

Here, the data compressor 17 is provided for compressing data so that the output from the circuit under test 16 need not be observed every clock. When the test is completed, the compression result output from the data compressor 17 is output to the outside via the input / output buffer 19. In this way, since it is only necessary to observe the compressed data after the test is completed, it is only necessary to take out the final compressed data from the input / output buffer 19 that does not operate with the high frequency clock CLK. Therefore, the circuit under test 16 can be tested using the high frequency clock CLK.

Further, the writing of an instruction to the instruction register 13 and the test start signal ST input to the AND gate 12 are performed.
The ART level control can also be performed using a low frequency clock. Therefore, the test can be performed using an inexpensive general-purpose tester that can output only a clock with a frequency of about several tens of MHz.

As an example of a concrete circuit of the data compressor 17, FIG. 2 shows an LFSR (LINEAR FEEDBACK SHIFT RESIST).
OR) indicates. This LFSR has eight EX-OR gates EO1 to EO8 so that 8-bit data can be compressed.
And D flip-flops D1 to D8. After the reset signal RST is input to the reset terminals CL of the D flip-flops D1 to D8 and reset, the PLL circuit 1
The clock CLK output from 1 is input to the clock terminal CK. The EX-OR gates EO1 to EO8 are respectively supplied with the input data I1 to I8 and the outputs from the D flip-flops D8 and D1 to D7 of the preceding stage, and after comparing the same, the comparison result is the D of the subsequent stage. It is input to the data terminal D of the flip-flops D1 to D8. As described above, the D flip-flops D1 to D8 sequentially receive the comparison results output from the EX-OR gates EO1 to EO8, and output the comparison results from the output terminal Q in synchronization with the clock CLK. The output terminals Q of the D flip-flops D1 to D8 are connected to the output terminals O1 to O8 of the LFSR, respectively.

The output data of the circuit under test 16 is the clock C.
The data is input to the data compressor 17 in synchronization with LK. Then, after the test is completed, the final compressed data is output from the output terminals O1 to O8. This compressed data is compared with the expected value obtained by the simulation, and the quality of the circuit under test 16 is diagnosed depending on whether they match. During the test execution, if any of the data output from the circuit under test 16 has an error, this data is transferred to the EX-OR gate EO.
1 to EO8, and an incorrect comparison result is input to the D flip-flop in the subsequent stage. And this D
The erroneous data is output from the flip-flop and is sequentially propagated to the subsequent D flip-flops D1 to D8 via the EX-OR gate in the subsequent stage. Therefore, if there is even one error in the data output from the circuit under test 16, the final compressed data will differ from the expected value,
Diagnosis is possible.

FIG. 3 shows the configuration of a semiconductor diagnostic circuit according to the second embodiment of the present invention. In this embodiment, the RAM 26
Is the target of the test, and the operation of reading the data written in the RAM 26 at a high speed is tested. This RA
In addition to M26, address counter 21, selector 14,
18 and 22 to 25, PLL circuit 11, AND gate 1
2, a data compressor 17, and an input / output buffer 19.

The address counter 21 sequentially outputs the addresses at which the data to be read by the RAM 26 in the test mode is stored from 0 to the final address. The selectors 14 and 22 receive the fmax test signal and switch the connection between the input terminal A or B and the output terminal, and the selectors 23 to 25 receive the test signal and receive the input terminal A or B and the output terminal. Switch the connection. Here, the test signal is used to switch between the normal mode and the test mode, and the fmax test signal is used in the test mode (RAM which uses the low-frequency external clock CLK).
26) or a test mode (reading from the RAM 26) using the high-frequency clock CLK output from the PLL circuit 11 is used.

The operation of the second embodiment will be described below with reference to FIG.
This will be described using the time chart of. In the normal mode, the test signal, the fmax test signal, and the test start signal START are all at the logic "0" level. At this point, the test end signal / STOP is at the logic "1" level.

The test signal is input to the selectors 18, 23 to 25, and the input terminal A and the output terminal are connected. PL
The high frequency clock CLK output from the L circuit 11 is input to the chip enable terminal CE of the RAM 26 via the selector 25. Further, read / write signals R, / W indicating a read or write operation are input to the read / write terminals R, / W of the RAM 26. The selector 23 receives the normal mode address and outputs this signal to the RAM 2
6 to the address input terminal AI. When performing a write operation, normal mode data is input to the selector 24, and this data is input to the data input terminal DI of the RAM 26. As a result, the RAM 26 performs the read or write operation in the normal mode. During the read operation, the data output from the RAM 26 is output to the outside via the selector 18 and the input / output buffer 19.

Next, a test mode for writing data in the RAM 26 at a low speed will be described. In conducting the test,
First, writing of data to the RAM 26 is performed by using the low-frequency external clock CLK. The test signal goes to a logic "1" and the fmax test signal remains a logic "0". Further, the read / write terminals of the RAM 26 are supplied with the read / write signals R and / W of the logic "0" level to enter the write mode.

The test signal is input to the selectors 18, 23 to 25 to connect the input terminal B and the output terminal. fm
The ax test signal becomes the logic "0" level indicating the test with the low frequency clock, and is input to the selectors 14 and 22, and the input terminal A and the output terminal are connected.

External clock C input to the selector 22
LK is input to the chip enable terminal CE of the RAM 26 via the selectors 22 and 25. The external address input to the selector 14 is input to the address input terminal AI of the RAM 26 via the selectors 14 and 23.
The external data input to the selector 24 is the selector 24
Is input to the data input terminal DI of the RAM 26. R
In the AM 26, external data is written according to the external address in synchronization with the external clock CLK.

Next, the mode is shifted to the test mode in which the data written in the RAM 26 is read at high speed. The test signal remains logic "1" and the fmax test signal changes to logic "1". In the selectors 14 and 22, the input terminal B and the output terminal are connected.

Clock C output from PLL circuit 11
LK is input to the AND gate 12 together with the test end signal / STOP (logic “1”) output from the address counter 21 and the test start signal START (logic “1”) input from the outside. Is output. The output clock CLK is input to the selector 22 and RA via the selector 22 and the selector 25.
It is input to the chip enable terminal CE of M26. RA
M26 has read / write signals R and / W of logic "1".
Is input to enter the read mode.

The address counter 21 outputs addresses from 0 to the final address, and the selectors 14 and 2
3 is input to the address input terminal AI of the RAM 26. In the RAM 26, the data stored at the input address is sequentially read out in synchronization with the clock CLK. The data output from the RAM 26 is input to the data compressor 17. The data compressor 17 compresses data in synchronization with the clock CLK. When the address counter 21 outputs the final address, it outputs a test end signal / STOP of logic "0" to the AND gate 12. As a result, the AND gate 12 outputs the PLL
The clock CLK output from the circuit 11 is not output, and the clock C to the RAM 26 and the data compressor 17 is output.
The LK supply is stopped and the test ends.

The final compressed data is output from the data compressor 17 via the selector 18 and the input / output buffer 19 to the outside. The final compressed data is compared with the expected value which has been clarified in advance, and the quality of the RAM 26 is diagnosed.

As described above, according to the second embodiment, the final compressed data may be observed after the end of the test as in the first embodiment. That is, from the input / output buffer 19 that does not operate with the high frequency clock CLK, the clock CL
It is not necessary to retrieve the data in synchronization with K, and the final compressed data may be retrieved only at the end of the test. Therefore,
The high frequency clock CLK can be used to test the RAM 26.

Further, the level control of the test start signal START to be input to the AND gate 12 can be performed even at a low frequency, and the test can be performed using an inexpensive general-purpose tester that can output only a clock having a frequency of about several tens MHz. .

The above-described embodiments are merely examples and do not limit the present invention. For example, the instruction register 13 is used as the instruction output means in the first embodiment. However, the present invention is not limited to this, as long as it can output an instruction to operate the circuit under test. For example,
The pseudo random pattern generating means can also be used as the instruction output means.

FIG. 5 shows an example of the structure of the pseudo random pattern generating means. This circuit outputs a pseudo-random 8-bit instruction by using the clock CLK output from the PLL circuit. The clock CLK is input to the clock terminals CK of the D flip-flops D11 to D18. D flip-flops D12 to D14 and D18
Output data is input to the EX-OR gate EO11,
This output is input to the D flip-flop D11. D
Data is sequentially transferred from the flip-flop D11 to the subsequent D flip-flops D12 to D18 in synchronization with the clock CLK, and the output data from the EX-OR gate EO11 is input to the D flip-flop D11. As a result, each of the D flip-flops D11 to D11
Output terminals O11 to O18 connected to the output terminal Q of D18
From, a pseudo-random instruction is output in synchronization with the clock CLK.

The data compressor is the LS shown in FIG.
It is not limited to FR. Any data can be used as long as it can compress the data output from the circuit under test, extract the final data, and observe the test result.

[0046]

As described above, according to the semiconductor diagnostic circuit of the present invention, a high frequency clock is applied to a circuit under test and its output is compressed to make a diagnosis. Even if there is a circuit that does not exist, the diagnosis is not hindered, and since the operation control of the command output means and the clock supply control means can be performed with a low frequency clock, the diagnosis can be performed using a general inexpensive tester or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor diagnostic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an LSFR which is an example of a data compressor in the semiconductor diagnostic circuit.

FIG. 3 is a block diagram showing a configuration of a semiconductor diagnostic circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart showing waveforms of respective signals in the semiconductor diagnostic circuit.

FIG. 5 is a block diagram showing an example of a configuration of a pseudo random pattern generating means that can be used in place of an instruction register in the semiconductor diagnostic circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional semiconductor diagnostic circuit.

[Explanation of symbols]

 11 PLL Circuit 12 AND Gate 13 Instruction Register 14, 15, 18, 22 to 25 Selector 16 Test Circuit 17 Data Compressor 19 Input / Output Buffer 21 Address Counter 26 RAM EO1 to EO8, EO11 EX-OR Gates D1 to D8, D11-D18 D flip-flop

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H03L 7/08

Claims (3)

[Claims] 1. A clock generation means for inputting a reference clock from the outside to generate a clock of a higher frequency; an instruction output means for outputting an instruction in synchronization with the clock generated by the clock generation means; The circuit under test that executes the instruction output from the instruction output unit and outputs the result in synchronization with the clock generated by the clock generation unit, and the clock generation unit outputs the result output by the circuit under test. Data compression means which is given in synchronization with the clock generated by the above and compresses and outputs the compression result, and a clock supply which controls the supply of the clock to the instruction output means, the circuit under test and the data compression means. A semiconductor diagnostic circuit comprising a control means. 2. The instruction output means comprises a pseudo random pattern generation means for generating and outputting a pseudo random instruction given the clock generated by the clock generation means. 1. The semiconductor diagnostic circuit according to 1. 3. A clock generator for inputting a reference clock from the outside to generate a clock of a higher frequency, an address counter for outputting an address in synchronization with the clock generated by the clock generator, and the address counter. A storage circuit for outputting pre-written data in synchronization with the clock generated by the clock generating means based on the address output from the clock generating means; And a clock supply control means for controlling the supply of the clock to the address counter, the memory circuit and the data compression means. A semiconductor diagnostic circuit characterized by the above.