JPH07183646A - Wiring board and mounting method using it - Google Patents

Wiring board and mounting method using it

Info

Publication number
JPH07183646A
JPH07183646A JP32437193A JP32437193A JPH07183646A JP H07183646 A JPH07183646 A JP H07183646A JP 32437193 A JP32437193 A JP 32437193A JP 32437193 A JP32437193 A JP 32437193A JP H07183646 A JPH07183646 A JP H07183646A
Authority
JP
Japan
Prior art keywords
wiring board
mounting
conductive bump
resin layer
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32437193A
Other languages
Japanese (ja)
Other versions
JP3560996B2 (en
Inventor
Hiroshi Ohira
洋 大平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP32437193A priority Critical patent/JP3560996B2/en
Publication of JPH07183646A publication Critical patent/JPH07183646A/en
Application granted granted Critical
Publication of JP3560996B2 publication Critical patent/JP3560996B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Abstract

PURPOSE:To obtain a circuit device of high reliability at low cost by covering with an unhardened insulating resin layer at least part of a surface of a wiring board for mounting equipped with a group of conductive bumps, which has a connection pad group, each equipped with a conductive bump. CONSTITUTION:A chip mounter is used for a conductive bump 4 of a wiring board 5 for mounting to match, position and arrange electrodes 6a and 6b of a chip-shape resistant element. For this positioning arrangement, a weight is applied instantaneously to the chip mounter to make the tip of the conductive bump 4 in a crushed shape, thus reducing the conductive bump 4 height. Next, this is left in room temperature to harden a room-temperature hardening type silicone resin as an unhardened-shape insulating resin layer 3. This enables the unhardened insulating resin layer 3 to isolate and insulate each connecting part. On the other hand, once it is hardened, its connecting parts are protected from the outer surface and making packaged electronic parts and the wiring board into one unit and fixing it are promoted, thus obtaining the packaged circuit device of high reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子部品の面実装に適す
る実装用配線板およびこの実装用配線板を用いた実装方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting wiring board suitable for surface mounting of electronic components and a mounting method using this mounting wiring board.

【0002】[0002]

【従来の技術】電子機器類の軽小化ないしコンパクト化
を目的として、回路機構の小形化なども図られている。
すなわち、面実装用のパッドを有する配線板面に、所要
の電子部品を実装して成る実装回路装置(実装回路ユニ
ット)が、各種の電子機器類で広く実用に供されつつあ
る。そして、前記電子部品の実装には、ハンダ付けによ
る実装方法が多用されている。具体的には、実装用配線
板の導体ターンの所定位置、すなわち搭載する電子部品
の電極に対応して設けられている各接続パッド面に、ク
リーム状にしたハンダペーストを印刷した後、電子部品
の電極群を対応する接続パッド面に位置を合わせて搭載
・配置し、リロフー炉を通過させてハンダーペーストを
溶かし、冷却固化し、電子部品を配線板上に固定する方
法が一般的に採用されている。なお、この工程において
は、前記配線板面の各接続パッド、もしくは電子部品の
電極面に金属バンプを設けておく場合もある。
2. Description of the Related Art For the purpose of making electronic devices lighter or more compact, circuit structures have been made smaller.
That is, a mounting circuit device (mounting circuit unit) in which required electronic components are mounted on a surface of a wiring board having pads for surface mounting is being widely put to practical use in various electronic devices. A mounting method using soldering is often used for mounting the electronic components. Specifically, after printing a solder paste in a cream shape on a predetermined position of the conductor turn of the mounting wiring board, that is, on each connection pad surface provided corresponding to the electrode of the electronic component to be mounted, the electronic component Generally, the method of mounting and arranging the electrode groups on the corresponding connection pad surface, passing through a Lilofu furnace to melt the solder paste, cooling and solidifying, and fixing the electronic components on the wiring board is generally adopted. ing. In this step, metal bumps may be provided on each connection pad on the wiring board surface or on the electrode surface of the electronic component.

【0003】[0003]

【発明が解決しようとする課題】前記したように、配線
板面への電子部品の実装は、ハンダ付け(ハンダ接続)
法が一般的であるが、ハンダ付け法にはいろいろの問題
点がある。具体的には、 (a)ハンダを溶融するために 200℃〜 300℃の温度が必
要であり、したがって、実装用の配線板については、前
記温度に耐える耐熱性が要求され、また、搭載する電子
部品も、前記温度に耐え得るように耐熱保護を予め施し
ておくことを要する。こうした要求に対しては、比較的
高価な材料を使う必要があり、また使用環境に対して、
必要以上の耐熱保護が必要になるという問題がある。
As described above, the mounting of electronic components on the wiring board surface is performed by soldering (solder connection).
Although the method is common, the soldering method has various problems. Specifically, (a) a temperature of 200 ° C to 300 ° C is required to melt the solder, and therefore, a wiring board for mounting is required to have heat resistance that can withstand the above temperature, and also to be mounted. Electronic parts also need to be preliminarily subjected to heat protection so as to withstand the above temperature. To meet these requirements, it is necessary to use relatively expensive materials,
There is a problem that heat protection more than necessary is required.

【0004】(b)また、前記 200℃〜 300℃のハンダ溶
融温度にて、ストレスフリーでハンダ付けされた電子部
品は冷却過程で、電子部品と配線板の熱膨張率の差によ
って、常温時に大きなストレスを内蔵することになる。
このため、各種環境での長期使用により、接続固定部、
特に応力の集中するハンダ付け部が金属疲労を起こし
て、断線するといった不具合が生じる場合がある。
(B) Also, at the solder melting temperature of 200 ° C. to 300 ° C., stress-free soldered electronic components are cooled at a normal temperature due to a difference in thermal expansion coefficient between the electronic components and the wiring board. It will be a great deal of stress.
For this reason, the connection fixing part,
In particular, the soldered portion where stress is concentrated may cause metal fatigue, resulting in disconnection.

【0005】(c)さらに、ハンダ付けにはフラックスが
必要であり、クリームハンダの場合は、予めハンダペー
ストの中に配合してある。そして、このフラックスは、
ハンダ溶融時に分解して酸性あるいはアルカリ性を呈し
て、配線板の導体パターン面(たとえば銅箔面),ある
いは電子部品の電極の酸化物を除去して、ハンダ付けを
助長する作用がある。しかし、一方では、フラックスの
分解物が電気回路の絶縁性を低下させるという有害作用
があるので、ハンダ付け後、洗浄処理などにより除去す
る必要がある。この除去には、一般的にフロンもしくは
他の有機溶剤の使用を要し、その廃液の地球環境に対す
る悪影響から、代替策が求められている。 (d)高密度
実装回路化に伴って、配線板の配線ピッチが微細になる
と、溶融ハンダが隣接する配線パターン同士がブリッジ
するという不具合も増大してきている。
(C) Further, flux is required for soldering, and in the case of cream solder, it is preliminarily mixed in the solder paste. And this flux is
When the solder melts, it decomposes and exhibits acidity or alkalinity to remove the oxide of the conductor pattern surface (for example, copper foil surface) of the wiring board or the electrode of the electronic component to promote soldering. However, on the other hand, since the decomposed product of the flux has a harmful effect of lowering the insulating property of the electric circuit, it is necessary to remove it by washing treatment after soldering. This removal generally requires the use of CFCs or other organic solvents, and because of the adverse effects of the waste liquid on the global environment, alternative measures are required. (d) As the wiring pitch of wiring boards becomes finer with the development of high-density mounting circuits, the problem that molten solder bridges adjacent wiring patterns is also increasing.

【0006】本発明は前記ハンダ付け実装における問題
を解消(回避)し、低コストでありながら、信頼性の高
い実装回路装置の構成に適する実装用配線板および実装
方法の提供を目的とする。
It is an object of the present invention to solve (avoid) the problems in soldering and to provide a mounting wiring board and a mounting method suitable for the construction of a mounting circuit device which is low in cost and high in reliability.

【0007】[0007]

【課題を解決するための手段】本発明に係る実装用配線
板は、搭載する電子部品の電極群に対応する接続パッド
群を少なくとも一主面に有する実装用配線板であって、
前記実装用配線板面の接続パッド群がそれぞれ導電性バ
ンプを備え、かつ導電性バンプ群を備えた面の少なくと
も一部が未硬化状の絶縁樹脂層で被覆されて成ることを
特徴とし、また、 本発明に係る実装方法は、少なくと
も一主面に導電性バンプを備えた接続パッド群が形成さ
れ、かつ導電性バンプ群を備えた面の少なくとも一部が
未硬化状の絶縁樹脂層で被覆されて成る配線板面上に、
前記導電性バンプ群に対応する電極群を有する電子部品
を位置合わせして搭載・配置する工程と、前記位置合わ
せした配線板の導電性バンプ群および電子部品の電極群
の間にそれぞれ応力が作用するように電子部品を実装す
る工程と、前記配線板面の絶縁樹脂層を硬化する工程と
を具備して成ることを特徴とする。
A mounting wiring board according to the present invention is a mounting wiring board having a connection pad group corresponding to an electrode group of an electronic component to be mounted on at least one main surface,
The connection pad group on the surface of the mounting wiring board has conductive bumps, and at least a part of the surface having the conductive bump group is covered with an uncured insulating resin layer, and In the mounting method according to the present invention, a connection pad group having a conductive bump is formed on at least one main surface, and at least a part of the surface having the conductive bump group is covered with an uncured insulating resin layer. On the surface of the wiring board
A step of aligning and mounting an electronic component having an electrode group corresponding to the conductive bump group, and a stress acts between the conductive bump group and the electrode group of the electronic component of the aligned wiring board. And a step of hardening the insulating resin layer on the surface of the wiring board.

【0008】そして、本発明は次のよう知見に基づいて
成されたものである。つまり、通常の金属は、表面が酸
化物ないし有機物で汚れており、導電性の液体、たとえ
ば導電ペーストなどを接触もしくは塗布固着させても、
その界面にかなり大きな界面抵抗が存在する。しかも、
その界面抵抗は、温度,湿度などの環境で容易に大きく
変動し易く、電子回路には適用し得なかったが、適度の
硬度を有した導電性バンプに、電子部品の電極を成す金
属を押し当て、さらに応力を作用させると、金属表面の
汚れが機械的に排除されて新生面を露出し、金属の新生
面および導電バンプの新生面が、界面抵抗零の接合を容
易に形成することを見出して、この現象を利用して本発
明を完成するに至ったものである。
The present invention is based on the following knowledge. That is, the surface of an ordinary metal is contaminated with an oxide or an organic substance, and even if a conductive liquid such as a conductive paste is contacted or applied and fixed,
There is a fairly large interfacial resistance at that interface. Moreover,
The interface resistance easily fluctuates greatly in environments such as temperature and humidity and could not be applied to electronic circuits, but the conductive bumps of appropriate hardness were pressed against the metal forming the electrodes of electronic parts. When applying and further applying stress, it was found that the dirt on the metal surface is mechanically removed to expose the new surface, and the new surface of the metal and the new surface of the conductive bump easily form a bond with zero interface resistance. The present invention has been completed by utilizing this phenomenon.

【0009】本発明において、実装用配線板は、たとえ
ばソルダーレジストを印刷し、仕上げ処理する前の、外
層回路パターン上の所定位置に、導電性バンプ群を形成
する一方、それら導電性バンプ群をほぼ埋める程度の厚
さに、未硬化の絶縁性樹脂を一体的に設けることにより
構成される。なお、未硬化の絶縁性樹脂層は、前記導電
性バンプ群を形成した面全体に設ける必要はなく、たと
えば各導電性バンプの周辺部など、島状に形成した形態
を採ってもよい。
In the present invention, the mounting wiring board is formed with conductive bump groups at predetermined positions on the outer layer circuit pattern before the solder resist is printed and finished, for example, while the conductive bump groups are formed. It is configured by integrally providing an uncured insulating resin with a thickness that is almost filled. The uncured insulating resin layer does not have to be provided on the entire surface on which the conductive bump group is formed, and may be formed in an island shape such as a peripheral portion of each conductive bump.

【0010】ここで、印刷配線板の外層回路を形成する
銅パターンなどは、各種の工程履歴において、表面が汚
染されているので、機械研磨ないし化学研磨を行い清浄
面にしてから、導電性バンプ群を形成することが望まし
く、清浄面化しておくことにより、銅パターンと導電性
バンプ群との界面抵抗の発生防止を助長し得る。また、
前記導電性バンプは、たとえば銀,金,銅,ハンダ粉な
どの導電性粉末、これらの合金粉末もしくは複合の金属
粉末と、たとえばポリカーボネート樹脂,ポリスルホン
樹脂,ポリエステル樹脂,フェノキシ樹脂,エポキシ樹
脂、フェノール樹脂,ポリイミド樹脂などのバインダー
成分とを混合して調製された導電性組成物、あるいは導
電性金属、導電性有機半導体などで構成される。そし
て、導電性組成物で形成する場合は、たとえば比較的厚
いメタルマスクを用いた印刷法により、アスペクト比の
高い導電性バンプを形成でき、その導電性バンプの高さ
は、一般的に10〜 400μm 程度の広範囲で形成できる。
Here, since the surface of the copper pattern forming the outer layer circuit of the printed wiring board is contaminated in various process histories, the surface of the copper pattern is mechanically or chemically polished to be a clean surface, and then the conductive bumps are formed. It is desirable to form a group, and by making the surface clean, it is possible to promote the prevention of the occurrence of the interface resistance between the copper pattern and the conductive bump group. Also,
The conductive bumps are made of conductive powder such as silver, gold, copper or solder powder, alloy powder of these or composite metal powder, and polycarbonate resin, polysulfone resin, polyester resin, phenoxy resin, epoxy resin, phenol resin, for example. , A conductive composition prepared by mixing a binder component such as a polyimide resin, or a conductive metal, a conductive organic semiconductor, or the like. When the conductive composition is formed, a conductive bump having a high aspect ratio can be formed by, for example, a printing method using a relatively thick metal mask, and the height of the conductive bump is generally 10 to 10. It can be formed in a wide range of about 400 μm.

【0011】一方、導電性金属でバンプを形成する手段
としては、 (a)銅箔を外層回路パターンとした場合は、
メッキレジストを印刷・パターニングして、銅,錫,
金,銀,ハンダなどをメッキして、選択的に微小な金属
柱(バンプ)群の形成するか、(b)外層回路パターン面
にハンダレジストの塗布・パターニングを行ってから、
ハンダ浴に浸漬して選択的に微小な金属柱(バンプ)の
形成などが挙げられる。ここで、導電性バンプに相当す
る微小金属魂ないし微小な金属柱は、異種金属を組合わ
せて成る多層構造、多層シェル構造でもよい。
On the other hand, as means for forming bumps of conductive metal, (a) when copper foil is used as an outer layer circuit pattern,
Printing and patterning plating resist, copper, tin,
After plating gold, silver, solder, etc. to selectively form minute metal pillars (bumps), or (b) applying and patterning a solder resist on the outer layer circuit pattern surface,
For example, it may be immersed in a solder bath to selectively form minute metal columns (bumps). Here, the minute metal particles or minute metal columns corresponding to the conductive bumps may have a multilayer structure or a multilayer shell structure formed by combining different metals.

【0012】なお、本発明において、導電性バンプを導
電性組成物で形成する場合は、メッキ法などの手段で行
う場合に較べて、さらに工程など簡略化し得るので、低
コスト化の点で有効である。また、適度の硬度を有する
導電性バンプとは、搭載・実装する電子部品の電極を成
す金属面の酸化物や有機物などの汚染物層を、押圧力な
どによって対接面から機械的に排除し、金属の新生面を
露出できる程度以上の応力を作用させた場合、電子部品
の電極を変形ないし破壊しない程度の硬度を要し、一般
的にはジュロメータ硬度で70〜 120が好適である。
In the present invention, when the conductive bumps are formed of a conductive composition, the process can be further simplified as compared with the case where the conductive bumps are formed by a plating method or the like, which is effective in terms of cost reduction. Is. In addition, conductive bumps with appropriate hardness are used to mechanically remove the contaminant layer such as oxides and organic substances on the metal surface forming the electrodes of electronic parts to be mounted and mounted from the contact surface by pressing force. When a stress is applied to the surface of the newly formed metal, the hardness of the electrode of the electronic component should not be deformed or destroyed, and a durometer hardness of 70 to 120 is generally preferable.

【0013】また、前記導電性バンプの大きさは、搭載
・実装する電子部品の電極の大きさに対応させるが、上
記導電性バンプの形成手段によって、径10〜 400μm 程
度で任意に形成できる。またバンプの形状は底面が大き
く先端部向かって細くなる形状が好適であり、山形ない
し半球状などでもよい。
The size of the conductive bumps corresponds to the size of the electrodes of the electronic parts to be mounted and mounted, but the conductive bumps can be arbitrarily formed to have a diameter of about 10 to 400 μm. The shape of the bump is preferably such that the bottom surface is large and becomes narrower toward the tip, and may be a mountain shape or a hemispherical shape.

【0014】前記導電性バンプを埋める程度の厚さに配
線板面上に、一体的に配置形成されている未硬化状の絶
縁樹脂層は、前記配線板の全面に配置形成してもよい
し、必要部分にのみ、選択的に配置形成してもよいし、
また、電子部品を搭載する直前に未硬化状の絶縁樹脂層
を塗布形成する形態を採ってもよい。この絶縁樹脂層
は、搭載された電子部品を固着する役割と、配線板の回
路部を保護する役割と、接続部を保護する役割とを兼ね
備える。そして、この絶縁樹脂層は、熱硬化型樹脂や紫
外線硬化型樹脂、嫌気性硬化樹脂、もしくはそれらの混
合タイプなどで形成しておき、電子部品搭載後紫外線な
いし加熱で硬化させるのが好ましく、たとえばソルダー
レジストとして市販されている樹脂が好適である。
The uncured insulating resin layer that is integrally formed and formed on the surface of the wiring board to a thickness to fill the conductive bumps may be formed and formed on the entire surface of the wiring board. , May be selectively formed only in a necessary portion,
Further, the uncured insulating resin layer may be applied and formed immediately before mounting the electronic component. The insulating resin layer has a role of fixing the mounted electronic component, a role of protecting the circuit portion of the wiring board, and a role of protecting the connection portion. It is preferable that the insulating resin layer is formed of a thermosetting resin, an ultraviolet curable resin, an anaerobic curable resin, or a mixed type thereof, and is cured by ultraviolet rays or heating after mounting the electronic component. A resin that is commercially available as a solder resist is suitable.

【0015】さらに、本発明の実装方法において、電子
部品の電極と配線板の導電性バンプとを、応力の作用に
よって界面抵抗がほぼ零の接続を形成して実装する際、
前記応力の付与は、通常、 0.5〜20 N/バンプ当たり程
度の力、導電性バンプの形状や材質によっては、未硬化
状樹脂の硬化収縮性などでもよい。つまり、搭載・実装
する電子部品は、通常、異なるメーカー製品の寄せ集め
であるため、その保存期間も一定でなく、電極材料の種
類も違うので、表面の汚れをなす酸化物層や有機物の種
類、また、その厚さなども多様であるが、一般的に通常
の電子部品では、汚染層の厚みがサブミクロンオーダー
である。そして、この程度の厚みの汚染層は、前記適度
の硬度を有した先端部の尖った導電性バンプを押し当て
ると、導電性バンプの突き当たり面で汚染層を排除でき
る。この具体的な手段としては、個々の電子部品の搭載
時にもしくは全電子部品を搭載後に治具板など用いて一
括して、電極部の上から力を作用させることにより行わ
れる。
Further, in the mounting method of the present invention, when the electrodes of the electronic component and the conductive bumps of the wiring board are mounted by forming a connection having an interface resistance of substantially zero by the action of stress,
The application of the stress may be a force of about 0.5 to 20 N / bump, or the curing shrinkage of the uncured resin depending on the shape and material of the conductive bump. In other words, the electronic components to be mounted and mounted are usually a collection of products from different manufacturers, so the storage period is not constant and the types of electrode materials are different, so the types of oxide layers and organic substances that stain the surface are different. The thickness of the contaminated layer is generally on the order of submicrons, although the thickness thereof is various. With respect to the contaminated layer having such a thickness, the contaminated layer can be removed at the abutting surface of the conductive bump by pressing the conductive bump having the appropriate hardness and having the sharp tip. As a concrete means for this, when the individual electronic components are mounted or after all the electronic components are mounted, they are collectively applied by using a jig plate or the like, and a force is applied from above the electrode portions.

【0016】なお、本発明において、実装する電子部品
としては、セラミック材料から構成されるチップ型抵抗
体、コンデンサー、或いはフラットリード、ガルリング
型リード、Jリードなど各種の形状のリードあるICパ
ッケージ、コネクターなどの電子部品、また高密度実装
のために、希に使用されるベアICチップなどもが挙げ
られる。また、これら電子部品の電極は、貴金属製であ
ってよいし、一般的な材料である錫鉛系ハンダ材料、錫
メッキ仕上げ、ニッケルメッキ仕上げ、銅、アルミニュ
ーム薄膜などの材質で形成されていてもよい。
In the present invention, the electronic components to be mounted are chip type resistors and capacitors made of ceramic materials, or IC packages having various lead types such as flat leads, galling type leads and J leads, and connectors. Examples include electronic components such as, and bare IC chips that are rarely used for high-density mounting. The electrodes of these electronic components may be made of noble metal, and are made of a general material such as tin-lead solder material, tin-plated finish, nickel-plated finish, copper, aluminum thin film, etc. Good.

【0017】[0017]

【作用】上記本発明に係る実装用配線板においては、搭
載・実装する電子部品の電極に対応した導電性バンプが
未硬化な絶縁樹脂層に埋め込まれた形に設置されてお
り、また、前記導電性バンプは応力の作用によって薄い
酸化物層などを破壊して新しい金属面を露出させる機能
を呈する。したがって、位置合わせ後、応力を作用させ
ることにより、前記導電性バンプに対して、搭載・実装
する電子部品の電極を界面抵抗零の状態で電気的な接続
を達成する。しかも、前記未硬化な絶縁樹脂層が各接続
部を互いに絶縁離隔する一方、硬化するとその接続部な
どを外界から保護するとともに、実装電子部品と配線板
との一体・固定化を助長するので、信頼性の高い実装回
路装置を提供し得ることになる。
In the mounting wiring board according to the present invention described above, the conductive bumps corresponding to the electrodes of the electronic component to be mounted / mounted are installed in such a manner that they are embedded in the uncured insulating resin layer. The conductive bump has a function of breaking a thin oxide layer or the like to expose a new metal surface by the action of stress. Therefore, after the alignment, by applying a stress, the electrode of the electronic component to be mounted / mounted is electrically connected to the conductive bump in a state where the interface resistance is zero. Moreover, while the uncured insulating resin layer insulates and separates the respective connection portions from each other, while hardening the connection portions and the like from the outside world, it promotes the integration and fixing of the mounted electronic components and the wiring board. It is possible to provide a highly reliable mounted circuit device.

【0018】[0018]

【実施例】以下図1 (a), (b), (c)、図2 (a),
(b), (c)、および図3 (a), (b),(c)を参照して本発
明の実施例を説明する。
EXAMPLES Examples 1 (a), 1 (b), 1 (c), 2 (a),
An embodiment of the present invention will be described with reference to (b), (c), and FIGS. 3 (a), (b), (c).

【0019】実施例1 図1 (a)は、本発明に係る実装用配線板例を断面的に、
また図1 (b)は図1 (a)に図示した実装用配線板に電子
部品を実装する態様を模式的に示す断面図、図1 (c)は
図1 (b)に図示した実装する態様で応力を作用させて電
子部品を実装した後の状態を模式的に示す断面図であ
る。
Example 1 FIG. 1 (a) is a sectional view showing an example of a mounting wiring board according to the present invention.
Further, FIG. 1B is a sectional view schematically showing a mode of mounting electronic components on the mounting wiring board shown in FIG. 1A, and FIG. 1C is the mounting shown in FIG. 1B. It is sectional drawing which shows typically the state after mounting an electronic component by applying a stress in a mode.

【0020】先ず、図1 (a)において、1は両面型実装
用配線板本体、2aは前記両面型実装用配線板本体1の接
続パッドを成す銅パターン、2bは回路パターン、3は前
記接続パッド2形成面に一体的に積層配置された未硬化
状の絶縁性樹脂層、4は前記接続パッド2面に形成配置
された導電性バンプである。さらに具体的には、両面型
実装用配線板本体1は、ガラスクロス入りエポキシ樹脂
を基材とし、接続パッド2a,回路パターン2bの厚さが35
μm 、接続パッド2aの形状が 0.9× 1.2mm、導電性バン
プ4が高さ60μm の山形、未硬化状の絶縁性樹脂層3が
厚さ40μm の室温硬化型シリコーン樹脂層で、1608タイ
プの抵抗素子を搭載・実装可能な、全体の厚さが 1.0mm
の実装用配線板5である。
First, in FIG. 1 (a), 1 is a double-sided mounting wiring board body, 2a is a copper pattern forming a connection pad of the double-sided mounting wiring board body 1, 2b is a circuit pattern, and 3 is the connection. An uncured insulating resin layer 4 integrally laminated on the pad 2 formation surface is a conductive bump formed and arranged on the connection pad 2 surface. More specifically, the double-sided mounting wiring board main body 1 is made of epoxy resin containing glass cloth as a base material, and the thickness of the connection pads 2a and the circuit patterns 2b is 35.
μm, the shape of the connection pad 2a is 0.9 × 1.2 mm, the conductive bumps 4 are 60 μm in height, and the uncured insulating resin layer 3 is a room temperature curing type silicone resin layer with a thickness of 40 μm. The total thickness is 1.0 mm, which enables mounting and mounting of elements.
This is the mounting wiring board 5.

【0021】そして、前記構成の実装用配線板5は、次
のようにして製造し得る。すなわち、一般的な手段で製
造した両面型実装用配線板本体1を先ず用意し、接続パ
ッド2a形成面を回転式ブラシで研磨してから、水洗後空
冷乾燥した。次いで、手早く、板厚 300μm のアルミ板
の所定箇所に 0.3mm径の穴を明けたメタルマスクを用い
て、前記両面型実装用配線板本体1の接続パッド2a面上
に、前記メタルマスクの穴を位置決め配置して、ポリマ
ータイプの銀系の導電性ペーストを印刷し、高さ約60μ
m の山形の導電性パンブ4を形成(形設)した。その
後、 120℃で30分間加熱硬化し、粘着絶縁樹脂層(未硬
化状の絶縁樹脂層)3として室温硬化型シリコーン樹脂
(信越化学KK製,商品名, RTVゴム,KF3498)を40μ
m 厚さで塗布することにより製造した。
The mounting wiring board 5 having the above structure can be manufactured as follows. That is, the double-sided mounting wiring board main body 1 manufactured by a general means was first prepared, the surface on which the connection pads 2a were formed was polished with a rotary brush, then washed with water and air-cooled and dried. Then, quickly, using a metal mask with a hole of 0.3 mm diameter drilled at a predetermined location on an aluminum plate with a plate thickness of 300 μm, make a hole for the metal mask on the surface of the connection pad 2a of the double-sided mounting wiring board body 1. Position, place a polymer type silver-based conductive paste on it, and
A m-shaped chevron-shaped conductive bump 4 was formed (formed). After that, it is heat-cured at 120 ° C for 30 minutes and 40 μm of room-temperature curing type silicone resin (trade name, RTV rubber, KF3498 manufactured by Shin-Etsu Chemical KK) is used as an adhesive insulating resin layer (uncured insulating resin layer) 3.
Manufactured by applying m thickness.

【0022】前記構成の実装用配線板5に対する電子部
品6の実装、たとえばチップ形の抵抗素子の実装は、次
のように行われる。すなわち、前記実装用配線板5の導
電性パンブ4に、チップマウンターを用いて、図1 (b)
に示すごとく、前記チップ形の抵抗素子6の電極6a,6b
を対応させて位置決め配置する。この位置決め配置に当
たって、チップマウンターに瞬間的に 5.0 Nの加重を加
えたところ、図1 (c)に示したように、前記導電性バン
プ4の先端部が潰れた形になり、導電性バンプ4の高さ
は30μm に減じた。次いで、これを24時間室温下に放置
して、シリコーン樹脂3を硬化させた。
The mounting of the electronic component 6 on the mounting wiring board 5 having the above-described structure, for example, the mounting of the chip type resistance element is performed as follows. That is, a chip mounter is used for the conductive bumps 4 of the mounting wiring board 5 as shown in FIG.
As shown in, the electrodes 6a and 6b of the chip-shaped resistance element 6 are
Position and arrange in accordance with. In this positioning arrangement, when a load of 5.0 N was momentarily applied to the chip mounter, the tip of the conductive bump 4 was crushed as shown in FIG. Height was reduced to 30 μm. Then, this was left at room temperature for 24 hours to cure the silicone resin 3.

【0023】上記実装した実装回路において、チップ形
の抵抗素子6は抵抗素子として、電気的に十分な機能を
有し、熱衝撃試験(−65℃〜 125℃,1000h)、加熱試
験( 125℃,1000h)、耐湿試験(80℃,85%総耐湿
度,1000h)など加速信頼性試験にも問題はなかった。
In the mounted circuit mounted above, the chip-shaped resistance element 6 has an electrically sufficient function as a resistance element, and has a thermal shock test (-65 ° C. to 125 ° C., 1000 hours) and a heating test (125 ° C.). , 1000h), humidity resistance test (80 ° C, 85% total humidity resistance, 1000h) and other accelerated reliability tests did not cause any problems.

【0024】実施例2 図2 (a)は、本発明に係る他の実装用配線板例を断面的
に、また図2 (b)は図2 (a)に図示した実装用配線板に
電子部品を実装する態様を模式的に示す断面図、図2
(c)は図2 (b)に図示した実装する態様で応力を作用さ
せて電子部品を実装した後の状態を模式的に示す断面図
である。
Embodiment 2 FIG. 2 (a) is a cross-sectional view of another mounting wiring board example according to the present invention, and FIG. 2 (b) is an electronic circuit diagram of the mounting wiring board shown in FIG. 2 (a). FIG. 2 is a cross-sectional view schematically showing an aspect of mounting components.
2C is a cross-sectional view schematically showing a state after mounting the electronic component by applying stress in the mounting mode shown in FIG. 2B.

【0025】実施例1の場合に準じて、図2 (a)に断面
的に示すような、28ピンのリードを有するガルリングタ
イプのFPパッケージタイプのICメモリ6を実装し得る
導電性パンブ4を備えた構成の実装用配線板5を用意し
た。なお、前記実装用配線板5の接続パッド2aの形状
は、 0.8× 1.6mm角で、最小1.25mmピッチであり、また
導電性バンプ4は高さ約50μm の山形を成していた。そ
して、前記実装用配線板5面に、ICメモリ6のリード
6aを対応する導電性パンブ4と位置合わせ・配置し、図
2 (b)に断面的に示すごとく、リード6a,6bの平坦面に
20 Nの力を作用させ、導電性パンブ4の高さが約35μm
程度になるよう押圧して実装を行った。
In accordance with the case of the first embodiment, a conductive bump 4 capable of mounting a galling type FP package type IC memory 6 having a 28-pin lead as shown in a sectional view in FIG. A mounting wiring board 5 having a configuration was prepared. The shape of the connection pads 2a of the mounting wiring board 5 was 0.8 × 1.6 mm square with a minimum pitch of 1.25 mm, and the conductive bumps 4 were mountain-shaped with a height of about 50 μm. Then, on the surface of the mounting wiring board 5, the leads of the IC memory 6 are
Align 6a with the corresponding conductive bump 4 and place it on the flat surface of the leads 6a and 6b as shown in cross section in FIG. 2 (b).
Applying a force of 20 N, the height of the conductive bump 4 is approximately 35 μm.
The mounting was carried out by pressing so as to achieve a certain degree.

【0026】こうして構成した図2 (c)に断面的に示す
ような、ICメモリー実装回路装置は、電気的に十分な
機能を呈し、熱衝撃試験(−65℃〜 125℃,1000h)、
加熱試験( 125℃,1000h)、耐湿試験(80℃,85%総
耐湿度,1000h)など加速信頼性試験にも問題はなかっ
た。
The thus constructed IC memory mounted circuit device as shown in cross section in FIG. 2 (c) exhibits an electrically sufficient function, and is subjected to a thermal shock test (-65 ° C. to 125 ° C., 1000 h).
There were no problems in accelerated reliability tests such as heating tests (125 ° C, 1000h) and humidity resistance tests (80 ° C, 85% total humidity resistance, 1000h).

【0027】実施例3 先ず、基材がガラスクロス入りエポキシ樹脂からなる常
法により製造した厚みは 1.0mmで銅パターンの厚みは18
μm で、 100μm 角,最小ピッチ 150μm ,表面を薄い
ニッケル、金メッキで被覆した接続パッド2a群を備え
た、図3 (a)に断面的に示すような配線板を素材とし、
実施例1の場合に準じてメタルマスクを介して高さ約30
μm の山形状の導電性バンブ4を設け、かつその導電性
バンブ4形設置面に、未硬化状の絶縁性樹脂層3を設け
て成る実装用配線板5を用意した。一方、 100μm 角
で,約 1μm 厚,最小ピッチ 150μm のアルミニューム
薄膜製I/O端子を有するICメモリーチップ(チップ寸
法,15×10mm角)を電子部品として用意した。ここで、
実装用配線板5の導電性バンプ4は、平均粒径 0.5μm
の鱗片状銀粉とビスフェノールタイプのエポキシ樹脂と
から成る導電性ペーストを印刷し、 120℃で30分間加熱
硬化処理して形成し、また未硬化状の絶縁性樹脂層3
は、ソルダーレジスト(商品名.UVR-150R,太陽インキ
KK)を約30μm の厚さに塗布して形成した。
Example 3 First, the base material made of epoxy resin containing glass cloth was manufactured by a conventional method to have a thickness of 1.0 mm, and a copper pattern had a thickness of 18 mm.
The wiring board is 100 μm square, the minimum pitch is 150 μm, the surface is thin nickel, and the connection pads 2a group coated with gold plating are used.
According to the first embodiment, the height is about 30 through the metal mask.
A wiring board 5 for mounting was prepared in which a conductive bump 4 having a mountain shape of μm was provided, and an uncured insulating resin layer 3 was provided on the conductive bump 4 installation surface. On the other hand, an IC memory chip (chip size, 15 × 10 mm square) having 100 µm square, I / O terminals made of aluminum thin film with a thickness of about 1 µm and a minimum pitch of 150 µm was prepared as an electronic component. here,
The conductive bumps 4 of the mounting wiring board 5 have an average particle size of 0.5 μm.
Insulating resin layer 3 which is uncured by printing a conductive paste consisting of scaly silver powder and bisphenol type epoxy resin and heat curing at 120 ° C for 30 minutes
Is a solder resist (trade name. UVR-150R, Taiyo Ink
KK) to a thickness of about 30 μm.

【0028】前記実装用配線板5面にICメモリーチッ
プ6を、図3 (b)に断面的に示すごとく、相互の導電性
バンプ4および I/O端子6a,6bを位置合わせして搭載・
配置した後、ICメモリーチップ6の上から均一に加重
がかかるように、20 Nの加重をかけたところ、前記導電
性バンプ4の高さが15μm に減じ、これを紫外線照射炉
に収容し、未硬化状の絶縁性樹脂層3を硬化させ、さら
に 120℃で30分間加熱して完全硬化させて、図3 (c)に
断面的に示すような、実装回路装置を構成した。 上
記、構成した実装回路装置は、電気的に十分な機能を有
し、熱衝撃試験(−65℃〜 125℃,1000h)、加熱試験
( 125℃,1000h)、耐湿試験(80℃,85%総耐湿度,
1000h)など加速信頼性試験にも問題はなかった。
The IC memory chip 6 is mounted on the surface of the mounting wiring board 5 by aligning the conductive bumps 4 and the I / O terminals 6a and 6b with each other as shown in a sectional view in FIG. 3 (b).
After arranging, a weight of 20 N was applied so that the weight was evenly applied from above the IC memory chip 6, and the height of the conductive bump 4 was reduced to 15 μm, and this was placed in an ultraviolet irradiation furnace. The uncured insulating resin layer 3 was hardened and further heated at 120 ° C. for 30 minutes to be completely hardened to form a mounted circuit device as shown in a sectional view in FIG. 3C. The above-configured mounted circuit device has an electrically sufficient function, and has a thermal shock test (-65 ° C to 125 ° C, 1000h), a heating test (125 ° C, 1000h), and a humidity resistance test (80 ° C, 85%). Total humidity resistance,
There was no problem in the accelerated reliability test such as 1000h).

【0029】[0029]

【発明の効果】本発明に係る実装用配線板によれば、従
来電子部品の実装において提起しているハンダ接続によ
る問題を容易に回避し得る。具体的には、 (1)常温ない
し 100℃程度のプロセス温度で電子部品の実装・接続が
可能となり、高級な耐熱材料を配線板や電子部品にも使
わなくてもよくなる。 (2)前記のように低温での接続が
可能であるため、配線板と電子部品との熱膨張率の差に
よるストレスも小さく押さえられ、接続部の剥離などの
発生が抑制されて長期使用に耐えるようになる。(3)ハ
ンダ接続に使用するフラックスなど電気的に有害物を使
用しないですむので、環境上の問題も発生しない。 (4)
配線のピッチが微細になっても、導電性バンプを微細に
形成することにより、電子部品との確実な電気的な接合
が図られ、かつ隣接する接続部同士のパターンがブリッ
ジするという不具合も生じない。かくして、本発明に係
る実装用配線板、およびこの実装用配線板を用いる実装
方法は、実用上多くの利点をもたらすものといえる。
According to the mounting wiring board of the present invention, it is possible to easily avoid the problem due to the solder connection, which has been posed in the conventional mounting of electronic components. Specifically, (1) electronic components can be mounted and connected at room temperature to 100 ° C process temperature, and high-grade heat-resistant materials do not have to be used for wiring boards and electronic components. (2) Since it is possible to connect at low temperature as described above, the stress due to the difference in the coefficient of thermal expansion between the wiring board and the electronic component can be suppressed to a small level, and the occurrence of peeling of the connection part can be suppressed for long-term use. Will endure. (3) Since it is not necessary to use electrically harmful substances such as flux used for solder connection, environmental problems do not occur. (Four)
Even if the pitch of the wiring becomes fine, by forming the conductive bumps finely, reliable electrical connection with electronic components is achieved, and there is a problem that the pattern of adjacent connection parts bridges. Absent. Thus, it can be said that the mounting wiring board and the mounting method using the mounting wiring board according to the present invention bring many practical advantages.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る実装用配線板および実装方法を例
示するもので、 (a)は実装用配線板の断面図、 (b)はチ
ップ形電子部品の搭載した状態を模式的に示すの断面
図、(C) 電子部品を実装して形成した実装回路装置の断
面図。
FIG. 1 illustrates a mounting wiring board and a mounting method according to the present invention. (A) is a cross-sectional view of the mounting wiring board, and (b) is a schematic view showing a state in which a chip-type electronic component is mounted. 2C is a cross-sectional view of a mounted circuit device formed by mounting electronic components.

【図2】本発明に係る実装用配線板および実装方法の他
の例を示するもので、 (a)は実装用配線板の断面図、
(b)はリード付きICの搭載した状態を模式的に示すの
断面図、(C) 電子部品を実装して形成した実装回路装置
の断面図。
FIG. 2 shows another example of a mounting wiring board and a mounting method according to the present invention, in which (a) is a cross-sectional view of the mounting wiring board,
FIG. 2B is a cross-sectional view schematically showing a state in which an IC with leads is mounted, and FIG. 6C is a cross-sectional view of a mounted circuit device formed by mounting electronic components.

【図3】本発明に係る実装用配線板および実装方法のさ
らに他の例を示するもので、 (a)は実装用配線板の断面
図、 (b)はベアのチップICの搭載した状態を模式的に
示すの断面図、(C) 電子部品を実装して形成した実装回
路装置の断面図。
3A and 3B show still another example of a mounting wiring board and a mounting method according to the present invention, in which FIG. 3A is a sectional view of the mounting wiring board, and FIG. 3B is a state in which a bare chip IC is mounted. FIG. 3C is a schematic cross-sectional view of the mounting circuit device formed by mounting the electronic component.

【符号の説明】[Explanation of symbols]

1…両面型実装用配線板本体 2a…接続パッド 2b
…回路パターン 3…未硬化の絶縁性樹脂層 4…導電性バンプ 5
…実装用配線板 6…搭載・実装電子部品 6a,6b
…電極(端子) 7…潰れた導電性バンプ
1 ... Wiring board body for double-sided mounting 2a ... Connection pad 2b
... Circuit pattern 3 ... Unhardened insulating resin layer 4 ... Conductive bump 5
… Mounting wiring board 6… Mounting / mounting electronic components 6a, 6b
… Electrodes (terminals) 7… Crushed conductive bumps

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 搭載する電子部品の電極群に対応する接
続パッド群を少なくとも一主面に有する実装用配線板で
あって、 前記実装用配線板面の接続パッド群がそれぞれ導電性バ
ンプを備え、かつ導電性バンプ群を備えた面の少なくと
も一部が未硬化状の絶縁樹脂層で被覆されて成ることを
特徴とする実装用配線板
1. A mounting wiring board having a connection pad group corresponding to an electrode group of an electronic component to be mounted on at least one main surface, wherein each connection pad group on the mounting wiring board surface includes a conductive bump. And a mounting wiring board characterized in that at least a part of the surface provided with the conductive bump group is covered with an uncured insulating resin layer.
【請求項2】少なくとも一主面に導電性バンプを備えた
接続パッド群が形成され、かつ導電性バンプ群を備えた
面の少なくともが未硬化状の絶縁樹脂層で被覆されて成
る配線板面上に、前記導電性バンプ群に対応する電極群
を有する電子部品を位置合わせして搭載・配置する工程
と、 前記位置合わせした配線板の導電性バンプ群および電子
部品の電極群の間にそれぞれ応力が作用するように電子
部品を実装する工程と、 前記配線板面の絶縁樹脂層を硬化する工程とを具備して
成ることを特徴とする実装方法。
2. A surface of a wiring board in which a connection pad group having conductive bumps is formed on at least one main surface, and at least the surface having conductive bump groups is covered with an uncured insulating resin layer. Above, a step of aligning and mounting an electronic component having an electrode group corresponding to the conductive bump group, and between the conductive bump group of the aligned wiring board and the electrode group of the electronic component respectively. A mounting method comprising a step of mounting an electronic component so that a stress acts, and a step of curing an insulating resin layer on the surface of the wiring board.
JP32437193A 1993-12-22 1993-12-22 Wiring board for mounting and mounting method using the same Expired - Fee Related JP3560996B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32437193A JP3560996B2 (en) 1993-12-22 1993-12-22 Wiring board for mounting and mounting method using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32437193A JP3560996B2 (en) 1993-12-22 1993-12-22 Wiring board for mounting and mounting method using the same

Publications (2)

Publication Number Publication Date
JPH07183646A true JPH07183646A (en) 1995-07-21
JP3560996B2 JP3560996B2 (en) 2004-09-02

Family

ID=18165046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32437193A Expired - Fee Related JP3560996B2 (en) 1993-12-22 1993-12-22 Wiring board for mounting and mounting method using the same

Country Status (1)

Country Link
JP (1) JP3560996B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000007419A1 (en) * 1998-07-29 2000-02-10 Sony Chemicals Corp. Production method for flexible substrate
JP2000216522A (en) * 1999-01-20 2000-08-04 Sony Chem Corp Flexible board and manufacture thereof
US6930390B2 (en) 1999-01-20 2005-08-16 Sony Chemicals Corp. Flexible printed wiring boards
JP2007266451A (en) * 2006-03-29 2007-10-11 Nippon Steel Chem Co Ltd Method of manufacturing semiconductor device provided with bump
KR100811034B1 (en) * 2007-04-30 2008-03-06 삼성전기주식회사 Method for manufacturing printed circuit board having embedded electronic components
JP2008091933A (en) 1995-11-17 2008-04-17 Dainippon Printing Co Ltd Electronic component
CN104619126A (en) * 2015-01-14 2015-05-13 吴盛龙 Circuit board locating device of LED chip mounter and mounting method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091933A (en) 1995-11-17 2008-04-17 Dainippon Printing Co Ltd Electronic component
WO2000007419A1 (en) * 1998-07-29 2000-02-10 Sony Chemicals Corp. Production method for flexible substrate
JP2000106482A (en) * 1998-07-29 2000-04-11 Sony Chem Corp Manufacture of flexible board
US6643923B1 (en) 1998-07-29 2003-11-11 Sony Chemicals Corp. Processes for manufacturing flexible wiring boards
US6848176B2 (en) 1998-07-29 2005-02-01 Sony Chemicals Corporation Process for manufacturing flexible wiring boards
US7053312B2 (en) 1998-07-29 2006-05-30 Sony Corporation Flexible wiring boards
JP2000216522A (en) * 1999-01-20 2000-08-04 Sony Chem Corp Flexible board and manufacture thereof
US6930390B2 (en) 1999-01-20 2005-08-16 Sony Chemicals Corp. Flexible printed wiring boards
JP2007266451A (en) * 2006-03-29 2007-10-11 Nippon Steel Chem Co Ltd Method of manufacturing semiconductor device provided with bump
KR100811034B1 (en) * 2007-04-30 2008-03-06 삼성전기주식회사 Method for manufacturing printed circuit board having embedded electronic components
CN104619126A (en) * 2015-01-14 2015-05-13 吴盛龙 Circuit board locating device of LED chip mounter and mounting method thereof

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