JPH071636B2 - Conversion buffer device - Google Patents

Description

The present invention relates to an associative memory (Content Ad) having a match detection function.
conversion buffer that uses dressable memory (CAN).

2. Description of the Related Art In the conventional conversion buffer, the search completion of CAM1 is transmitted to RAM2 by using the external clock 18 as shown in FIG. That is, when the search of CAM1 seems to be completed, the RAM access enable 17 is output from the clock synchronous EOS circuit 4,
This made the gate 19 conductive and connected the lines 10 and 12.

Problems to be Solved by the Invention In this method, the timing of outputting the RAM access enable is controlled by the clock. The output timing must be set after the CAM search is completed, and the synchronous clock requires a sufficient margin. Therefore, it took a wasteful time from the end of CAM search to the start of RAM access. The address translation buffer is an important technique for supporting virtual memory, and its speed is desired. The present invention provides a new method for solving the above problems of the conventional one, and an object thereof is to access the RAM at high speed after the completion of the search operation of the CAM is guaranteed. It is to provide a conversion buffer device.

Means for Solving the Problems The conversion buffer device of the present invention includes a sense line of an associative memory having a match detection function for storing data before conversion,
The word line of the random access memory that stores the converted data is connected through the gate, and the asynchronous match detection end signal generation circuit is provided in the associative memory, and the output controls the conduction of the gate. It is composed.

Action In the present invention as described above, high-speed conversion can be performed because the signal is transmitted from the CAM to the RAM asynchronously with the external clock by using the CAM.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In the conversion buffer device of this embodiment, as shown in FIG.
Asynchronous match detection end signal generation circuit 3 (hereinafter EOS
Circuit). The RAM access enable 17 is output very slightly after the time when the latest search in CAM1 ends. This makes the gate 19 conductive and the access to the RAM2 is started. Therefore, the transmission from the CAM to the RAM is performed without waste of time.

The operation will be described with reference to FIGS. 2a, 2b and 3 which are embodiments of the present invention. FIG. 3 is an overall configuration diagram of the apparatus, and FIGS. 2A and 2B are enlarged views of a part of the apparatus to describe the circuit in the cell.

The sense line 10 is kept high when the input data and the stored data match by the precharge method. This drives the RAM word line 12 and reads the data stored therein. In case of a mismatch, the sense line 10 is discharged by all the CAM cells of the mismatched bits in the word. On the other hand, EOS line 11 has only one asynchronous EOS circuit 3
It is discharged only by. Where EOS line 11 has an E
In addition to the OS circuit 3, the dummy cell 23 is connected to the CAM bit number minus one and has the same load capacitance as the sense line 10. CA
When a search is begun in M, EOS line 11 will always go low because either bitline 13, 14 is high. The slowest word line that goes low is only discharged by one CAM cell, but EOS line 11
Discharge of 1 Nch transistor of EOS circuit 3
Since it is done only at 20, all words have been searched when EOS line 11 falls to Low. To be exact, EOS
Discharge on line 11 and slowest sense line 10
Are discharged at the same timing. So EOS
After delaying the line by the two-stage inverter 22, the RAM 19 is used as the RAM access enable 8 for conducting the gate 19. Here, although the two-stage inverter 22 is not essential, using it increases the margin in the actual circuit and further improves the reliability.

In FIG. 3, a virtual address is stored in CAM1 and a physical address is stored in RAM2. Address is 32 bits, CAM1 and RAM2 are each 1 word 20 to 23 bits depending on page size
Take composition. That is, 20 to 23 CAM cells 5 and RAM cells 6 are arranged in the word direction. 32 to 64 rows are arranged in the depth direction according to the number of entries. CAM sense line 10
Is connected to the word line 12 of the RAM via an inverter 21 and a gate 19. Also, the EOS line 11 is connected to the gate 19 after passing through the inverter 22 for two stages due to delay. EO
One EOS circuit and one-bit dummy cell are connected to the S line. Also, all the NOs in word line 12 of RAM2
By taking R, the disagreement signal 7 is generated. This is C
Indicates that the virtual address entered in AM1 is not stored.

In the present embodiment, a cell may be configured by adjusting the delay of the inverter 22 by setting a cell for detecting a mismatch as n bits and a cell for detecting a match as (bit number-n) bits.

As described above, the conversion buffer device of the present invention is
Since M is used, full associative search can be performed at high speed. High-speed conversion is possible because the signal transmission from CAM to RAM is asynchronous with the external clock. With the development of microprocessors, virtual memory support is an important issue, and the present invention is very useful in realizing high speed address translation.

[Brief description of drawings]

FIG. 1 is a block diagram of an address conversion buffer device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of the device of this embodiment, FIG. 3 is a block diagram of the entire device, and FIG. FIG. 1 is a block diagram of a conventional address translation buffer device. 1 ... CAM, 2 ... RAM, 3 ... Asynchronous EOS circuit, 4 ...
… Synchronous EOS circuit, 5 …… CAM cell, 6 …… RAM cell, 7
...... Inconsistency signal, 8 ... RAM access enable, 9 ...
… CAM word line, 10 …… sense line, 11 …… EOS line, 12 …… RAM word line, 13,15 …… bit line, 14,16 …… bit line, 17 …… RAM access enable, 18 …… External clock, 19 ... Gate, 20 ... Nch
Transistors, 21, 22 ... Inverters, 23 ... Dummy cells.

Claims (2)

[Claims] 1. A sense line of an associative memory having a coincidence detecting function for storing data before conversion and a word line of a random access memory for storing data after conversion are connected through a gate, and the sense line is stored in the associative memory. A conversion buffer device provided with an asynchronous match detection end signal generation circuit, and the output of which controls the conduction of the gate. 2. An associative detection end signal generation circuit is an additional circuit for one word, which is composed of a 1-bit cell that always detects a mismatch and a cell that is 1 bit less than the number of words that always detects a match in the associative memory. The conversion buffer device according to claim 1, wherein the mismatch signal generated here is used as a match detection end signal.