JPH0712588A - Encoder frequency divider - Google Patents

Abstract

PURPOSE:To prevent a positional error by making a frequency dividing interval uniform. CONSTITUTION:A counter 2 is incrementally or decrementally counted according to a code C and a pulse D identified by a code identifier 1 from output pulses A, B of an encoder. A multiplier 3 multiplies an output counted value of the counter 2 by a frequency dividing ratio E. An adder 4 adds, if an output multiplied value of the multiplier 3 has a fraction of a decimal point or less, an offset value N of 0<N<1 to the fraction, and if the value after the addition is 1 or more, '1' is added to an integer value of an output value of the multiplier 3 and the sum is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code discriminating circuit which receives a two-phase pulse output from a rotary encoder and converts it into a code and a pulse value, and a pulse value output from the code discriminating circuit is counted up / up by the code. The present invention relates to an encoder frequency divider circuit of a servo control device, which comprises a counter that counts down and outputs, and divides a count value output from the counter by a frequency division ratio.

[0002]

2. Description of the Related Art Conventionally, this kind of encoder frequency dividing circuit
As shown in FIG. 2 as an example, first, the output pulses A and B from the encoder are divided into a code C and a pulse number D by the code determination circuit 1. Then, the pulse number D is counted up / down by the code C by the counter 2. According to the count value of the number of pulses, the count up / down selection circuit 5 performs pulse conversion by the frequency division ratio E and frequency division.
As the count up / down selection circuit 5, BRM (Bi
nary Rate Multiplier) is used.

[0003]

In the above-mentioned conventional encoder frequency dividing circuit, since the frequency division is performed by the BRM as the pattern of the frequency division ratio, the frequency division intervals corresponding to the constant number of pulses output from the encoder are not always equal. However, there is a drawback that a position error will occur if the servo controller performs positioning or the like. An object of the present invention is to provide an encoder frequency dividing circuit that can obtain frequency division intervals evenly and does not cause a position error due to positioning or the like in servo control.

[0004]

SUMMARY OF THE INVENTION An encoder frequency dividing circuit according to the present invention comprises a multiplier for multiplying a count value output by a counter by a frequency division ratio, and outputting the multiplied value. When it has, it has the adder which adds the offset value N which is 1>N> 0 to the fractional value, and adds 1 to the integer value of the output value and outputs it when the summed value is 1 or more.

[0005]

The offset value is added to the fractional value of the output value of the multiplier, and if it is 1 or more, 1 is added to the integer value. Therefore, the fractional value is reflected in the addition value, and the frequency division intervals can be equalized. Positional errors in control are eliminated.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a configuration block diagram of an embodiment of an encoder frequency dividing circuit according to the present invention. The encoder frequency dividing circuit is composed of a code discriminating circuit 1, a counter 2, a multiplier 3 and an adder 4. The code discriminating circuit 1 receives the pulses A and B output from an encoder (not shown), divides them into a code C and a pulse D, and outputs them. The counter 2 counts up / down the pulse number of the pulse D by the code C.
The multiplier 3 receives the count value of the counter 2 and the frequency division ratio E, multiplies them, and outputs the result. The adder 4 adds the offset value N to the fractional part below the decimal point of the output value (count value × frequency division ratio) of the multiplier 3 and if the summed value (fractional number + N) is 1 or more, the output value 1 is added to the integer value and output as a count-up / count-down pulse. That is,
For example, when the frequency division ratio E is 20000/32768 pulses and the offset value is N = 16384/32768 pulses, and one pulse is input from the encoder, 1 × E + N = 1 × 20000/32768 + 16384
/ 32768 = 0.61 + 0.5 = 1.11 and the fractional value after the decimal point is 0.61, so the fractional value +
Since the offset value = 1.11 is a value greater than or equal to 1, 1 is output, and when 2 pulses are input, 2 × E + N = 1 × 20000/32768 + 16384
/ 32768 = 1.22 + 0.5 = 1.72, and fractional value + offset value = 0.22 + 0.5 =
Since it is 0.72, the integer value 1 is output as it is.

After 3 pulses or less, such processing is performed and the count up / down pulse is output. The output count-up / down pulse is converted into an encoder pulse form of a two-phase pulse of A and B phases, and frequency division is completed.
In this frequency divider circuit, when the pulse count value output from the counter is multiplied by the frequency division ratio, if the value obtained by adding the offset value without ignoring the fraction is 1 or more, 1 is added to the integer value to count up. Since / down pulse value is used, uneven frequency division intervals do not occur. In the encoder frequency dividing circuit of the present embodiment, since the offset value is added to the fractional value of the multiplication value of the pulse value and the frequency division ratio and reflected in the integer value, there is no influence by ignoring the fractional number and the division error is reduced. .

[0008]

As described above, according to the present invention, by adding the offset value to the fraction of the multiplication value and reflecting the result in the integer value, it is possible to minimize the frequency division error due to the fraction being ignored. As a result, there is no unevenness in frequency division intervals in servo control, and position detection errors can be prevented.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of an encoder frequency dividing circuit of the present invention.

FIG. 2 is a configuration block diagram of a conventional example of an encoder frequency dividing circuit.

[Explanation of symbols]

 1 Sign Discrimination Circuit 2 Counter 3 Multiplier 4 Adder A, B Output Pulse C Code D Pulse E Frequency Division Ratio N Offset Value

Claims (1)

[Claims] 1. A code discriminating circuit for inputting a two-phase pulse output from a rotary encoder and converting it into a code and a pulse value, and a pulse value output by the code discriminating circuit is up / down counted by the code and output. A counter for dividing the count value output from the counter by a division ratio, and a multiplier for multiplying the count value by the division ratio and outputting the same; When the output value of the instrument has a fractional part,
An encoder having an adder that adds an offset value N of 1>N> 0 to the fractional value and adds 1 to the integer value of the output value to output if the summed value is 1 or more. Divider circuit.