JPH07122827A - Substrate for mounting electronic part - Google Patents

Substrate for mounting electronic part

Info

Publication number
JPH07122827A
JPH07122827A JP29126593A JP29126593A JPH07122827A JP H07122827 A JPH07122827 A JP H07122827A JP 29126593 A JP29126593 A JP 29126593A JP 29126593 A JP29126593 A JP 29126593A JP H07122827 A JPH07122827 A JP H07122827A
Authority
JP
Japan
Prior art keywords
substrate
sealing resin
electronic component
semiconductor chip
electronic part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29126593A
Other languages
Japanese (ja)
Inventor
Natsuya Ishikawa
夏也 石川
Original Assignee
Sony Corp
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, ソニー株式会社 filed Critical Sony Corp
Priority to JP29126593A priority Critical patent/JPH07122827A/en
Publication of JPH07122827A publication Critical patent/JPH07122827A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Abstract

PURPOSE: To fill a section between an electronic part and a base material positively with a sealing resin in a substrate for mounting the electronic part, in which a lead is formed onto the surface of a base material and the specified electronic part is mounted on the lead while the section between the electronic part and the base material is filled with the sealing resin.
CONSTITUTION: A recessed-shaped guide groove 25 is formed in a region, in which an electronic part is mounted on the surface of a base material 22, thus positively filling a section between the electronic part and the base material 2 with a sealing resin 7 sealing the section between the electronic part and the base material 22.
COPYRIGHT: (C)1995,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は電子部品実装用基板に関し、特に電子部品及び基板間に封止用の樹脂を挿入するようになされた電子部品実装用基板に適用して好適なものである。 The present invention relates to an electronic component mounting substrate, more particularly, suitably applied to an electronic component mounting board adapted to insert a resin for sealing between the electronic component and the substrate .

【0002】 [0002]

【従来の技術】従来、半導体チツプ等の電子部品をフリツプチツプ実装方式によつて電子部品実装用基板上に実装したものとして図6に示すような構成のものがある。 Conventionally, there is constituted as shown in FIG. 6 the electronic components such as semiconductor chips as an implementation of the I connexion electronic component mounting board to flip chip mounting method.
すなわち図6(A)において電子部品実装用基板1はエポキシ又はフエノール樹脂でなる基材2上に銅パターン層でなるリード3が形成され、当該リード3上にはんだバンプ4を介して半導体チツプ5が熱溶着されている。 That electronic component mounting board 1 in FIG. 6 (A) is lead 3 made of a copper pattern layer on a substrate 2 made of an epoxy or phenolic resin is formed, the semiconductor chip 5 through the bump 4 solder on the lead 3 There has been heat-welded.

【0003】この半導体チツプ5及び基材2間に封止用樹脂7を挿入することにより、半導体チツプ5及び基材2の熱膨張率の違いによるはんだバンプ4の切断又は半導体チツプ5のクラツク等を未然に防止するようになされている。 [0003] By inserting the sealing resin 7 between the semiconductor chip 5 and the substrate 2, the semiconductor chip 5 and Kuratsuku like cutting or semiconductor chip 5 of the solder bumps 4 due to a difference in thermal expansion coefficients of the substrate 2 It is adapted to prevent the.

【0004】 [0004]

【発明が解決しようとする課題】ところでかかる構成の電子部品実装用基板1においては、半導体チツプ5及び基材2間のギヤツプはリード3及びはんだバンプ4の高さを合計した微小な高さであり、この間に封止用樹脂7 In [0005] Incidentally electronic component mounting board 1 having such a configuration, the semiconductor chip 5 and Giyatsupu between the substrate 2 in a very small height which is the sum of the height of the lead 3 and the solder bumps 4 Yes, the sealing resin 7 during this time
を挿入しようとしても当該ギヤツプ内に封止用樹脂7が十分に入らず、例えば図6(B)に示すように半導体チツプ5及び基材2間に予め存在していた空気によつて封止用樹脂7に空間(ボイド)8が残る。 Even without entering the sealing resin 7 well within the Giyatsupu attempting to insert, for example a semiconductor chip 5 and by connexion seal air that had previously existed between the substrate 2 as shown in FIG. 6 (B) space (voids) 8 to use the resin 7 remains.

【0005】この結果半導体チツプ5の発熱等によつてボイド8内の空気が膨張及び収縮し、これに伴つて封止用樹脂7及びはんだバンプ4にクラツク又は切断等の不良が発生する問題があつた。 A problem which results air heat generation due connexion voids within 8 to the semiconductor chip 5 is expanded and contracted, this accompanied connexion to the sealing resin 7 and the solder bumps 4 of Kuratsuku or cutting such defects occur is Atsuta.

【0006】また封止用樹脂7を半導体チツプ5及び基材2間に挿入する場合、当該封止用樹脂7を基材2の半導体チツプ5が実装された周囲に滴下することになるが、このとき図7に示すように半導体チツプ5及び基材2間のギヤツプからはみ出した封止用樹脂7が基材2に実装された他の電子部品9に付着し、当該電子部品9を交換することが困難になる問題があつた。 [0006] When inserting the sealing resin 7 between the semiconductor chip 5 and the substrate 2, but will be dropped the sealing resin 7 around the semiconductor chip 5 of the substrate 2 is mounted, at this time attached to other electronic components 9 in which the semiconductor chip 5 and the sealing resin 7 protruding from Giyatsupu between the substrate 2 is mounted on the substrate 2 as shown in FIG. 7, to replace the electronic component 9 that problem has been made that difficult.

【0007】本発明は以上の点を考慮してなされたもので、電子部品及び基材間に封止用樹脂を確実に充填し得る電子部品実装用基板を提案しようとするものである。 [0007] The present invention has been made in view of the above, it is intended to propose a substrate for electronic component mounting which can reliably fill the sealing resin between the electronic component and the substrate.

【0008】 [0008]

【課題を解決するための手段】かかる課題を解決するため本発明においては、基材22表面にリード3を形成し、リード3に所定の電子部品5を実装すると共に、電子部品5及び基材22間に封止用樹脂7を充填する電子部品実装用基板20において、基材22表面の電子部品5を実装する領域に凹状の溝25を形成する。 In the present invention for solving the Means for Solving the Problems] Such problems lead 3 is formed on the substrate 22 surface, as well as implementing a predetermined electronic component 5 to the lead 3, the electronic component 5 and the base in the electronic component mounting substrate 20 to fill the sealing resin 7 between 22 to form a concave groove 25 in a region for mounting electronic components 5 of the substrate 22 surface.

【0009】また本発明においては、凹状の溝25は、 [0009] In the present invention, the concave groove 25,
基材22表面の電子部品5を実装する領域よりも外側から実装領域の内部に亘つて形成されるようにする。 Than the region for mounting electronic components 5 of the substrate 22 surface to be Wataru connexion formed inside of the mounting region from the outside.

【0010】 [0010]

【作用】基材22の表面に形成されたガイド溝25に封止用樹脂7を滴下することにより、当該ガイド溝25に沿つて封止用樹脂7が電子部品5及び基材22間に流入し、当該電子部品5及び基材22間に確実に充填される。 [Action] by dropwise addition of sealing resin 7 to the guide groove 25 formed on the surface of the substrate 22, flows along connexion sealing resin 7 to the guide groove 25 between the electronic component 5 and substrate 22 and it is reliably filled between the electronic component 5 and substrate 22.

【0011】 [0011]

【実施例】以下図面について、本発明の一実施例を詳述する。 For EXAMPLES be described with reference to the accompanying drawings an embodiment of the present invention.

【0012】図6との対応部分に同一符号を付して示す図1において基材22の表面には半導体チツプ5が実装される領域の周辺部から当該領域のほぼ中心に向かつて傾斜したガイド溝25が形成されている。 [0012] the corresponding parts on the surface of the substrate 22 in FIG. 1 are denoted by the same reference numerals with FIG. 6 is inclined One unsuitable from the periphery of the region where the semiconductor chip 5 is mounted approximately in the center of the area guides groove 25 is formed. このガイド溝25は例えば凸形状の金型を用いたプレス成型によつて形成される。 The guide groove 25 is by connexion formed in the press molding using a mold, for example a convex shape.

【0013】このような形状のガイド溝25が形成された基材22にはんだバンプ4を介して半導体チツプ5を実装すると、ガイド溝25の先端部25Aが半導体チツプ5の実装領域から外部に突出した状態となる(図1 [0013] Upon mounting the semiconductor chip 5 through the bump 4 solder substrate 22 such a shape of the guide groove 25 is formed, the distal end portion 25A of the guide groove 25 projects outward from the mounting region of the semiconductor chip 5 the state (Fig. 1
(A))。 (A)).

【0014】この突出したガイド溝25の先端部25A [0014] distal end portion 25A of the projecting guide groove 25
を封止用樹脂の滴下部として当該滴下部25Aに封止用樹脂7を滴下すると、図1(B)に示すようにガイド溝25が当該滴下部25Aから半導体チツプ実装領域の中心部に向かつて傾斜していることにより、当該ガイド溝25に沿つて封止用樹脂7が半導体チツプ5及び基材2 When the dropwise addition of sealing resin 7 to the dropping portion 25A as dropping of the sealing resin, in the center of the semiconductor chip mounting area from the guide groove 25 is the dropping portion 25A as shown in FIG. 1 (B) direction by being once inclined, the guide groove 25 in along connexion sealing resin 7 in the semiconductor chip 5 and the substrate 2
2間に流入する。 It flows into between the two.

【0015】このとき当該ガイド溝25が形成されていることにより、半導体チツプ5及び基材22間のギヤツプが広くなり、封止用樹脂7が一段と容易に当該ギヤツプ内に流れ込むことになる。 [0015] By this time the guide groove 25 is formed, the semiconductor chip 5 and Giyatsupu between the substrate 22 is widened, so that the sealing resin 7 flows into the more readily within the Giyatsupu.

【0016】以上の構成において、図2に示すようにガイド溝25の先端部の滴下部25Aに滴下された封止用樹脂7は、ガイド溝25の傾斜及び、当該ガイド溝25 [0016] In the above configuration, the sealing resin 7 dripped to the dropping portion 25A of the distal portion of the guide groove 25 as shown in FIG. 2, the inclination of the guide groove 25 and, the guide groove 25
が形成されることによつて拡がつた半導体チツプ5及び基材22間のギヤツプによつて当該ギヤツプ内に容易に流れ込む。 There easily flow into by connexion within the Giyatsupu to Giyatsupu between the semiconductor chip 5 and the substrate 22 One Hiroga by connexion to be formed.

【0017】この結果、半導体チツプ5及び基材22間に予め存在する空気によるボイド8(図6)が半導体チツプ5及び基材22間のギヤツプから外部に抜け出し、 [0017] As a result, it voids 8 by the air pre-existing between the semiconductor chip 5 and the substrate 22 (FIG. 6) exits to the outside from Giyatsupu between the semiconductor chip 5 and the substrate 22,
当該ギヤツプ内には封止用樹脂7が充填される。 The within the Giyatsupu sealing resin 7 is filled.

【0018】このとき、滴下部25Aに滴下された封止用樹脂7はガイド溝25に沿つて流れ込むことにより、 [0018] At this time, the sealing resin 7 dripped to a dropping portion 25A is by flowing along connexion with the guide groove 25,
半導体チツプ5の周囲に容易に流れ出さず、これにより半導体チツプ5の周囲に実装された他の電子部品に封止用樹脂7が付着することを有効に回避し得る。 Not easily flow out around the semiconductor chip 5, thereby sealing resin 7 to the other electronic components mounted on the periphery of the semiconductor chip 5 can be effectively prevented from adhering.

【0019】以上の構成によれば、基材22の表面の半導体チツプ実装領域にガイド溝25を形成したことにより、一段と確実に封止用樹脂7を半導体チツプ5及び基材22間のギヤツプに充填することができる。 According to the above configuration, by forming the guide groove 25 in the semiconductor chip mounting area of ​​the surface of the substrate 22, to further ensure the sealing resin 7 to Giyatsupu between the semiconductor chip 5 and the substrate 22 it can be filled.

【0020】なお上述の実施例においては、半導体チツプ5の実装領域の周囲から当該領域の中心までガイド溝25を形成した場合について述べたが、本発明はこれに限らず、例えば図3(A)に示すように基材32において半導体チツプ5の実装領域の周囲にガイド溝35の封止用樹脂7の滴下部35Aを形成し、当該低下部35A [0020] Note that in the embodiment described above has dealt with the case of forming the guide groove 25 from the periphery of the mounting region of the semiconductor chip 5 to the center of the region, the present invention is not limited to this, for example, FIG. 3 (A the dropping portion 35A of the sealing resin 7 of the guide groove 35 formed around the mounting area of ​​the semiconductor chip 5 in the substrate 32 as shown in), the reduction unit 35A
から半導体チツプ5の実装領域の中心部に向かつてガイド溝35を形成すると共に、当該ガイド溝35を半導体チツプ5の実装領域の中心部からさらに上記滴下部35 The semiconductor chip One suited in the center of the mounting region of 5 to form the guide groove 35, the guide grooves 35 further said dropping portion 35 from the center of the mounting region of the semiconductor chip 5 from
Aに対して対向する位置(半導体チツプ実装領域の周囲)に突出するボイド排出部35Bを形成するようにしても良い。 Position opposing against A may be formed a void discharge section 35B that protrudes (semiconductor chip around the mounting region).

【0021】ここで図3(B)は図3(A)のA−A´ [0021] A-A'here FIG. 3 (B) FIG. 3 (A)
線を断面にとつて示す断面図であり、ガイド溝35は滴下部35Aからボイド排出部35Bに向かつて傾斜してなり、滴下部35Aに滴下された封止用樹脂7は当該傾斜によつてボイド排出部35Bまで流れ込むことにより、半導体チツプ5及び基材32間に存在していた空気は封止用樹脂7の流入によつてボイド排出部35Bからギヤツプの外部に確実に排出される。 Is a sectional view showing connexion with a line cross-section, the guide groove 35 becomes inclined with One unsuitable from a dropping portion 35A to the void discharge section 35B, the sealing resin 7 dripped to a dropping unit 35A Yotsute to the inclined by flowing to the void discharge section 35B, air present between the semiconductor chip 5 and the substrate 32 is reliably discharged to the outside of Giyatsupu from O connexion void discharge section 35B to the inflow of the sealing resin 7.

【0022】この結果半導体チツプ5及び基材32間にはボイドのない封止用樹脂7が充填される。 [0022] As a result the semiconductor chip 5 and the sealing resin 7 with no void between the substrate 32 is filled.

【0023】また図3の実施例においては、滴下部35 [0023] In the embodiment of Figure 3, dropping portion 35
Aからボイド排出部35Bに向かつて傾斜したガイド溝35を形成した場合について述べたが、本発明はこれに限らず、例えば図4(B)に示すように滴下部45A及びボイド排出部45Bに比して、半導体チツプ5の実装領域の中心部において最も深く湾曲形成されたガイド溝45を形成するようにしても良い。 It has dealt with the case of forming the guide groove 35 is inclined One unsuitable from A to void discharge section 35B, the present invention is not limited to this, for example, dropping portion 45A and void discharge portion 45B as shown in FIG. 4 (B) compared to, it may be formed a guide groove 45 which is most deeply curved at the center of the mounting region of the semiconductor chip 5.

【0024】このようにすれば封止用樹脂7が半導体チツプ実装領域の中心部において溜まり易くなる。 The sealing resin 7 Thus tends accumulate at the center of the semiconductor chip mounting region. 因に図4(A)はガイド溝45を有する電子部品実装用基板4 4 to cause (A) is an electronic component mounting substrate 4 having a guide groove 45
0の平面図である。 0 is a plan view of the.

【0025】また上述の実施例においては、1方向に形成されたガイド溝25(図1)、35(図3)及び45 [0025] In the above embodiment, formed in one direction the guide groove 25 (FIG. 1), 35 (FIG. 3) and 45
(図4)について述べたが、本発明はこれに限らず、例えば図5(A)に示すように、基材52において半導体チツプ5の実装領域のほぼ中心で交差する十字形状のガイド溝55を形成するようにしても良い。 Has been described (FIG. 4), the present invention is not limited to this, for example, FIG. 5 (A), a cross-shaped guide groove 55 that intersect at approximately the center of the mounting area of ​​the semiconductor chip 5 in the base member 52 it may be formed a.

【0026】このようにすれば、封止用樹脂7の滴下部55Aから封止用樹脂7を流入させた際、3つのボイド排出部55B、55C及び55Dからボイドを排出することができ、半導体チツプ5及び基材52間のギヤツプに確実に封止用樹脂7を充填することができる。 [0026] In this way, when allowed to flow into the sealing resin 7 from the dropping portion 55A of the sealing resin 7, three void discharge section 55B, it is possible to discharge the void from 55C and 55D, the semiconductor the Giyatsupu between chips 5 and substrate 52 can be reliably filled with the sealing resin 7.

【0027】またこの場合、十字形状に形成されたガイド溝55の2つの端部(55A、55B)を封止用樹脂7の滴下部とすることにより、2箇所から封止用樹脂7 Further in this case, by two end portions of the guide groove 55 formed in a cross shape (55A, 55B) and dropped portion of the sealing resin 7, the sealing resin from two places 7
を流入させることができ、この分封止用樹脂7の充填工程に要する時間を短時間化することができる。 The can be made to flow, it is possible to short the time required for filling step of the swarming sealing resin 7. 因に図5 Figure to cause 5
(B)は図5(A)のA−A´線を断面にとつて示す断面図である。 (B) is a sectional view showing connexion with the cross section A-A'line in FIG. 5 (A).

【0028】また上述の実施例においては、凸形状の金型を用いてガイド溝25、35、45及び55を形成する場合について述べたが、本発明はこれに限らず、例えばルータを用いて削りとつたり、又はアデイテイブ法を用いたプリント配線基板を基材とした場合には最外層のレジストのパターンを凹形状にパターンニングしてガイド溝を形成するようにしても良い。 Further in the embodiment described above has dealt with the case of forming the guide grooves 25, 35, 45 and 55 using a mold having a convex shape, the present invention is not limited to this, for example using a router or convex shaving, or may be formed a guide groove by patterning the pattern of the outermost layer of resist to a concave shape when the printed wiring board using the Adeiteibu method was substrate.

【0029】また上述の実施例においては、基材22、 Further, in the aforementioned embodiment, the substrate 22,
32、42又は52としてエポキシ又はフエノール等の樹脂基板を用いた場合について述べたが、本発明はこれに限らず、例えばアルミナ又はガラスセラミツク等のセラミツク材上に銅又は銀パターンが形成されたセラミツク基板を用いるようにしても良い。 32, 42 or 52 has been described for the case where a resin substrate such as epoxy or phenolic as the present invention is not limited to this, for example alumina or glass ceramic, copper or silver pattern on ceramic materials and the like are formed ceramic it may be used as the substrate.

【0030】 [0030]

【発明の効果】上述のように本発明によれば、基材表面の電子部品を実装する領域に凹形状のガイド溝を形成することにより、電子部品及び基材間を封止する封止用樹脂を電子部品及び基材間に確実に充填し得る電子部品実装用基板を実現し得る。 Effects of the Invention According to the present invention as described above, by forming a concave-shaped guide groove in a region for mounting electronic components on the substrate surface, a sealing for sealing between the electronic component and the substrate the resin capable of realizing electronic component mounting board which can reliably filled between the electronic component and the substrate.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明による電子部品実装用基板の一実施例を示す平面図及び断面図である。 It is a plan view and a cross-sectional view showing an embodiment of the electronic component mounting substrate according to the present invention; FIG.

【図2】封止用樹脂の滴下状態を示す部分的斜視図である。 2 is a partial perspective view showing a dropping state of the sealing resin.

【図3】他の実施例による電子部品実装用基板を示す平面図及び断面図である。 3 is a plan view and a cross-sectional view showing an electronic component mounting substrate according to another embodiment.

【図4】他の実施例による電子部品実装用基板を示す平面図及び断面図である。 4 is a plan view and a cross-sectional view showing an electronic component mounting substrate according to another embodiment.

【図5】他の実施例による電子部品実装用基板を示す平面図及び断面図である。 5 is a plan view and a cross-sectional view showing an electronic component mounting substrate according to another embodiment.

【図6】従来の電子部品実装用基板を示す側面図である。 6 is a side view showing a conventional substrate for electronic component mounting.

【図7】従来の電子部品実装用基板を示す平面図である。 7 is a plan view showing a conventional substrate for electronic component mounting.

【符号の説明】 DESCRIPTION OF SYMBOLS

3……リード、4……はんだバンプ、5……半導体チツプ、7……封止用樹脂、20、30、40、50……電子部品実装用基板、22、32、42、52……基材、 3 ...... lead, 4 ...... solder bumps, 5 ...... semiconductor chip, 7 ...... sealing resin, 20, 30, 40 ...... electronic component mounting board, 22, 32, 42, 52 ...... group wood,
25、35、45、55……ガイド溝。 25,35,45,55 ...... guide groove.

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】基材表面にリードを形成し、上記リードに所定の電子部品を実装すると共に、上記電子部品及び上記基材間に封止用樹脂を充填する電子部品実装用基板において、 上記基材表面の上記電子部品を実装する領域に凹状の溝を形成したことを特徴とする電子部品実装用基板。 1. A forming leads on the substrate surface, as well as implementing a predetermined electronic component in the lead, in the electronic component mounting board of filling a sealing resin between said electronic component and the substrate, the electronic component mounting board, characterized in that the formation of the concave groove in a region mounting the electronic components on the substrate surface.
  2. 【請求項2】上記凹状の溝は、 上記基材表面の上記電子部品を実装する領域よりも外側から上記実装領域の内部に亘つて形成されたことを特徴とする請求項1に記載の電子部品実装用基板。 Wherein said concave groove, electrons according to claim 1, characterized in that it is Wataru connexion formed inside said mounting region from the outside than the area for mounting the electronic components of the substrate surface substrate for component mounting.
JP29126593A 1993-10-26 1993-10-26 Substrate for mounting electronic part Pending JPH07122827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29126593A JPH07122827A (en) 1993-10-26 1993-10-26 Substrate for mounting electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29126593A JPH07122827A (en) 1993-10-26 1993-10-26 Substrate for mounting electronic part

Publications (1)

Publication Number Publication Date
JPH07122827A true JPH07122827A (en) 1995-05-12

Family

ID=17766636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29126593A Pending JPH07122827A (en) 1993-10-26 1993-10-26 Substrate for mounting electronic part

Country Status (1)

Country Link
JP (1) JPH07122827A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011018927A (en) * 2010-09-07 2011-01-27 Murata Mfg Co Ltd Circuit board
CN102054793A (en) * 2009-10-30 2011-05-11 夏普株式会社 Substrate member, module, electric equipment, and manufacturing method of modules
JP2012212832A (en) * 2011-03-31 2012-11-01 Kyocer Slc Technologies Corp Method for manufacturing composite wiring board
JP2012222209A (en) * 2011-04-11 2012-11-12 Ngk Spark Plug Co Ltd Component mounted board
JP2013098555A (en) * 2011-10-28 2013-05-20 Samsung Electro-Mechanics Co Ltd Circuit board, manufacturing method thereof, and semiconductor package comprising said circuit board
US9173299B2 (en) 2010-09-30 2015-10-27 KYOCERA Circuit Solutions, Inc. Collective printed circuit board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054793A (en) * 2009-10-30 2011-05-11 夏普株式会社 Substrate member, module, electric equipment, and manufacturing method of modules
JP2011096865A (en) * 2009-10-30 2011-05-12 Sharp Corp Substrate member, module, electric equipment, and manufacturing method of modules
JP2011018927A (en) * 2010-09-07 2011-01-27 Murata Mfg Co Ltd Circuit board
US9173299B2 (en) 2010-09-30 2015-10-27 KYOCERA Circuit Solutions, Inc. Collective printed circuit board
JP2012212832A (en) * 2011-03-31 2012-11-01 Kyocer Slc Technologies Corp Method for manufacturing composite wiring board
JP2012222209A (en) * 2011-04-11 2012-11-12 Ngk Spark Plug Co Ltd Component mounted board
JP2013098555A (en) * 2011-10-28 2013-05-20 Samsung Electro-Mechanics Co Ltd Circuit board, manufacturing method thereof, and semiconductor package comprising said circuit board

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