JPH07101095A - Printer - Google Patents

Abstract

PURPOSE:To provide a printer reduced in manufacturing cost and forming a printing image of high image quality. CONSTITUTION:A selection output gate SL1 is selected by selection signals SEL1, SEL2 and, when a strobe signal STB is inputted, printing data DATA is stored in a shift register in synchronous relation to a selected clock signal. This printing data DATA is outputted to an gate element through latch circuits L1-L64 and the gate element corresponding to the printing data DATA is driven. By this constitution, a current flows to the heating resistor corresponding to the driven gate element and the selection gate elements of SL2-SL4 are successively selected by the selection signal SEL1, SEL2 to perform printing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus equipped with a thermal head for performing thermal recording on a recording medium such as thermal paper, and a driving method thereof.

[0002]

2. Description of the Related Art FIG. 40 is a circuit diagram showing an electrical configuration of an example of a conventional thermal head. This thermal head is composed of a large number of heating resistors R1 to R1728 and a plurality of drive circuits 9 and the like, and in FIG.
The heat generating resistors are connected to one drive circuit 9, and the 576 heat generating resistors and the nine drive circuits 9 are divided into a total of three blocks B1 to B3 to perform a printing operation.

FIG. 41 is a circuit diagram showing an example of the drive circuit 9 shown in FIG. The drive circuit 9 outputs the print data DI composed of serial data from the external clock signal C.
A shift register S that converts the parallel data into a predetermined number of bits and outputs the parallel data by transferring in synchronization with LK.
R1 to SRn and a plurality of latch circuits L1 to Ln that store the outputs of the shift registers SR1 to SRn according to the latch signal LAT from the outside, and the latches L1 to Ln according to the strobe signal STBI and the print control signal BEO from the outside. Gate elements G1 to open and close the output of
Gn and a plurality of switching elements T1 to Tn for controlling the current flowing through the heating resistors R1 to Rn by the outputs of the respective gate elements G1 to Gn.

One end of each of the plurality of heating resistors R1 to Rn formed on the thermal head is connected to each of the switching elements T1 to Tn.
n drain elements, the other ends of the heating resistors R1 to Rn are commonly connected to the output side VH of the external power supply 10, and the source sides of the switching elements T1 to Tn are commonly connected. External power supply 7 to the terminal GND2
The ground side of 0 is connected.

This operation will be described with reference to the timing chart shown in FIG. The print data DATA for 1728 pixels formed as one scan line is input to and transferred to the shift registers SR1 to SRn of each drive circuit 9 in synchronization with the clock signal CLK, and the print signal for 64 pixels is provided in each drive circuit 9. DATA is converted into parallel data, respectively.

Next, the latch signal LAT is inverted, and the outputs of the shift registers SR1 to SRn of the drive circuit 9 are stored in the respective latch circuits L1 to Ln.

Next, when the print control signal BEO is inverted to the low level and the strobe signal STB1 is inverted to the low level, the block B composed of the heating resistors R1 to R576.
Each of the gate elements G1 to G of the nine drive circuits 9 corresponding to 1
n is opened, and each of the switching elements T1 to Tn is opened based on the print signal DATA stored in each of the latch circuits L1 to Ln.
Becomes selectively conductive. Then, the heating resistors R1 to R1
An electric current selectively flows through R576 to generate heat, heat the thermal paper or the thermal transfer film, and perform the printing operation of 1/3 of one scanning line corresponding to the block B1.

Similarly, when the strobe signal STB2 is inverted to the low level, the heating resistors R577 to R11 are similarly generated.
When a current flows selectively to 52 to generate heat, the printing operation of 1/3 of one scanning line corresponding to the block B2 is performed, and the strobe signal STB3 is inverted to a low level,
A current selectively flows through the heating resistors R1153 to R1728 to generate heat, and ⅓ of one scanning line corresponding to the block B3.
The printing operation of the part is performed. In this way, a series of images are recorded by printing one scanning line and repeating the above-mentioned operation while step-transporting the thermal paper or the thermal transfer film.

[0009]

However, as shown in FIG.
In the thermal head shown in FIG.
Since it is necessary to provide the same number of shift registers SR1 to SRn, latch circuits L1 to Ln, and switching elements T1 to Tn as the number of 28, the circuit configuration of the drive circuit 9 is further complicated, and a large number of the drive circuits 9 are thermally converted. It must be mounted on the head, and there is a problem in that the manufacturing cost of the thermal head increases.

Further, when the number of drive circuits 9 is large, there is a problem that it is difficult to downsize the thermal head.

SUMMARY OF THE INVENTION An object of the present invention is to provide a printer which can simplify the drive circuit and reduce the manufacturing cost in order to solve the above-mentioned problems.

[0012]

SUMMARY OF THE INVENTION According to the present invention, a plurality of heating resistors that form a printing pixel, a plurality of switching elements that control a current flowing through each heating resistor, and a plurality of gates that open and close each switching element. A column group for each of a predetermined number n (where n is a natural number) of a device and a shift register for inputting print data composed of serial data in synchronization with a clock signal and converting it into parallel data. Drive gate element that connects n gate elements corresponding to the heating resistors of each column group in common and opens / closes the output from the shift register by an external strobe signal, and the heating resistors of a plurality of row groups. Data is output from the shift register to the n select gate elements that commonly connect the bodies through the gate elements and the drive gate element. , A selection control means for driving a predetermined selection gate element by a selection signal from the outside and time-divisionally driving a heating resistor commonly connected to the selection gate element via the gate element, and a heating resistor of the row group A plurality of clock signal generating means for generating a clock signal corresponding to each of the plurality of clock signal generating means; And a clock signal selecting means for selecting the clock signal from the clock signal generating means.

Further, according to the present invention, a plurality of heating resistors forming a print pixel, a plurality of switching elements for controlling a current flowing through each heating resistor, a plurality of gate elements for opening and closing each switching element, and serial data. The shift register for inputting the print data consisting of the following in synchronization with the clock signal and converting it into parallel data and the heating resistor are divided into a predetermined number n (where n is a natural number) of column groups, and A driving gate element that connects n gate elements corresponding to the heating resistors of the column group in common and opens / closes the output from the shift register by a strobe signal from the outside, and a heating element of a plurality of row groups as the gate element. When data from the shift register is output to the n select gate elements that are commonly connected via the drive gate element and And a selection control means for driving a predetermined selection gate element in response to a selection signal and time-divisionally driving a heating resistor commonly connected to the selection gate element via the gate element. A plurality of storage means for storing a plurality of clock signal generation patterns for generating a clock signal corresponding to each heating resistor, and a plurality of clocks for generating a clock signal based on the clock signal generation pattern of the storage means A clock for selecting the clock signals from the plurality of clock signal generating means corresponding to the heating resistors to be time-division driven when the heating resistors are time-divisionally driven for each heating resistor of the row group by the signal generating means and the selection control means. A thermal head comprising a signal selecting means.

Further, according to the present invention, a plurality of heat generating resistors forming a print pixel, a plurality of switching elements for controlling a current flowing through each heat generating resistor, a plurality of gate elements for opening and closing each switching element, and serial data. The shift register for inputting the print data consisting of the following in synchronization with the clock signal and converting it into parallel data and the heating resistor are divided into a predetermined number n (where n is a natural number) of column groups, and A driving gate element that connects n gate elements corresponding to the heating resistors of the column group in common and opens / closes the output from the shift register by a strobe signal from the outside, and a heating element of a plurality of row groups as the gate element. When data from the shift register is output to the n select gate elements that are commonly connected via the drive gate element and And a selection control means for driving a predetermined selection gate element in response to a selection signal and time-divisionally driving a heating resistor commonly connected to the selection gate element via the gate element. A plurality of storage means for storing a plurality of clock signal generation patterns for generating a clock signal corresponding to each of the heating resistors, and time-division driving the row-group heating resistors by the selection control means. Based on the generation pattern selection means for selecting the generation pattern of the clock signal corresponding to the driven heating resistor from the plurality of clock signal generation patterns stored in the storage means, and the clock signal generation pattern selected by the generation pattern selection means ,
A thermal head comprising: a clock signal generating means for sequentially generating a clock signal.

[0015]

According to the present invention, the plurality of clock signal generating means generate a clock signal corresponding to each heating resistor of the row group. The clock signal selecting means, when the time-division driving is performed for each heating resistor of the row group by the selection control means, selects a clock signal corresponding to the heating resistor to be time-division driven and generates a clock signal.

Therefore, print data corresponding to each heating resistor time-divisionally driven by the generated clock signal is input to the shift register. As a result, the selection control unit sequentially applies a current to each heating resistor of the row group to perform printing, and it is possible to obtain a high-quality printed image in which adjacent printing dots are continuous.

Further, according to the invention, the storage means stores a plurality of clock signal generation patterns for generating a corresponding clock signal for each heating resistor of the row group.
The plurality of clock signal generation means generate clock signals based on the clock signal generation pattern of the storage means. The clock signal selecting means, when time-divisionally driven for each heating resistor of the row group by the selection control means, selects and drives a clock signal corresponding to the heating resistor to be time-divisionally driven to generate a clock signal. .

Therefore, by the generated clock, the print data corresponding to each heating resistor which is time-division driven is input to the shift register. As a result, the selection control unit sequentially applies current to each of the heating resistors of the row group to perform printing, and it is possible to obtain a high-quality printed image in which adjacent printing dots are continuous.

Further according to the invention, the storage means stores a plurality of clock signal generation patterns for generating a clock signal corresponding to each heating resistor of the row group. The generation pattern selecting means, when the heating resistors of the row group are time-divisionally driven by the selection control means,
A clock signal generation pattern corresponding to the heating resistor driven in a time division manner is selected from a plurality of clock signal generation patterns of the storage means. The clock signal generation means sequentially generates clock signals based on the clock signal generation pattern selected by the generation pattern selection means.

Therefore, print data corresponding to each heating resistor time-divisionally driven by the generated clock signal is input to the shift register. As a result, the selection control means sequentially applies a current to each heating resistor of the row group to perform printing, and it is possible to obtain a high-quality printed image in which adjacent printing dots are continuous.

[0021]

【Example】

(Embodiment 1) FIG. 1 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to an embodiment of the present invention. This thermal head has a large number of heating resistors R1 to R204.
8 and a plurality of drive circuits 20. In FIG. 1, the individual electrodes 23 of the 256 heating resistors are connected to one drive circuit 20, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, the print data DATA,
Selection signals SEL1, SEL2, strobe signal STB,
Control signals such as a clock signal CLK and a latch signal LAT are input.

Further, the clock signal generation circuit 25 includes clock signals CLK1 to C that have different output timings.
LK4, selection signals SEL1 and SEL2 are input, the clock signal CLK is output from the clock signal generation circuit 25, and the clock signal CLK is applied to each drive circuit 20.

FIG. 2 is a circuit diagram showing an electrical configuration of the drive circuit 20 shown in FIG. The drive circuit 20 transfers the print signal DATA composed of serial data in synchronization with the clock signal CLK from the outside to convert the parallel image data into parallel data for each predetermined number of bits, and the shift registers SR1 to SR64. When a plurality of latch circuits L1 to L64 storing the outputs of the shift registers SR1 to SR64 and a strobe signal STB are input by a latch signal LAT from the outside, the latch circuit L is input.
Drive gate element G1 for outputting data from 1 to L64
To G64.

Four gate elements S1 to S256 for driving each heating resistor are connected in parallel to each drive gate element G1 to G64. For example, the drive gate element G1 includes gate elements S1 to S4. Are connected. The four gate elements S (collective names of the gate elements S1 to S256) connected to the drive gate elements G1 to G64 are commonly connected to the select gate elements SL1 to SL4, respectively. Drive gate elements G1 to G64 of which the output is opened or closed. The selection gate elements SL1 to SL4 are selected and driven by a combination of the output levels (high level or low level) of the selection signals SL1 and SL2.

The gate elements S1 to S256 are connected to the switching elements T1 to T256, and the switching element T1.
By controlling 1 to T256, the output pad D1
Through D256, the currents flowing through the heating resistors R1 to R256 are controlled. The order of the heating resistors corresponds to the number of the gate element. For example, the k-th heating resistor (k is a natural number) counting from the shortest part is connected to the gate element SLk shown in FIG.

Further, every four heating resistors are divided into one group, and in each of the adjacent odd-numbered and even-numbered groups, in the arrangement of the selection gate elements S corresponding to the odd-numbered groups of heating resistors. , The numbers of the gate elements are in ascending order, and the numbers of the gate elements are in descending order in the arrangement of the selection gate elements S corresponding to the heating resistors of the even-numbered groups.

Here, the gate elements S of each group are commonly connected to the selection gate elements SL1 to SL4 in the order of arrangement,
For example, the gate elements S1 and S8 are selected as the first selection gate element SL1, the selection gate elements S2 and S7 are selected as the second selection gate element SL2, and the gate elements S3 and S6 are selected as the third selection gate element SL2. A gate element S4 and a gate element S5 are commonly connected to the gate element SL3 and a fourth select gate element SL4.

FIG. 3 is a time chart when the thermal head shown in FIG. 1 is driven. In this time chart, as means for inputting the print data corresponding to the heating resistors selected by the selection gate elements SL1 to SL4, instead of processing the printing data to be printed in advance, all the printing resistors corresponding to the order of the heating resistors are input. The print data of is input as it is as serial data.

Next, of the print data, only the clock signal CLK synchronized with the print data corresponding to the heating resistors selected by the selection gate elements SL1 to SL4 is input, that is, the continuous print data is required. Print data to be printed is selected and stored in the shift register. Therefore, the print data D shown in FIG. 3 are all data output corresponding to the order of the heating resistors,
The clock signals CK1 to CK4 are output in synchronization with the print data to be printed. After the output of the print data D1 to D4, the latch signal LAT is inverted for a certain period of time, and the outputs of the shift registers SR1 to SR64 of the drive circuits 22 are stored in the latch circuits L1 to L64. Next, when the strobe signal is output, printing is performed based on the data stored in the latch circuits L1 to L64.

FIG. 4 is a time chart showing the output timing of the clock signals CK1 to CK4. The clock signal CK1 is output in synchronization with the 8n + 1 (n is a natural number) and 8 (n + 1) th print data from the first print data, and the clock signal CK2 is the 8n + 2, 8n + 7th print data from the first print data. The clock signal CK3 is output in synchronization with the data, the clock signal CK3 is output in synchronization with the 8n + 3rd and 8n + 6th print data from the first print data, and the clock signal CK4 is the 8n + 4th, 8n + 5th print data from the first print data. It is output in synchronization with the data.

FIG. 5 shows a clock signal generation circuit 25 for generating the clock signals CK1 to CK4 shown in FIGS. Depending on the combination of the output levels (low level or high level) of the selection signals SL1 and SL2,
Select gate elements SL11 to SL14 are selected. When both the selection signals SEL1 and SEL2 are at low level, the selection gate element SL14 is selected, and the selection signals SEL1 and S
Select gate element SL11 when both EL2 are high level
Is selected. In addition, the selection signal SEL1 is high level,
When the selection signal SEL2 is low level, the selection gate element SL12 is selected, the selection signal SEL1 is low level,
Select gate element S when select signal SEL2 is at high level
L13 is selected. When the select gate element SL14 is selected and its output is at high level, the AND gate element 2
The clock signal CLK1 is selected by 6 and output via the OR gate element 30.

When the select gate element SL11 is selected and its output is at a high level, the clock signal CLK2 signal is selected via the AND gate element 27 and output via the OR gate element 30. Select gate element SL12
Is selected and its output is at a high level, the clock signal CLK3 signal is selected via the AND gate element 28 and output via the OR gate element 30. When the select gate element SL14 is selected and its output is at the high level, the clock signal C is supplied via the AND gate element 29.
LK4 is selected and output via the OR gate element 30.

The output timing of the clock signal CLK1 is the output timing of the clock signal CK1 shown in FIG. 4, and the output timing of the clock signal CLK2 is the output timing of the clock signal CK2. The output timing of the clock signal CLK3 is the output timing of the clock signal CK3 shown in FIG. 4, and the output timing of the clock signal CLK is the output timing of the clock signal CK4.

Therefore, as shown in FIG. 3, the clock signals CK1 to CK4 are output in synchronization with the print data D1 to D4 according to the output levels of the selection signals SEL1 and SEL2.

FIG. 6 is a print image when the thermal head shown in FIG. 1 prints based on the time chart shown in FIG. In this thermal head, after printing by the print data corresponding to the clock signal CK1, print data corresponding to the clock signal CK2, print data corresponding to the clock signal CK3, and print data corresponding to the clock signal CK4 are printed on the recording medium. Are sequentially carried out in the carrying direction.

Therefore, as shown in FIG. 6, a print image of a meandering line is obtained. In this print image, the print dots are evenly spaced in the print of each line, so that streaks and blurring do not occur locally. Further, in reality, since the length of the heating resistor in the paper feeding direction is sufficiently longer than the length shown in FIG. 6, there is almost no gap between adjacent printing dots, and printing can be performed as a continuous line.

(Embodiment 2) FIG. 7 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 32. In FIG. 7, the individual electrodes 23 of the 256 heating resistors are connected to one drive circuit 32, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, print data DATA, selection signals SEL1 and SEL2, strobe signal STB, clock signals CLK1 to CLK4, and control signals such as latch signal LAT are input to each drive circuit 32.

FIG. 8 is a circuit diagram showing an electrical configuration of the drive circuit 32 shown in FIG. The drive circuit 32 is similar to the drive circuit 20 shown in FIG. 2, and corresponding parts are denoted by the same symbols. The difference between the drive circuit 32 and the drive circuit 20 is that the drive circuit 32 is provided with a clock signal generation circuit 33. This clock signal generation circuit 33
2 has the same circuit configuration and operation as the clock signal generating circuit 25 shown in FIG. The other parts are the same as those of the drive circuit shown in FIG.

FIG. 9 is a time chart when the thermal head shown in FIG. 7 is driven. Print data DATA of this time chart, latch signal LAT, clock signal CLK, strobe signal STB, selection signal SEL
The output timings of 1 and SEL2 are the same as those in the time chart shown in FIG.

The clock signals CK1 to CK4 in the clock signals CLK1 to CLK4 are output in synchronization with the data to be printed out of the printing data D, as shown in FIG. Depending on the combination of the output levels (low level or high level) of the selection signals SEL1 and SEL2 in the clock signal generation circuit 33, the clock signal CK
1 to CK4 are sequentially selected and output from the OR gate element 34 to the shift register SR.

Also, when the thermal head shown in FIG. 7 is used to print based on the time chart shown in FIG. 9, the printed image shown in FIG. 6 can be obtained.

(Third Embodiment) FIG. 10 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 20. In FIG. 10, the individual electrodes 23 of the 256 heating resistors are connected to one drive circuit 20, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. Further, each drive circuit 20 has print data DATA and selection signals SEL1 and SEL.
2. Control signals such as strobe signal STB, clock signal CLK, and latch signal LAT are input.

The clock signal CK0 and the selection signals SEL1 and SEL2 are input to the clock signal generation circuit 40, and the clock signal CL is output from the clock signal generation circuit 40.
K is output and given to each drive circuit 20. The circuit diagram of the drive circuit 20 is shown in FIG. 2, and the time charts for driving this thermal head are shown in FIG. 3 and FIG. 4, and since the contents have been described above, the description thereof will be omitted.

FIG. 11 shows a clock generation circuit 40 for generating the clock signals CK1 to CK4 shown in FIGS. Depending on the combination of the output levels (low level or high level) of the selection signals SL1 and SL2,
Select gate elements SL11 to SL24 are selected. When both the selection signals SEL1 and SEL4 are at low level, the selection gate element SL24 is selected, and the selection signals SEL1 and S
Select gate element SL21 when EL2 are both high level
Is selected. In addition, the selection signal SEL1 is high level,
When the selection signal SEL2 is low level, the selection gate element SL22 is selected, the selection signal SEL1 is low level,
Select gate element S when select signal SEL2 is at high level
L23 is selected.

When the select gate element SL24 is selected and its output is at high level, the clock signal CK0 is input to the clock generator 46 via the AND gate element 41. The clock signal CK0 is a clock signal that is output in synchronization with the print data DATA of all the heating resistors. When selected by the selection gate element 21 and its output is at a high level, the clock signal CK0 is input to the clock generator 47 via the AND gate element 42. When the select gate element 22 is selected and its output is at high level,
The clock signal CK0 is input to the clock generator 48 via the AND gate element 43. Select gate element 23
Is selected and its output is at a high level, the clock signal CK0 is input to the clock generator 49 via the AND gate element 44. The clock signal CLK is output from the clock signal generators 46 to 49 via the OR gate element 45.

FIG. 12 shows clock signal generators 46-49.
3 is a block diagram showing the electrical configuration of FIG. The clock signal generators 46 to 49 respectively have 8-bit memories M1 to M4. For example, the clock signal generator 46
In the memory M1 of FIG. 3, 8-bit data “10000001” is stored in the memory M1, and this data indicates a clock signal generation pattern. The operation of the clock signal generator 46 will be described below. When the clock signal generator 46 is selected, the clock signal CK0
Is input to the input terminal IN of the clock signal generator 46. When the first clock signal of the clock signal CK0 is input, the logical value of the first bit of the 8-bit data is determined, and since the logical value is "1", it is synchronized with the first clock signal. , High level clock signal CLK
Is output from the output terminal OUT. Next, clock signal C
When the second clock of K0 is input, the logical value of the second bit of the data is determined, and since the logical value is "0", the low-level clock signal CLK is synchronized with the second clock signal. Is output from the output terminal OUT.

Thereafter, the above-described processing is repeated, and the clock signal CLK corresponding to the logical value of the 8-bit data "10000001" is output. When the clock signal corresponding to the 8th bit of the data is output, the data corresponding to the 1st bit of the data is output next. That is, the clock signal corresponding to 8-bit data is set to 1 synchronization, the cycle is repeated, and the clock signal CLK is output. Therefore, the output timing of the clock signal CLK output from the pulse generator 46 is the output timing of the clock signal CK1 in the time charts shown in FIGS.

The pulse generator 47 is an 8-bit memory M.
2 and 8-bit data “0100
“0010” is stored. When the pulse generator 47 is selected and the clock signal CK0 is input, the clock signal C corresponding to the clock signal generation pattern represented by the data of the memory M2 is synchronized with this signal as described above.
LK is output. Therefore, the output timing of the clock signal CLK output from the pulse generator 47 is the clock signal CK of the time charts shown in FIGS.
2 is the output timing.

The pulse generator 48 is an 8-bit memory M.
3 and the 8-bit data “0010
“0100” is stored. When the pulse generator 48 is selected and the clock signal CK0 is input, the clock signal C corresponding to the clock signal generation pattern represented by the data of the memory M3 is synchronized with this signal as described above.
LK is output. Therefore, this pulse generator 48
The output timing of the clock signal output from the clock signal CK of the time chart shown in FIGS.
3 is the output timing.

The pulse generator 49 is an 8-bit memory M.
4 and the memory M4 stores 8-bit data "0001
1000 ”is stored. When the pulse generator 49 is selected and the clock signal CK0 is input, the clock signal C corresponding to the clock signal generation pattern represented by the data of the memory M4 is synchronized with this signal as described above.
LK is output. Therefore, this pulse generator 49
The output timing of the clock signal output from the clock signal CK of the time chart shown in FIGS.
4 is the output timing.

Also, when the thermal head shown in FIG. 10 is used to print based on the time chart shown in FIG. 3, the printed image shown in FIG. 6 can be obtained.

(Embodiment 4) FIG. 13 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 50. In FIG. 13, the individual electrodes 23 of the 256 heating resistors are connected to one drive circuit 50, and all the heating resistors R1 to R2048 are connected to the common electrode V.
Commonly connected to H. In addition, each drive circuit 50 has
Print data DATA, selection signals SEL1 and SEL2, strobe signal STB, clock signals CLK1 to CLK
4. Each control signal such as the latch signal LAT is input.

FIG. 14 shows the drive circuit 50 shown in FIG.
3 is a circuit diagram showing the electrical configuration of FIG. This drive circuit 50
2 is similar to the drive circuit 20 shown in FIG. 2, and corresponding parts are denoted by the same symbols. The difference between the drive circuit 50 and the drive circuit 20 is that the drive circuit 50 is provided with a clock signal generation circuit 51. The clock signal generation circuit 51 is the same as the clock signal generation circuit 40 shown in FIG.
Since the circuit configuration and operation are the same, the description is omitted. The other parts are the same as those of the drive circuit shown in FIG.

Since the time charts for driving the thermal head shown in FIG. 13 are shown in FIGS. 3 and 4 and have been described above, the description thereof will be omitted. Further, when the thermal head shown in FIG. 13 is used to print based on the time chart shown in FIG. 3, the printed image shown in FIG. 6 can be obtained.

(Embodiment 5) FIG. 15 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to an embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 20. In FIG. 1, the individual electrodes 23 of the 256 heating resistors are connected to one drive circuit 20, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, print data DATA, selection signals SEL1 and SEL2, strobe signal STB, clock signals CLK1 to CLK4, and control signals such as latch signal LAT are input to each drive circuit 20.

The clock signal CK0, the selection signals SEL1, SEL2, and the trigger signal TRG are input to the clock signal generation circuit 55, and the clock signal CLK is output from the clock signal generation circuit 40 and given to each drive circuit 20. . The circuit diagram of the drive circuit 20 is shown in FIG. 2 and has been described above.

FIG. 16 is a time chart when the thermal head shown in FIG. 15 is driven. This time chart is similar to the time chart shown in FIG. The difference between this time chart and the time chart shown in FIG. 3 is that in this time chart, when the clock signals CK1 to CK4 are output, the trigger signal TRG is output.
Are being output in synchronization. The trigger signal TRG will be described later. The output timings of other signals are the same as those in the time chart shown in FIG. The output timings of the clock signals CK1 to CK4 shown in FIG. 3 are shown in the time chart of FIG.

FIG. 17 shows a clock signal generation circuit 55 for generating the clock signals CK1 to CK4 shown in FIGS. The selection gate elements SL31 to SL34 are selected by a combination of the output levels (low level or high level) of the selection signals SL1 and SL2. When both the selection signals SEL1 and SEL2 are at the low level, the selection gate element SL34 is selected and the selection signal SEL
Select gate element S when both 1 and SEL2 are at high level
L31 is selected. When the selection signal SEL1 is high level and the selection signal SEL2 is low level, the selection gate element SL32 is selected, and when the selection signal SEL1 is low level and the selection signal SEL2 is high level, the selection gate element SL33 is selected.

When the select gate element SL34 is selected and its output is at the high level, the trigger signal TRG is sent via the AND gate element 56 to the select terminal S1 of the memory M11.
Entered in. When selected by the selection gate element 31 and its output is at high level, the trigger signal TRG is input to the selection terminal S2 of the memory M12 via the AND gate element 57. When the select gate element 32 is selected and its output is at high level,
The trigger signal TRG is input to the select terminal S3 of the memory M13. When the select gate element 33 is selected and its output is at high level, the trigger signal TRG is input to the select terminal S4 of the memory M14 via the AND gate element 59. The clock signal CK0 is input to the input terminal IN of the clock signal generator 60.

The clock signal CKO is a clock signal output in synchronization with the print data DATA of all the heating resistors. Further, the output terminal OUT of the clock signal generator 60
The processed clock signal CLK is output. The clock signal generator 60 has a memory LM, and each memory M
The data of 11 to M11 are read.

The operation of clock signal generator 60 having the memory function shown in FIG. 18 will be described. For example, when the select terminal S1 of the memory M11 becomes high level and the memory M11 is selected, the 8-bit data “10000001” stored in the memory 11 is transferred to the memory LM of the clock signal generator 60. The 8-bit data stored in the memory M11 represents a clock signal generation pattern. In this case, the first clock signal of the clock signal CK0 is the clock generator 60.
Input to the memory LM, the logical value of the first bit of the 8-bit data stored in the memory LM is determined. Since the logical value is “1”, the high level is synchronized with the first clock signal. Clock signal CLK is output from the output terminal OUT. Next, when the second clock of the clock signal CK0 is input, the logical value of the second bit of the data is determined, and since the logical value is "0", it is synchronized with the second clock signal and goes to the low level. Clock signal CLK is output from the output terminal OUT.

Thereafter, the above-described processing is repeated, and the clock signal CLK corresponding to the logical value of the 8-bit data "10000001" is output. When the clock signal corresponding to the 8th bit of the data is output, the data corresponding to the 1st bit of the data is output next. That is, the clock signal corresponding to 8-bit data is set to 1 synchronization, the cycle is repeated, and the clock signal CLK is output. Therefore, the output timing of the clock signal CLK output from the pulse generator 60 is the output timing of the clock signal CK1 in the time charts shown in FIGS.

Next, when the select terminal 52 of the memory M12 goes high and the memory M12 is selected, the 8-bit data "01000" stored in the memory M12 is selected.
010 ”is transferred to the memory LM of the clock signal generator 60. In this case, when the clock signal CK0 is input, the clock signal CLK corresponding to the clock signal generation pattern represented by the data of the memory M12 is output in synchronization with this signal. Therefore, the output timing of the clock signal output from the pulse generator 60 is the output timing of the clock signal CK2 in the time charts shown in FIGS.

Next, when the select terminal S3 of the memory M13 goes high and the memory M13 is selected, the 8-bit data "00100" stored in the memory M13 is selected.
100 ”is transferred to the memory LM of the clock signal generator 60. In this case, when the clock signal CK0 is input, the clock signal CLK corresponding to the clock signal generation pattern represented by the data of the memory M13 is output in synchronization with this signal. Therefore, the output timing of the clock signal output from the pulse generator 60 is the output timing of the clock signal CK3 in the time charts shown in FIGS.

Next, when the select terminal 54 of the memory M14 becomes high level and the memory M14 is selected, the 8-bit data "00011" stored in the memory M14 is stored.
000 ”is transferred to the memory LM of the clock signal generator 60. In this case, when the clock signal CK0 is input, the clock signal CLK corresponding to the clock signal generation pattern represented by the data of the memory M14 is output in synchronization with this signal. Therefore, the output timing of the clock signal output from the pulse generator 60 is the output timing of the clock signal CK4 in the time charts shown in FIGS.

Even when the thermal head shown in FIG. 15 prints based on the time chart shown in FIG. 16, the printed image shown in FIG. 6 can be obtained.

(Sixth Embodiment) FIG. 19 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 65. In FIG. 19, the individual electrodes 23 of the 256 heating resistors are connected to one drive circuit 22, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. Further, each drive circuit 65 has print data DATA and selection signals SEL1 and SEL.
2. Control signals such as strobe signal STB, clock signal CLK, and latch signal LAT are input.

FIG. 20 shows a drive circuit 65 shown in FIG.
3 is a circuit diagram showing the electrical configuration of FIG. This drive circuit 50
2 is similar to the drive circuit 20 shown in FIG. 2, and corresponding parts are denoted by the same symbols. The difference between the drive circuit 65 and the drive circuit 20 is that the drive circuit 65 is provided with a clock signal generation circuit 66. In this clock signal generation circuit 66, the clock signal generation circuit 5 shown in FIG.
Since the circuit configuration and operation are the same as those of No. 5, description will be omitted. The other parts are the same as those of the drive circuit shown in FIG.

FIG. 21 is a time chart when the thermal head shown in FIG. 19 is driven. The clock signal CK in the clock signal CK0 corresponding to the print data of all the heating resistors is continuously output in synchronization with the print data D. The signal is processed by the clock signal generation circuit 55 described above, and clock signals CK1 to CK4 are processed.
Is output in synchronization with the trigger signal TRG. The output timings of the other signals are the same as the output timings of the time charts shown in FIGS.

Even when the thermal head shown in FIG. 19 prints based on the time chart shown in FIG. 21, the printed image shown in FIG. 6 can be obtained.

(Embodiment 7) FIG. 22 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 70. In FIG. 1, the individual electrodes 71 of the 256 heating resistors are connected to one drive circuit 20, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, the heating resistors R1 to R
The whole 2048 is divided into a block B1 and a block B2, and selectively driven by the corresponding strobe signals STB1 and STB2. Therefore, the strobe signal STB1 is input to each drive circuit of the block B1, and the strobe signal STB2 is input to each drive circuit of the block B2. Further, the print data DA is provided in each drive circuit 70.
Control signals such as TA and clock signals CLK1 to CLK4 are input. The selection signals SEL1 and SEL2 are input to the drive circuits 70 of the B1 block, and the selection signals SEL3 and SEL are input to the drive circuits 70 of the B2 block.
4 is input.

Further, the clock signal generating circuit 25a includes
Clock signal CLK1 with different output timing
~ CLK4, selection signals SEL1, SEL2 are input,
The clock signal CLK is output from the clock signal generation circuit 25a and applied to each drive circuit 70 of the block B1. The clock signals CLK1 to CLK4 and the selection signals SEL3 and SEL4 having different output timings are input to the clock signal generation circuit 25b, and the clock signal CLK is output from the clock signal generation circuit 25b and given to each drive circuit 70 of the block B2. To be

FIG. 23 is a circuit diagram showing an electrical configuration of an example of the drive circuit 70. The drive circuit 70 transfers a print signal D1 composed of serial data in synchronization with an external clock signal CLK, thereby converting the output into parallel data for each predetermined number of bits, and the strobes SR1 to SR64. Signal STB (general term for strobe signal STB1 and strobe signal STB2)
Is input, the shift registers SR1 to SR6
Drive gate elements G1 to G64 for outputting data from
It has and.

Four gate elements S1 to S256 for driving each heating resistor are connected in parallel to each drive gate element G1 to G64. For example, the drive gate element G1 includes gate elements S1 to S4. Are connected. The four gate elements S (collective names of the gate elements S1 to S256) connected to the drive gate elements G1 to G64 are commonly connected to the select gate elements SL1 to SL4, respectively. Selected by the driving gate elements G1 to G64 of FIG. The selection gate elements SL1 to SL4 are selected and driven by a combination of the output levels (high level or low level) of the selection signals SL1 and SL2.

By controlling the switching elements T1 to T256, the gate elements S1 to S256 control the switching elements T1 to T256 to output the heating pads R1 to R25 via the output pads D1 to D256.
The current flowing through 6 is controlled. The order of each heating resistor and the number of the gate element correspond to each other. For example, the k-th heating resistor (k is a natural number) counting from the end is connected to the gate element SLk shown in FIG. .

Further, every four heating resistors are divided into one group, and in each adjacent odd-numbered and even-numbered groups, in the arrangement of the selection gate elements S corresponding to the odd-numbered groups of heating resistors. , The numbers of the gate elements are in ascending order, and the numbers of the gate elements are in descending order in the arrangement of the selection gate elements S corresponding to the heating resistors of the even-numbered groups.

Here, the gate elements S of each group are commonly connected to the selection gate elements SL1 to SL4 in the order of arrangement,
For example, the gate elements S1 and S6 are selected as the first selection gate element SL1, the selection gate elements S2 and S7 are selected as the second selection gate element SL2, and the gate elements S3 and S6 are selected as the third selection gate element SL2. A gate element S4 and a gate element S5 are commonly connected to the gate element SL3 and a fourth select gate element SL4.

Further, in the drive circuit 70, the clock gate CG is provided instead of providing the latch circuit, and when the strobe signal STB is in the active state (low level),
Since the input of the clock signal CLK is blocked, the printing data can be input to the other block while the printing of one block is being performed by the strobe signal STB.

As described above, the drive circuit 70 does not need to be provided with a latch circuit and a plurality of heating resistors are commonly connected to one shift register. Therefore, the number of shift registers can be greatly reduced. You can As a result, the circuit scale of the drive circuit 70 can be greatly reduced.

Next, the operation of the thermal head equipped with the drive circuit 70 of FIG. 23 will be described with reference to the time chart of FIG. In each of the block B1 and the block B2, one line is printed in four divisions, and one block is printed in each block, that is, eight divisions. Here, the heating resistor of the block B1 and the heating resistor of the block B2 alternately print in synchronization with the strobe signal STB, and the odd-numbered printing data D is the printing data of the block B1 and the even-numbered printing data. D
Is print data of block B2. Select gate element S
As means for inputting the print data corresponding to the heating resistors selected by L1 to SL4, instead of processing the print data to be printed in advance, all the print data corresponding to the order of the heating resistors are directly converted to serial data. You are typing.

Next, of the print data, only the clock signal CLK which is synchronized with the print data corresponding to the heating resistors selected by the select gate elements SL1 to SL4 is input, that is, the continuous print data is required. Print data to be printed is selected and stored in the shift register. Therefore, the print data D shown in FIG. 24 is all data output corresponding to the order of the heating resistors, and the clock signals CK1 to CK8 are output in synchronization with the print data to be printed.

Clock signals CK1, CK3, CK5, C
As shown in FIG. 25, K7 is output in synchronization with the print data to be printed in the data DB1 of the B1 block, and the clock signals CK2, CK4, CK6, CK8 are
It is output in synchronization with the data to be printed in the data DB2 of the B2 block.

FIG. 26 is a timing chart showing the output timing of the clock signals CK1 to CK8. The clock signals CK1 and CK2 are output in synchronization with the 8n + 1 (n is a natural number) and 8 (n + 1) th print data from the first print data of each block.
3 and CK4 are 8n from the first print data of each block
The clock signals CK5 and CK6 are output in synchronization with the + 2nd, 8n + 7th print data, and the clock signals CK5 and CK6 are output in synchronization with the 8n + th, 8n + 6th print data from the first print data of each block.
Is 8n + 4th from the first print data of each block,
It is output in synchronization with the 8n + 5th print data.

Clock signal generation circuit 25 shown in FIG.
Reference symbols a and 25b are clock signal generation circuits for generating the clock signals CK1 to CK8 described above. The clock signal generating circuits 25a and 25b are the same as the clock signal generating circuit 25 shown in FIG. 5, respectively, and the circuit configuration and the operation contents have been described above, and therefore the description thereof will be omitted. Therefore, as shown in the timing chart of FIG. 24, depending on the combination of the output levels (high level or low level) of the selection signal SEL1 and the selection signal SEL2, the clock signal generation circuit 25a sequentially outputs the clock signals CK1, CK3, CK5. CK7 is selected and output. Further, the clock signal generation circuit 2 is selected by combining the output levels of the selection signal SEL3 and the selection signal SEL4.
The clock signals CK2, CK4, CK6 are sequentially output from 5b.
CK8 is selected and output.

FIG. 27 is a block B1 and a block B when printing is performed on the thermal head shown in FIG. 22 based on the timing chart shown in FIG.
2 is a printed image. In the block B1, the print data selected by the clock signal CK3 following the print data selected by the clock signal CK1,
The print data selected by the clock signal CK5 and the print data selected by the clock signal CK7 are sequentially printed in the paper feeding direction. In block B2,
Following the printing by the printing data selected by the clock signal CK2, the printing data selected by the clock signal CK4, the printing data selected by the clock signal CK6, and the printing by the printing data selected by the clock signal CK8 are described above. The printing is sequentially performed in the paper feeding direction alternately with the printing of the block B1.

Therefore, as shown in FIG. 27, a print image of a meandering line is obtained. In this print image, the print dots are evenly spaced in the print of each line, so that streaks, haze, etc. do not occur locally. Further, in reality, the length of the heating resistor in the paper feeding direction is sufficiently longer than the length shown in FIG. 27, so that there is almost no gap between adjacent printing dots, and printing can be performed as a continuous line.

(Embodiment 8) FIG. 28 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 75. In FIG. 28, the individual electrodes 71 of the 256 heating resistors are connected to one drive circuit 75, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, the heating resistors R1 to R1
The entire R2048 is divided into a block B1 and a block B2, and selectively driven by the corresponding strobe signals STB1 and STB2. Therefore, the strobe signal STB1 is input to each drive circuit of the block B1, and the strobe signal STB2 is input to each drive circuit of the block B2. In addition, print data D is provided in each drive circuit 75.
Each control signal such as ATA and clock signals CLK1 to CLK4 is input. Each drive circuit 75 of B1 block
Select signals SEL1 and SEL2 are input to the drive circuits 75 of the B2 block.
L4 is input.

FIG. 29 shows a drive circuit 75 shown in FIG.
3 is a circuit diagram showing the electrical configuration of FIG. This drive circuit 75
23 is similar to the drive circuit 70 shown in FIG. 23, and corresponding parts are denoted by the same symbols. The difference between the drive circuit 75 and the drive circuit 70 is that the drive circuit 75 is provided with a clock signal generation circuit 76. The clock signal generation circuit 76 is the same as the clock signal generation circuit 25 shown in FIG.
Since the circuit configuration and operation are the same, the description is omitted. Also, for the other parts, the drive circuit 70 shown in FIG.
The description is omitted because it is the same as.

FIG. 30 is a time chart when the thermal head shown in FIG. 28 is operated. Print data DATA and strobe signal ST of this time chart
The output timings of B1, STB2, and the selection signals SEL1 to SEL4 are the same as those in the time chart shown in FIG.

The clock signals CK1 to CK4 in the clock signals CLK1 to CLK4 are output in synchronization with the print data D to be printed. The clock signals CK1 to CK4 corresponding to the print data of the block B1 are selected by the clock signal generation circuit 76 by the combination of the output levels of the selection signals SEL1 and SEL2 in the clock generation circuit 76 of the drive element 75 of the block B1 as described above. And is output from the OR gate element 77 to the shift register SR. Select signal SE in clock signal generation circuit 76 of drive element 75 of block B2
Depending on the combination of the output levels of L3 and SEL4, the clock signals CK1 to CK1 corresponding to the print data of the block B2.
CK4 is sequentially selected by the clock signal generation circuit 76 as described above, and is output from the OR gate element 77 to the shift register SR. The output timings of the clock signals CK1 to CK4 are shown in FIG.

Further, when the thermal head shown in FIG. 28 is used for printing on the basis of the time chart shown in FIG. 30, the printed image shown in FIG. 27 can be obtained.

(Embodiment 9) FIG. 31 is a circuit diagram showing the electrical construction of a thermal head of a printing apparatus according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 70. In FIG. 31, the individual electrodes 71 of the 256 heating resistors are connected to one drive circuit 70, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, the heating resistors R1 to R1
The entire R2048 is divided into a block B1 and a block B2, and selectively driven by the corresponding strobe signals STB1 and STB2. Therefore, the strobe signal STB1 is input to each drive circuit of the block B1, and the strobe signal STB2 is input to each drive circuit of the block B2. Further, the print data D is provided in each drive circuit 70.
Each control signal such as ATA and clock signal CLK is input. The selection signals SEL1 and SEL2 are input to the drive circuits 70 of the B1 block, and the selection signals SEL3 and SEL4 are input to the drive circuits 70 of the B2 block.

Further, the clock signal generating circuit 40a includes
The clock signal CK0 and the selection signals SEL1 and SEL2 are input, the clock signal CLK is output from the clock signal generation circuit 40a, and the clock signal CLK is applied to each drive circuit 70 of the block B1. The clock signal CK0 and the selection signals SEL3 and SEL4 are input to the clock signal generation circuit 40b,
The clock signal CLK is output from the clock signal generation circuit 40b and given to each drive circuit 70 of the block B2.

Drive circuit 70 is shown in FIG. 23, and clock signal generation circuits 40a and 40b are the same as clock signal generation circuit 40 shown in FIG. Therefore, since the configuration and operation of each circuit have been described above, the description thereof will be omitted. The time chart when the thermal head in FIG. 31 is driven is the same as the time charts shown in FIGS. further,
Even when the thermal head shown in FIG. 31 prints based on the time chart shown in FIG. 24, the printed image shown in FIG. 27 can be obtained.

(Embodiment 10) FIG. 32 is a circuit diagram showing the electrical construction of a thermal head of a printer according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 80. In FIG. 1, the individual electrodes 71 of the 256 heating resistors are connected to one drive circuit 80, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. In addition, the heating resistors R1 to R1
The entire R2048 is divided into a block B1 and a block B2, and selectively driven by the corresponding strobe signals STB1 and STB2. Therefore, the strobe signal STB1 is input to each drive circuit of the block B1, and the strobe signal STB2 is input to each drive circuit of the block B2. In addition, the print data D is provided in each drive circuit 20.
Each control signal such as ATA and clock signal CLK is input. The selection signals SEL1 and SEL2 are input to the drive circuits 80 of the B1 block, and the selection signals SEL3 and SEL4 are input to the drive circuits 80 of the B2 block.

FIG. 33 shows a drive circuit 80 shown in FIG.
3 is a circuit diagram showing the electrical configuration of FIG. This drive circuit 80
23 is similar to the drive circuit 70 shown in FIG. 23, and corresponding parts are denoted by the same symbols. The difference between the drive circuit 80 and the drive circuit 70 is that the drive circuit 80 is provided with a clock signal generation circuit 81. The clock signal generating circuit 81 has the same structure and operation as the clock signal generating circuit shown in FIG. The other parts are the same as those of the drive circuit 70 shown in FIG. 23, and the description thereof will be omitted.

FIG. 34 is a time chart when the thermal head shown in FIG. 32 is operated. Print data DATA and strobe signal STB in this time chart
The output timings of STB1, STB2, and selection signals SEL1 to SEL4 are the same as those in the time chart shown in FIG.

Further, as shown in FIG. 34, the clock signals CK1 to CK8 are output in synchronization with the data to be printed out of the printing data D. Select signal S in clock signal generation circuit 81 of drive element 80 in block B1
A clock signal CK corresponding to the print data of the block B1 is obtained by combining the output levels of EL1 and SEL2.
1, CK3, CK5, and CK7 are sequentially generated by the clock signal generation circuit 81 as described above, and output from the OR gate element 82 to the shift register SR. It is output from the drive element 82 of the block B2 to the shift register SR. The clock signals CK2, CK4, CK6, CK8 corresponding to the print data of the block B2 are obtained by combining the output levels of the selection signals SEL3, SEL4 in the clock signal generation circuit 81 of the drive element 80 of the block B2.
Are sequentially selected by the clock signal generation circuit 81 as described above, and the OR gate element 82 shifts to the shift register SR.
Is output to. The output timings of the clock signals CK1 to CK8 are shown in FIG.

When printing is performed on the thermal head shown in FIG. 32 based on the time chart shown in FIG. 34, the print image shown in FIG. 27 can be obtained.

(Embodiment 11) FIG. 35 is a circuit diagram showing the electrical construction of a thermal head of a printer according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 70. In FIG. 35, the individual electrodes 71 of the 256 heating resistors are connected to one drive circuit 70, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. Also, the heating resistor R1
~ R2048 is divided into blocks B1 and B2 as a whole, and selectively driven by corresponding strobe signals STB1 and STB2. Therefore, the strobe signal STB1 is input to each drive circuit of the block B1, and the strobe signal STB2 is input to each drive circuit of the block B2.
Is entered. Further, print data DATA, a clock signal CLK, control signals such as a trigger signal TRG, and the like are input to the drive circuits 70. The selection signals SEL1 and SEL2 are input to the drive circuits 70 of the B1 block, and the selection signals SEL are input to the drive circuits 70 of the B2 block.
3, SEL4 is input.

Further, the clock signal generation circuit 55a includes
Clock signal CK0, trigger signal TRG, selection signal SE
L1 and SEL2 are input, and the clock signal generation circuit 55
The clock signal CLK is output from a and applied to each drive circuit 70 of the block B1. Clock signal generation circuit 5
The clock signal CK0, the trigger signal TRG, and the selection signals SEL3 and SEL4 are input to 5b, and the clock signal CLK is output from the clock signal generation circuit 55b and applied to each drive circuit 70 of the block B2.

Drive circuit 70 is shown in FIG. 23, and clock signal generation circuits 55a and 55b are the same as clock signal generation circuit 55 shown in FIG. Therefore, since the configuration and operation of each circuit have been described above, the description thereof will be omitted.

FIG. 36 is a time chart when the thermal head shown in FIG. 35 is driven. This time chart is similar to the time chart shown in FIG. The difference between this time chart and the time chart shown in FIG. 24 is that in this time chart, the trigger signal TRG is output in synchronization with the clock signals CK1 to CK8. Since the trigger signal TRG has been described above, the description thereof will be omitted. The output timings of other signals are the same as the output timings of the time charts shown in FIGS.

When the thermal head shown in FIG. 35 is used to print based on the time chart shown in FIG. 36, the printed image shown in FIG. 27 can be obtained.

(Embodiment 12) FIG. 37 is a circuit diagram showing the electrical construction of a thermal head of a printer according to still another embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R2048 and a plurality of drive circuits 90. In FIG. 37, the individual electrodes 71 of the 256 heating resistors are connected to one drive circuit 90, and all the heating resistors R1 to R2048 are commonly connected to the common electrode VH. Also, the heating resistor R1
~ R2048 is divided into blocks B1 and B2 as a whole, and selectively driven by corresponding strobe signals STB1 and STB2. Therefore, the strobe signal STB1 is input to each drive circuit of the block B1, and the strobe signal STB2 is input to each drive circuit of the block B2.
Is entered. Further, print data DATA, control signals such as a clock signal CLK, and the like are input to each drive circuit 20. The selection signals SEL1 and SEL2 are input to the drive circuits 70 of the B1 block, and the selection signals SEL3 and SEL4 are input to the drive circuits 70 of the B2 block.

FIG. 38 shows a drive circuit 90 shown in FIG.
3 is a circuit diagram showing the electrical configuration of FIG. This drive circuit 90
23 is similar to the drive circuit 70 shown in FIG. 23, and corresponding parts are denoted by the same symbols. The difference between the drive circuit 90 and the drive circuit 70 is that the drive circuit 90 is provided with a clock signal generation circuit 92. This clock signal generation circuit 90 is equivalent to the clock signal generation circuit 5 shown in FIG.
Since the circuit configuration and operation are the same as those of No. 5, description will be omitted. The other parts are the same as those of the drive circuit 70 shown in FIG. 23, and the description thereof will be omitted. Also, reference numeral 91
The circuit block indicated by corresponds to the circuit block indicated by reference numeral 61 in FIG.

FIG. 39 is a time chart when the thermal head shown in FIG. 37 is operated. Print data DATA and strobe signal ST of this time chart
The output timings of B1, STB2, and the selection signals SEL1 to SEL4 are the same as those in the time chart shown in FIG.

Further, as shown in FIG. 39, the clock signals CK1 to CK4 are output in synchronization with the data to be printed out of the printing data D, and the trigger signal TRG is synchronized with the clock signals CK1 to CK4. Is output. Since the trigger signal TRG has been described above, its description is omitted.

The clock signals CK1 to CK4 corresponding to the print data of the block B1 are generated by the clock signal generation circuit 92 by the combination of the output levels of the selection signals SEL1 and SEL2 in the clock generation circuit 92 of the drive element 90 of the block B1. Are sequentially output to the shift register SR. Select signals SEL3, SE in the clock signal generation circuit 92 of the drive element 90 of the block B2
The clock signals CK1 to CK4 corresponding to the print data of the block B2 are output to the shift register SR by the clock signal generation circuit 76 according to the combination of the output levels of L4. The output timing of the clock signals CK1 to CK4 is shown in FIG.

Also, when the thermal head shown in FIG. 37 is used for printing on the basis of the time chart shown in FIG. 39, the printed image shown in FIG. 27 is obtained.

[0111]

As described above in detail, according to the present invention, the number of shift registers can be greatly reduced.
The scale of the drive circuit of the thermal head can be greatly reduced. Therefore, the printing apparatus can be downsized and the manufacturing cost can be reduced.

Further, according to the present invention, it is possible to obtain an image in which the adjacent printing dots are continuous, so that it is possible to prevent the occurrence of blurring and streaks due to the spacing between the adjacent printing dots. As a result, the quality of the printed image of the printing device can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an electrical configuration of a drive circuit 20.

FIG. 3 is a time chart for explaining a driving method of the thermal head shown in FIG.

4 is a time chart showing the contents of clock signals CK1 to CK4 shown in FIG.

5 is a circuit diagram of a clock signal generation circuit 25. FIG.

FIG. 6 is a print image obtained by the thermal head shown in FIG.

FIG. 7 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus that is another embodiment of the present invention.

FIG. 8 is a circuit diagram showing an electrical configuration of a drive circuit 32.

9 is a time chart for explaining a driving method of the thermal head shown in FIG.

FIG. 10 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 11 is a circuit diagram showing an electrical configuration of a clock signal generation circuit 40.

FIG. 12 is a circuit diagram showing an electrical configuration of clock signal generators 46 to 49.

FIG. 13 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 14 is a circuit diagram showing an electrical configuration of a drive circuit 50.

FIG. 15 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

16 is a time chart for explaining a driving method of the thermal head shown in FIG.

FIG. 17 is a circuit diagram showing an electrical configuration of a clock signal generation circuit 55.

FIG. 18 is a circuit diagram showing an electrical configuration of a clock signal generator 61 to which memories M11 to M14 are attached.

FIG. 19 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus which is still another embodiment of the invention.

FIG. 20 is a circuit diagram showing an electrical configuration of a drive circuit 65.

FIG. 21 is a time chart for explaining a driving method of the thermal head shown in FIG.

FIG. 22 is a time chart for explaining a method of driving the thermal head of the printing apparatus according to still another embodiment of the present invention.

FIG. 23 is a circuit diagram showing an electrical configuration of a drive circuit 70.

FIG. 24 is a time chart for explaining a driving method of the thermal head shown in FIG.

FIG. 25 is a diagram illustrating clock signals CK1 to CK shown in FIG.
8 is a time chart showing the contents of No. 8.

FIG. 26 is a diagram illustrating clock signals CK1 to CK shown in FIG.
8 is a time chart showing the contents of No. 8.

FIG. 27 is a print image obtained by the thermal head shown in FIG.

FIG. 28 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 29 is a circuit diagram showing an electrical configuration of a drive circuit 75.

FIG. 30 is a time chart for explaining a driving method of the thermal head shown in FIG. 28.

FIG. 31 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 32 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 33 is a circuit diagram showing an electrical configuration of a drive circuit 80.

FIG. 34 is a time chart for explaining a driving method of the thermal head shown in FIG. 32.

FIG. 35 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 36 is a time chart for explaining a driving method of the thermal head shown in FIG.

FIG. 37 is a circuit diagram showing an electrical configuration of a thermal head of a printing apparatus according to still another embodiment of the present invention.

FIG. 38 is a circuit diagram showing an electrical configuration of a drive circuit 90.

FIG. 39 is a time chart for explaining a driving method of the thermal head shown in FIG. 37.

FIG. 40 is a circuit diagram showing an electrical configuration of a thermal head of a conventional printing device.

FIG. 41 is a circuit diagram showing an electrical configuration of a conventional drive circuit 9.

42 is a time chart for explaining a method of driving the thermal head shown in FIG.

[Explanation of reference numerals] 20, 32, 50, 65, 70, 75, 80, 90 Driving circuit 23, 71 Individual electrode 25, 33, 40, 40a, 40b, 51, 55, 55
a, 55b, 76, 81, 92 Clock signal generation circuit 26-29, 41-44, 56-59 AND gate element 30, 34, 45, 72, 82 OR gate element 46-49, 60 Clock generator

Claims (3)

[Claims] 1. A plurality of heating resistors constituting a print pixel, a plurality of switching elements for controlling a current flowing through each heating resistor, a plurality of gate elements for opening and closing each switching element, and a print consisting of serial data. A shift register for inputting data in synchronization with a clock signal and converting it into parallel data, and the heating resistor are divided into column groups of a predetermined number n (where n is a natural number), and each column group is A drive gate element that connects n gate elements corresponding to the heating resistor in common and opens / closes the output from the shift register by a strobe signal from the outside, and a heating resistor of a plurality of row groups in common via the gate element. N selection gate elements to be connected, and a selection signal from the outside when data from the shift register is output to the driving gate element. Selection control means for driving a predetermined selection gate element by time-division driving a heating resistor commonly connected to the selection gate element via the gate element, and a clock signal corresponding to each heating resistor of the row group And a plurality of clock signal generating means for generating heat generating resistors, the plurality of clock signal generating means corresponding to the heat generating resistors to be time-division driven by the selection control means when the time-division driving is performed for each heat generating resistor of the row group. And a clock signal selecting means for selecting the clock signal. 2. A plurality of heating resistors forming a printing pixel, a plurality of switching elements for controlling a current flowing through each heating resistor, a plurality of gate elements for opening and closing each switching element, and a printing consisting of serial data. A shift register for inputting data in synchronization with a clock signal and converting it into parallel data, and the heating resistor are divided into column groups of a predetermined number n (where n is a natural number), and each column group is A drive gate element that connects n gate elements corresponding to the heating resistor in common and opens / closes the output from the shift register by a strobe signal from the outside, and a heating resistor of a plurality of row groups in common via the gate element. N selection gate elements to be connected, and a selection signal from the outside when data from the shift register is output to the driving gate element. And a selection control unit that drives a predetermined selection gate element by time-divisionally driving a heating resistor commonly connected to the selection gate element via the gate element. A plurality of storage means for storing a plurality of clock signal generation patterns for generating a clock signal corresponding to each resistor, based on the clock signal generation pattern of the storage means,
A plurality of clock signal generating means for generating a clock signal; and a plurality of clock signal generating means corresponding to the heating resistors driven in a time sharing manner when the selection control means drives the heating resistors in each row group in a time sharing manner. And a clock signal selecting means for selecting a clock signal from the thermal head. 3. A plurality of heating resistors forming a print pixel, a plurality of switching elements for controlling a current flowing through each heating resistor, a plurality of gate elements for opening and closing each switching element, and a print consisting of serial data. A shift register for inputting data in synchronization with a clock signal and converting it into parallel data, and the heating resistor are divided into column groups of a predetermined number n (where n is a natural number), and each column group is A drive gate element that connects n gate elements corresponding to the heating resistor in common and opens / closes the output from the shift register by a strobe signal from the outside, and a heating resistor of a plurality of row groups in common via the gate element. N selection gate elements to be connected, and a selection signal from the outside when data from the shift register is output to the driving gate element. And a selection control unit that drives a predetermined selection gate element by time-divisionally driving a heating resistor commonly connected to the selection gate element via the gate element. A plurality of storage means for storing a plurality of clock signal generation patterns for generating a clock signal corresponding to each resistor; and a time division drive when the heating resistors of the row group are time division driven by the selection control means. Generation pattern selection means for selecting a generation pattern of the clock signal corresponding to the heating resistor from a plurality of clock signal generation patterns stored in the storage means, and sequentially based on the clock signal generation pattern selected by the generation pattern selection means A thermal head comprising: a clock signal generating means for generating a clock signal.