JPH0693456B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device. The present invention is
For example, it can be applied to LSI manufacturing process technology and the like to obtain a good flat surface.

[Outline of Invention]

The present invention relates to a method for manufacturing a semiconductor device in which an insulating film is formed on a wiring layer formed on a substrate and planarized, in which heating of the insulating film that can flow by heat treatment and etching after forming a mask layer are performed. In combination, it achieves further flattening than before and solves the problems of the conventional flattening technology.

[Conventional technology]

Conventionally, for example, when a multilayer wiring of two or more layers is formed in an LSI manufacturing technology, for the reason of facilitating the processing of the wiring of the second layer or more and preventing disconnection of the wiring and improving reliability, Flattening, that is, improvement of the step shape of the insulating film and the lower layer wiring portion formed on the substrate has been performed. For example, as the step, as shown in FIG. 11, there are a polysilicon gate electrode 2 and a polysilicon wiring 3 formed on a silicon substrate 1. 6 is a field area (locos). Here, improvement of the step shape means reduction of height difference of the step, taper of the step, and the like.

Conventionally, as a planarization technique, there are a reflow method and a RIE low temperature planarization method.

The reflow method is used in a process in which high temperature heat treatment can be used. That is, when the processing can be performed at a temperature of about 800 to 900 ° C. or higher, the insulating film 4 which can be fluidized by heat treatment is used to improve the step difference on the substrate 1. However, in the conventional reflow method,
Since only the softening phenomenon of the insulating film 4 due to the high temperature heat treatment is used, unevenness due to the influence of the step may remain on the insulating film 4 as shown in FIG. For example, the surface A and the surface B in FIG. 9 do not coincide with each other, and sufficient planarization cannot be achieved. For this reason,
To form the field region 6, instead of the general Locos method,
In some cases, the Flat Locos method cannot but be used. Such unevenness is a serious problem particularly in a fine semiconductor structure, and for example, in the case of a wiring fined to 1.0 μm rule or less or a multilayer wiring, the planarization is not sufficient by the reflow method.

On the other hand, the low-temperature flattening method by RIE may generate crater-like surface roughness C on the surface after RIE flattening, depending on the masking material used and the type of insulating film 4 to be flattened. (For example, when some kind of photoresist is used as a masking material and PSG, that is, phosphosilicate glass is used as an insulating film. Autumn 1984, Proceedings of Japan Society of Applied Physics P470, 12P-D-3, Nishimoto et al. reference). When flattening is achieved only by RIE, until the surface is sufficiently flattened, the insulating film, the interface with the lower layer,
Furthermore, RIE-induced defects may occur in the lower layer and the substrate. In FIG. 10, reference numerals 21 and 31 are SiO ₂ sidewalls.

Further, as a method of using the RIE and the reflow method together, Japanese Patent Laid-Open No.
There is the following technique described in the 8-216443 publication. In this technique, as shown in FIG. 2, a thick CVD SiO ₂ layer 6B is formed on the _second polysilicon layer 2B on the lower first polysilicon layer 2A on the SiO ₂ insulating film 7 on the substrate 1. A resist is applied on the lever and RIE is performed to remove C on the second polysilicon layer 2B.
The etching is stopped before the VDSiO ₂ layer 6B disappears. Strip the resist. Then, the BPSG layer 4 is formed on the CVD SiO ₂ layer 6B.
A is formed and melted by heat treatment, and Al is deposited on this BPSG layer 4A.
Form layer 2C. However, in this known technique, the same problem as shown in FIG. 9 occurs in the reflow method of the BPSG layer 4A, and the steps indicated by a and b on the surface inevitably remain.

At the time of RIE, the problem of surface roughness shown in FIG. 10 occurs,
This is reflected in the upper flow film (BPSG layer 4A).

In addition, this technique requires a two-layer process of RIE of SiO ₂ 6B and reflow of the BPSG layer 4A, making it inevitable to thicken the film and complicating the process.

[Problems to be solved by the invention]

The present invention solves the above-mentioned problems of the prior art, that is, unevenness corresponding to steps may remain, surface roughness may occur, and defects may occur, and a sufficient flatness without unevenness or roughness may be provided. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which has a high degree of precision and can be applied to a semiconductor having a fine structure and which can suppress the occurrence of defects.

[Technical means and actions for solving problems]

The present invention relates to a method of manufacturing a semiconductor device in which an insulating film is formed on a wiring layer formed on a substrate and planarized, and (a) a step of forming a fluidizable insulating film on the wiring layer by heat treatment, (B) a step of forming a mask layer on the flowable insulating film, etching the entire surface to flatten the surface, and then removing the mask layer; and (c) the step (b), followed by the flow. A method of manufacturing a semiconductor device, comprising the step of flattening the uneven portion of the surface of the flowable insulating film generated by the etching step of the step (b) by reflowing a possible insulating film by heat treatment, By adopting this configuration, the above object is achieved.

This will be described with reference to FIGS. 3 to 7 showing embodiments to be described later in detail. A wiring layer (specifically, a polysilicon gate electrode 2, A flowable insulating film 4 is formed on the polysilicon wiring layer 3 and the like) by a heat treatment so as to exemplify FIG. 4 (step a in FIG. 1). Next, a mask layer 5 is formed as shown in FIG. 5, and the entire surface of the mask layer 5 is removed to remove the mask layer 5 and the surface is flattened to a state as shown in FIG. 6 (step b in FIG. 1). Then, the insulating film 4 is heat-treated to obtain a flat surface shape as shown in FIG. 7 (step c in FIG. 1. In the example of FIG. 7, since the contact holes 11 and 12 are formed in advance, this shoulder The part is also tapered).

Since the present invention comprises the above technical means, even if the formed insulating film 4 has irregularities, a substantially flat surface shape can be obtained by forming the next mask layer 5 and etching the entire surface. Even if crater-like roughness remains on the surface, the insulating film 4 is heat-treated next, so that the surface shape is reflowed and sufficiently flattened. Although using RIE for etching may induce defects,
In this invention, since heat treatment is performed later, this can be reduced or eliminated (annealed out).

As described above, according to the present invention, the conventional reflow method may leave unevenness, but this problem is solved, the surface flatness is improved, and the processing accuracy of the wiring formed thereon is improved. Is improved, processing becomes easier, and it is also advantageous in preventing step disconnection. Of course, the special Locos method may not be used.
Further, the possibility that surface roughness may occur during planarization by the conventional RIE method can be reduced, the surface flatness is improved, and the same effect as described above is brought about. In addition, defects that may be caused by RIE can be eliminated or reduced.

Example of Invention

 Examples of the present invention will be described below.

The following examples describe the present invention by so-called LDD (Lightly D
This is applied to a MOS-FET with an oped drain structure. LD
The D-structure is suitable for miniaturization, but as described above, planarization is important for an LSI having a fine structure, so the present invention was applied to such an LSI process.

FIG. 3 shows a stage in which wiring layers such as the polysilicon gate electrode 2 and the polysilicon wiring layer 3 are formed on the substrate 1 in the LDD-NMOS-FET of this example. This drain region 8 is
High-concentration portion 81 with high impurity doping concentration (indicated by n ⁺ in the figure)
And a low-concentration portion 82 (denoted by n ⁻ in the figure) having a low doping concentration, and the low-concentration portion 82 suppresses the adverse effect of hot electrons. Due to the manufacturing process, the source region 9 also includes the high concentration portion 91 and the low concentration portion 92. Sidewall spacers 21 of SiO ₂ are formed on both side walls of the gate electrode 2 to form the low concentration portions 82 and 92. Sidewall spacers 31 of SiO ₂ are also formed on the polysilicon wiring layer 3. Reference numeral 6 is a field region formed on the substrate 1. In this embodiment, the field region 6 is formed with a SiO ₂ thickness of 5000 Å by the LOCOS method using a normal Si ₃ N ₄ mask method. Reference numeral 7 is a gate insulating film. This gate insulating film 7 was formed with a thickness of SiO ₂ 200Å.
Polysilicon gate electrode 2 and polysilicon wiring layer 3
Was formed by phos-doped with a sheet resistance of 30 Ω / □ and a thickness of 3000 Å and patterned by RIE. Impurity distribution of Si inside of the LDD structure, the drain region 8, the low-density portion of the source region 9 (n ^-
Parts) 82 and 92 are made by doping phosphorus with a dose amount of 3 × 10 ¹³ cm ^-2 and 60 KeV, and the high concentration part (n ⁺ part) has an arsenic dose amount of 5
It is formed by doping with × 10 ¹⁵ om ⁻² 70 KeV, and is formed by annealing these impurities at 940 ° C. after ion implantation.

Although not shown, the lower portion of the field region 6 is doped with a P-type impurity for a channel stopper, and the channel portion and the lower portion of the channel are doped with an impurity for controlling a threshold voltage and an impurity for preventing punch-through, respectively. .

FIG. 4 shows an insulating film 4 which can be flowed by heat treatment on the wiring layer (polysilicon electrode 2 or polysilicon wiring layer 3).
The state in which the is formed is shown. In this embodiment, AsSG (arsenic silicate glass) is used as the material of the insulating film 4,
An As concentration of 10 wt% was used. This insulating film 4 is CVD
The film thickness was set to 2.0 μ.

Although AsSG is used as the material of the interlayer insulating film 4 here, PSG (phosphorus silicate glass) or doped SiO ₂ (doped-S) such as BPSG in which PSG is further doped with boron to lower the melting point is used.
iO ₂ ) can be used. In addition, organic substances such as polyimide can also be used by adjusting the heat treatment temperature.

Next, as shown in FIG. 5, a mask layer 5 for etching and flattening is formed. In this embodiment, a masking material was formed by spin-on coating a photoresist on the entire surface of the substrate and baking at 180 ° C. for 30 minutes. The thickness of the mask layer 5 was 1.0 μm. As this photoresist, for example, OFPR- manufactured by Tokyo Ohka Co., Ltd.
800 can be used.

Thus, the mask layer 5 is formed, the entire surface is etched to remove the mask layer 5, and the surface is flattened. That is,
The mask layer 5 and the insulating film 4 are simultaneously etched by RIE in the state shown in FIG. 5 so that the mask layer 5 is removed and the surface of the insulating film 4 becomes almost completely flat. The state after this etching is shown in FIG. RI
As the etching gas for E, for example, a mixed gas of CHF ₃ and O ₂ can be used.

In this embodiment, thereafter, contact holes 11 and 12 to the source region 9 and the drain region 8 are formed. The contact holes 11 and 12 can be formed by RIE using a photoresist mask.

Next, a step of heat treating the insulating film 4 is performed. FIG. 7 shows the state after this heat treatment step. That is, after forming the mask layer 5 and flattening the surface by etching, in this embodiment, heat treatment was performed at 900 ° C. in a N ₂ atmosphere for 10 to 30 minutes. As a result, the insulating film 4 made of SsSG is reflowed, and the surface planarized by etching is further planarized. As a result, even if crater-like roughness remains on the surface only by etching, this roughness can be removed or reduced. In addition, defects that may be introduced during etching, for example, defects induced by RIE are annealed out and removed by this heat treatment.

As described above, the heat treatment process eliminates the surface step and the surface roughness of the insulating film 4, so that the insulating film 4 can be completely planarized. Moreover, even if a defect occurs due to RIE or the like, it can be removed.

Moreover, in this embodiment, as shown in FIG.
As for 2 as well, this heat treatment rounds the upper edge and forms a taper.

FIG. 8 shows a state in which the second wiring is formed in this embodiment. After the heat treatment, a wiring material is deposited by vapor deposition or sputtering to form a pattern, thereby forming a second wiring layer.
13, 14, 15, etc. are formed.

In the above-described embodiment, as the planarization method by RIE, the method of forming the sidewall spacers 21 and 31 on the sidewalls of the polysilicon gate electrode 2 and the polysilicon wiring layer 3 in advance is used. Since the semiconductor device of this embodiment is an LDD-MOS-FET, the sidewall spacer 21 of SiO ₂ has already been formed on the gate electrode 2 for forming the LDD, and this method can be used without adding a new step. Can be used. (SiO ₂ sidewall spacer 31 of polysilicon wiring layer 3
Can be formed in the same process as the sidewall spacer 21 of the gate electrode 2). It is considered that such an LDD structure will be widely adopted in the future, and in this case, it can be said that the present invention can be preferably applied.

However, the use of the above sidewall spacers is not essential for planarization by RIE, and naturally the present invention is applied to other than the LDD structure, and the sidewall spacers are not used.
The present invention is also effective when performing RIE flattening and heat treatment (reflow).

Of course, the present invention is not limited to the embodiments described above.

〔The invention's effect〕

As described above, according to the method for manufacturing a semiconductor device of the present invention, the unevenness due to the influence of the lower layer does not remain on the surface, the surface roughness can be prevented, the surface flatness is improved, and the processing accuracy of the wiring formed thereon is improved. However, the processing is facilitated, and it is advantageous only in preventing step breakage, does not require special processing means, and has the effect that defects that may occur due to RIE or the like can be prevented or suppressed.

[Brief description of drawings]

FIG. 1 is a process diagram showing the present invention. Figure 2 shows
It is a figure showing a problem of a prior art. FIGS. 3 to 8 are sectional views showing the first embodiment of the present invention in the order of manufacturing steps. 9 and 10 are sectional views of a conventional example. FIG. 11 is a sectional view of a general semiconductor device. 1 ... Substrate, 2 ... Wiring layer (gate electrode), 3 ... Wiring layer (polysilicon wiring layer), 4 ... Insulating film, 5 ... Mask layer, 6 ... Field region, 7 ... Gate insulation Membrane, 8
…… Drain region, 9 …… Source region, 81,91 …… High concentration part, 82,92 …… Low concentration part.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which an insulating film is formed on a wiring layer formed on a substrate to planarize the insulating film, the method comprising: (a) forming a fluid insulating film on the wiring layer by heat treatment; , (B) a step of forming a mask layer on the flowable insulating film, etching the entire surface to flatten the surface, and then removing the mask layer, and (c) the step (b) followed by the flow step. A method of manufacturing a semiconductor device, comprising: reflowing a possible insulating film by heat treatment to flatten the uneven portion of the surface of the flowable insulating film caused by the etching step of the step (b).