JPH0691329B2 - Power supply system - Google Patents

Power supply system

Info

Publication number
JPH0691329B2
JPH0691329B2 JP58052383A JP5238383A JPH0691329B2 JP H0691329 B2 JPH0691329 B2 JP H0691329B2 JP 58052383 A JP58052383 A JP 58052383A JP 5238383 A JP5238383 A JP 5238383A JP H0691329 B2 JPH0691329 B2 JP H0691329B2
Authority
JP
Japan
Prior art keywords
power supply
package
platter
pins
packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58052383A
Other languages
Japanese (ja)
Other versions
JPS59178512A (en
Inventor
則夫 千石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58052383A priority Critical patent/JPH0691329B2/en
Publication of JPS59178512A publication Critical patent/JPS59178512A/en
Publication of JPH0691329B2 publication Critical patent/JPH0691329B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Direct Current Feeding And Distribution (AREA)
  • Power Sources (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 電源給電方式に関し、特にプラッタ(大形のプリント配
線回路基板)に電子部品を搭載した複数のパッケージ
(小形のプラント配線回路基板)をコネクタを介して接
続する構造におけるプラッタからパッケージへの電源給
電方式に関する。
Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a power supply system, and in particular, a plurality of packages (small plant wiring circuit boards) in which electronic parts are mounted on platters (large printed wiring circuit boards) via connectors. The present invention relates to a power supply system for supplying power from a platter to a package in a structure of connecting with each other.

〔発明の背景〕[Background of the Invention]

第1図はデータ処理装置における一般的な構造を示して
いる。一般にプラッタ10に複数のパッケージ14A,14B,14
Cがコネクタ12を介して接続される。コネクタ12の各ピ
ン16はプラッタ10とパッケージ14との間の論理信号路お
よびプラッタ10からパッケージ14の給電路となる。従来
この種の構造においては、標準化がはかられており、プ
ラッタ10からパッケージ14への給電路数(給電のために
配置されたコネクタのピンの本数)は一定にされてい
る。しかし、各パッケージの負荷電流量は異なってお
り、各パッケージにおけるコネクタの接触抵抗による電
圧降下は一様でなく、よって各パッケージへの給電電圧
が不均一になるという問題があった。
FIG. 1 shows a general structure of a data processing device. Generally platter 10 has multiple packages 14A, 14B, 14
C is connected via connector 12. Each pin 16 of the connector 12 serves as a logic signal path between the platter 10 and the package 14 and a power supply path from the platter 10 to the package 14. Conventionally, this type of structure has been standardized, and the number of power supply paths from the platter 10 to the package 14 (the number of pins of the connector arranged for power supply) is constant. However, the load current amount of each package is different, and the voltage drop due to the contact resistance of the connector in each package is not uniform, so that there is a problem that the power supply voltage to each package becomes uneven.

〔発明の目的〕[Object of the Invention]

本発明の目的は各プラッタへの給電電圧をほぼ均一にす
る電源給電方式を提供することにある。
An object of the present invention is to provide a power supply system that makes the supply voltage to each platter substantially uniform.

〔発明の概要〕[Outline of Invention]

本発明は、プラッタと、プラッタの内層に設けられた電
源層と接続する複数の電源給電用ピンを備え、プラッタ
の一方の面に装着される複数のコネクタと、電子部品が
搭載され、表面に電源給電用パターンを備え、複数の電
源給電用ピンと電源給電用パターンとが接触するよう一
端が各コネクタに装着される複数のパッケージとを有
し、複数の電源給電用ピン及び電源給電用パターンを介
してプラッタから各パッケージに電源給電が行われる電
源給電方式において、各パッケージは、前記複数の電源
給電用ピンに対応して設けられ、各パッケージの内層に
設けられた電源層に接続する複数のスルーホールを有
し、各パッケージの負荷電流量に応じて、複数のスルー
ホールの全部若しくは所定のスルーホールが電源給電用
パターンと接続されていることを特徴とする。
The present invention includes a platter and a plurality of power supply pins that are connected to a power supply layer provided on an inner layer of the platter, and a plurality of connectors mounted on one surface of the platter and electronic components are mounted on the surface. A power supply pattern is provided, and a plurality of power supply pins and a plurality of packages each having one end attached to each connector so that the power supply patterns are in contact with each other are provided. In a power supply system in which power is supplied from a platter to each package via a package, each package is provided corresponding to the plurality of power supply pins, and is connected to a power supply layer provided in an inner layer of each package. It has through holes, and all or a predetermined number of through holes are connected to the power supply pattern according to the load current amount of each package. And wherein the Rukoto.

〔発明の実施例〕Example of Invention

以下、本発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第2図は1枚のパッケージ14を示す。コネクタ12は多数
のピン16のうち、例えば16Aで示す20本のピンが電源給
電のためのピンであり、プラッタ10の電源層と電気的に
接続されている。他の論理信号用のピンはプラッタ10の
論理信号層と電気的に接続されている。電源給電用ピン
16Aはパッケージ14上の電源給電用のパターン24に接触
され、電気的に接続される。パターン24には、スルーホ
ール20および22が設けられているものと、スルーホール
20のみ設けられているものがある。スルーホール22はパ
ッケージ14の内層に設けられた電源層に接続されてい
る。従って第2図の例では、図の上から1番目、3番
目、下から1番目、3番目の給電用ピン16Aのみがパッ
ケージ14の電源層に接続され、図の上から2番目および
下から2番目の給電用ピン16Aはパッケージ14の電源層
には接続されない。
FIG. 2 shows a single package 14. In the connector 12, of the many pins 16, for example, 20 pins indicated by 16A are pins for power supply, and are electrically connected to the power layer of the platter 10. The pins for other logic signals are electrically connected to the logic signal layer of the platter 10. Power supply pin
16A is brought into contact with and electrically connected to the power supply pattern 24 on the package 14. Pattern 24 with through holes 20 and 22 and through holes
Some have only 20. The through hole 22 is connected to the power supply layer provided in the inner layer of the package 14. Therefore, in the example of FIG. 2, only the first, third, and first and third feeding pins 16A from the top of the drawing are connected to the power supply layer of the package 14, and the second and the top from the top of the drawing are connected. The second power supply pin 16A is not connected to the power layer of the package 14.

全てのパッケージにおいて、コネクタの給電用ピン16A
の全てがパッケージ14の電源層に接続される従来例によ
ると、例えば各ピンの接触抵抗を10mΩとし、各コネク
タ12の給電用ピン数を20として、3つのパッケージ14A,
14B,14Cの各負荷電流量を夫々70A,35A,10Aとした場合各
コネクタによる夫々の総電圧降下はパッケージ14Aで35m
V、パッケージ14Bで17.5mV、パッケージ14Cで5mVとな
り、パッケージ間で30mVの差が生じることになる。
16A pin for powering the connector in all packages
According to the conventional example in which all are connected to the power supply layer of the package 14, for example, the contact resistance of each pin is 10 mΩ, the number of power supply pins of each connector 12 is 20, and three packages 14A,
When the load current for 14B and 14C is 70A, 35A and 10A respectively, the total voltage drop due to each connector is 35m for package 14A.
V, 17.5 mV for package 14B and 5 mV for package 14C, resulting in a 30 mV difference between packages.

しかるに本実施例においては、第2図に示すように、給
電用ピン16Aからパッケージ14の電源層への給電路数を
各パッケージの負荷電流量に応じて設定することによ
り、各パッケージへの給電電圧をほぼ均一化する。
However, in this embodiment, as shown in FIG. 2, the number of power supply paths from the power supply pin 16A to the power supply layer of the package 14 is set in accordance with the load current amount of each package to supply power to each package. Make the voltage almost uniform.

このような調整に基づいて前例を参照して具体的に説明
すれば、給電用ピン数を20として、パッケージ14A,14B,
14Cのピン16Aによる給電路数を夫々20(全ての給電用ピ
ンをパッケージの電源層に接続),10,3に設定すること
により、電圧降下を夫々35mV,35mV,35mVと殆んど均一化
することができる。
Based on such adjustment, a specific explanation will be given with reference to the previous example, assuming that the number of power supply pins is 20, the packages 14A, 14B,
By setting the number of power supply paths by pin 16A of 14C to 20 (all power supply pins are connected to the power supply layer of the package), 10 and 3, the voltage drop is almost uniform at 35mV, 35mV and 35mV respectively. can do.

第3図は第2図のIII-III線断面図を示す。給電用ピン1
6Aはパターン24に接触され、スルーホール22を介して内
層の電源層28に接続されている。第4図は第2図のIV-I
V線断面図を示す。給電用ピン16Aはパターン24に接触さ
れるが、電源層28に接続されたスルーホール22には、パ
ターン24が接続されておらず、このピンは給電路となら
ない。なお、スルーホール20,22にコンデンサ30を取付
けることにより、直流的には電流は流れず、交流的には
内層接続と同等の特性が得られるようにしてもよい。
FIG. 3 is a sectional view taken along line III-III in FIG. Power supply pin 1
6A is in contact with the pattern 24 and is connected to the inner power supply layer 28 through the through hole 22. Figure 4 shows IV-I in Figure 2.
A sectional view taken along line V is shown. The power supply pin 16A is in contact with the pattern 24, but the pattern 24 is not connected to the through hole 22 connected to the power supply layer 28, and this pin does not serve as a power supply path. By attaching the capacitor 30 to the through holes 20 and 22, it is possible that a current does not flow in terms of direct current and the same characteristics as in the inner layer connection are obtained in terms of alternating current.

〔発明の効果〕〔The invention's effect〕

以上のように、本発明によれば各パッケージの負荷電流
に差が生じる場合でも、各コネクタにおける電圧降下を
均一化できるので、各パッケージにほぼ均一な電圧の供
給を行なうことができ、特に積層基板を用いる高密度の
回路構成等の利用上、優れた効果が奏される。
As described above, according to the present invention, even if there is a difference in the load current of each package, the voltage drop in each connector can be made uniform, so that it is possible to supply a substantially uniform voltage to each package, and in particular, stacking An excellent effect is exhibited in utilizing a high-density circuit configuration using a substrate.

【図面の簡単な説明】[Brief description of drawings]

図は本発明の一実施例を示すもので、第1図は装置全体
を示す概略斜視図、第2図は概略正面図、第3図は第2
図のIII-III線拡大断面図、第4図は第2図のIV-IV線拡
大断面図である。 10……プラッタ、12……コネクタ、 14……パッケージ、16……ピン、 16A……給電用ピン。
FIG. 1 shows an embodiment of the present invention. FIG. 1 is a schematic perspective view showing the entire apparatus, FIG. 2 is a schematic front view, and FIG.
The III-III line enlarged sectional view of a figure, and FIG. 4 are the IV-IV line enlarged sectional views of FIG. 10 …… platter, 12 …… connector, 14 …… package, 16 …… pin, 16A …… feeding pin.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H02J 1/00 306 B 7509−5G ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H02J 1/00 306 B 7509-5G

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】プラッタと、前記プラッタの内層に設けら
れた電源層と接続する複数の電源給電用ピンを備え、前
記プラッタの一方の面に設けられた複数のコネクタと、
電子部品が搭載され、表面に電源給電用パターンを備
え、前記複数の電源給電用ピンと前記電源給電用パター
ンとが接触するよう一端が前記複数のコネクタの各々に
装着された複数のパッケージとを有し、前記複数の電源
給電用ピン及び前記電源給電用パターンを介して前記プ
ラッタから各パッケージに電源給電が行われる電源給電
方式において、 前記各パッケージは、前記複数の電源給電用ピンに対応
して設けられ、前記各パッケージの内層に設けられた電
源層に接続する複数のスルーホールを有し、前記各パッ
ケージの負荷電流量に応じて、前記複数のスルーホール
の全部若しくは所定のスルーホールが前記電源給電用パ
ターンと接続されていることを特徴とする電源給電方
式。
1. A platter, and a plurality of connectors provided on one surface of the platter, comprising a plurality of power supply pins connected to a power layer provided in an inner layer of the platter,
An electronic component is mounted, a power supply pattern is provided on the surface, and a plurality of packages each having one end attached to each of the plurality of connectors so that the plurality of power supply pins are in contact with the power supply pattern are provided. However, in a power supply system in which power is supplied from the platter to each package through the plurality of power supply pins and the power supply pattern, each package corresponds to the plurality of power supply pins. Each of the plurality of through holes is provided with a plurality of through holes connected to a power supply layer provided in an inner layer of each of the packages, and all of the plurality of through holes or a predetermined through hole are provided according to the load current amount of each of the packages. A power supply system that is connected to a power supply pattern.
JP58052383A 1983-03-30 1983-03-30 Power supply system Expired - Lifetime JPH0691329B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58052383A JPH0691329B2 (en) 1983-03-30 1983-03-30 Power supply system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58052383A JPH0691329B2 (en) 1983-03-30 1983-03-30 Power supply system

Publications (2)

Publication Number Publication Date
JPS59178512A JPS59178512A (en) 1984-10-09
JPH0691329B2 true JPH0691329B2 (en) 1994-11-14

Family

ID=12913279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58052383A Expired - Lifetime JPH0691329B2 (en) 1983-03-30 1983-03-30 Power supply system

Country Status (1)

Country Link
JP (1) JPH0691329B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5911477Y2 (en) * 1979-09-26 1984-04-09 富士通株式会社 motherboard assembly

Also Published As

Publication number Publication date
JPS59178512A (en) 1984-10-09

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