JPH0691227B2 - A method of manufacturing a semiconductor device - Google Patents

A method of manufacturing a semiconductor device

Info

Publication number
JPH0691227B2
JPH0691227B2 JP59023178A JP2317884A JPH0691227B2 JP H0691227 B2 JPH0691227 B2 JP H0691227B2 JP 59023178 A JP59023178 A JP 59023178A JP 2317884 A JP2317884 A JP 2317884A JP H0691227 B2 JPH0691227 B2 JP H0691227B2
Authority
JP
Japan
Prior art keywords
mos
cmos
manufacturing
soi
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59023178A
Other languages
Japanese (ja)
Other versions
JPS60167364A (en
Inventor
耕司 千田
義光 広島
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP59023178A priority Critical patent/JPH0691227B2/en
Publication of JPS60167364A publication Critical patent/JPS60167364A/en
Publication of JPH0691227B2 publication Critical patent/JPH0691227B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関するものである。 DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL FIELD The present invention relates to a method of manufacturing a semiconductor device.

従来例の構成とその問題点 近年、絶縁基板上に形成された相補型MOS(C−MOS)が重要視されてきた。 Conventional structure and problems in recent years, formed on an insulating substrate a complementary MOS (C-MOS) have been emphasized.

以下、図面を参照しながら、従来のSOI−CMOSについて説明を行う。 Hereinafter, with reference to the drawings, a description is given of a conventional SOI-CMOS.

第1図は従来のSOI−CMOSの模式的断面図を示すものである。 Figure 1 shows a schematic cross-sectional view of a conventional SOI-CMOS. 第1図において、1は絶縁基板、2はPチャンネル型MOS(P−MOS)、3はNチャンネル型MOS(N−MO In Figure 1, 1 denotes an insulating substrate, 2 is P-channel type MOS (P-MOS), 3 is an N-channel type MOS (N-MO
S)、4はゲート電極、5は配線である。 S), 4 denotes a gate electrode, 5 is a wiring.

以上のように絶縁基板1上に作られたSOI−CMOSは、基板との寄生容量が小さいため高速動作が可能である。 SOI-CMOS made on the insulating substrate 1 as described above, can operate at high speed because the parasitic capacitance is small and the substrate. さらに、ラッチアップがない,高耐圧,ソフトエラーに強い、といった特長を持っている。 In addition, there is no latch-up, a high breakdown voltage, strong to soft error, and has features such as.

しかし、上記のような構造のSOI−CMOSを製作するには、絶縁基板上に単結晶を成長させてMOSのチャネル領域を形成しなければならない。 However, to fabricate the SOI-CMOS structure as described above, it must form a MOS channel region by growing a single crystal on an insulating substrate. ところが、絶縁基板上に良質の単結晶を成長させるのは、困難である。 However, to grow a high quality single crystal on an insulating substrate is difficult.

発明の目的 本発明は上記欠点に鑑み、単結晶基板に形成したC−MO Object This invention has been made in view of the above drawbacks, C-MO formed in the single crystal substrate
SをSOI−CMOSにするための半導体装置の製造方法を提供するものである。 There is provided a method of manufacturing a semiconductor device for the S to SOI-CMOS.

発明の構成 この目的を達成するために本発明の半導体装置の製造方法は、単結晶基板に作ったC−MOSを絶縁基板に接着し、前記単結晶基板の不必要な部分を除去することから構成されている。 The method of manufacturing a semiconductor device of the present invention configured to achieve this object of the present invention, since the bonding the C-MOS made a single crystal substrate an insulating substrate, to remove unnecessary portions of the single crystal substrate It is configured.

この構成により、絶縁基板上に単結晶を成長させるプロセスが不必要になり、容易にSOI−CMOSを製作することが出来る。 With this configuration, the process of growing a single crystal on the insulating substrate becomes unnecessary, it is possible to easily fabricate the SOI-CMOS.

実施例の説明 以下、図面を用いて、本発明の一実施例を詳細に説明する。 Description of the embodiments below, with reference to the drawings, a description will be given of an embodiment of the present invention in detail.

先ず、第2図に示すように、標準的なC−MOS半導体プロセスで、N型シリコン基板11にC−MOSを形成する。 First, as shown in FIG. 2, in standard C-MOS semiconductor process to form a C-MOS to N-type silicon substrate 11.
第2図において、12はP−MOS、13はN−MOS、14はゲート電極、15は配線である。 In Figure 2, 12 is P-MOS, 13 N-MOS, 14 denotes a gate electrode, 15 denotes a wiring.

次に、第3図に示すように、第2図のN型シリコン基板 Next, as shown in FIG. 3, the second view N-type silicon substrate
11に形成されたC−MOSをガラス基板のような絶縁体21 11 as a glass substrate formed C-MOS in an insulator 21
に接着する。 To adhere to. さらに、第3図に示すようにC−MOSの活性領域だけが残るように、N型シリコン基板11の不必要な領域を研磨または、エッチングにより除去する。 Further, as only the active region of the C-MOS as shown in FIG. 3 remains, polishing unnecessary regions of N-type silicon substrate 11 or is removed by etching.

次に、第4図に示すようにホトリソグラフイによるレジストパタン41を用いて、不必要なシリコンをエッチングしてP−MOS42,N−MOS43を島状に分離する。 Next, using the resist pattern 41 by photolithographic as shown in Figure 4, to separate the P-MOS 42, N-MOS 43 in an island shape by etching the unnecessary silicon.

最後に、第5図に示すように、保護膜51で素子を保護して、SOI−CMOSが完成する。 Finally, as shown in FIG. 5, to protect the element with the protective film 51, SOI-CMOS is completed.

以上のように本実施例によれば、標準的なシリコン基板に形成されたC−MOSを、SOI−CMOSに変えることができる。 According to this embodiment, as described above, a CMOS formed in a standard silicon substrate, can be varied in SOI-CMOS.

なお、本実施例ではSOI−CMOSであったが、SOI−CMOS,S While this embodiment was SOI-CMOS, SOI-CMOS, S
OI−PMOSでもよい。 It may be OI-PMOS.

発明の効果 以上のように本発明は、単結晶基板に形成されたC−MO The present invention as described above the effect of the invention, C-MO formed on the single crystal substrate
Sを絶縁基板に接着して、単結晶基板の不必要な部分を除去してSOI−CMOSを製造することができ、その実用的効果は大なるものがある。 By bonding a S to the insulating substrate, to remove unnecessary portions of the single crystal substrate can be manufactured SOI-CMOS, in its practical effect is there is a large becomes.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図は従来のSOI−CMOSの模式的断面図、第2図〜第5図は、本発明の一実施例のSOI−CMOSの製造工程を示す断面図である。 Figure 1 is a schematic sectional view of a conventional SOI-CMOS, FIG. 2-FIG. 5 is a sectional view showing a SOI-CMOS manufacturing process of an embodiment of the present invention. 12,42……P−MOS、13,43……N−MOS、14……ゲート電極、15……配線、21……絶縁基板、51……保護膜。 12,42 ...... P-MOS, 13,43 ...... N-MOS, 14 ...... gate electrode, 15 ...... wiring, 21 ...... insulating substrate, 51 ...... protective film.

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】結晶基板に形成した素子の面に絶縁基板を接着する工程と、素子領域だけが残るように結晶基板を研磨またはエッチングにより除去する工程と、素子を島状に分離する工程からなることを特徴とする半導体装置の製造方法。 And 1. A process of bonding an insulating substrate on the surface of the element formed on the crystal substrate, a step of removing by polishing or etching the crystal substrate so that only the element region is left, the step of separating the elements into islands the method of manufacturing a semiconductor device characterized by comprising.
JP59023178A 1984-02-09 1984-02-09 A method of manufacturing a semiconductor device Expired - Lifetime JPH0691227B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59023178A JPH0691227B2 (en) 1984-02-09 1984-02-09 A method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59023178A JPH0691227B2 (en) 1984-02-09 1984-02-09 A method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
JPS60167364A JPS60167364A (en) 1985-08-30
JPH0691227B2 true JPH0691227B2 (en) 1994-11-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59023178A Expired - Lifetime JPH0691227B2 (en) 1984-02-09 1984-02-09 A method of manufacturing a semiconductor device

Country Status (1)

Country Link
JP (1) JPH0691227B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2566175B2 (en) * 1990-04-27 1996-12-25 セイコー電子工業株式会社 Semiconductor device and manufacturing method thereof
US6067062A (en) * 1990-09-05 2000-05-23 Seiko Instruments Inc. Light valve device
TW214603B (en) * 1992-05-13 1993-10-11 Seiko Electron Co Ltd Semiconductor device
JP3526058B2 (en) * 1992-08-19 2004-05-10 セイコーインスツルメンツ株式会社 Semiconductor device for light valve
KR100632136B1 (en) * 1996-03-12 2006-11-30 코닌클리케 필립스 일렉트로닉스 엔.브이. Method of manufacturing a hybrid integrated circuit

Also Published As

Publication number Publication date
JPS60167364A (en) 1985-08-30

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