JPH0689973A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit having a protection circuit which can protect internal cells from static electricity in accordance with the areas of the cells and can cope with an overvoltage generated under complicated conditions, such as the ESD pulse, etc. CONSTITUTION:In this circuit having such a structure that a plurality of I/O cells 82 are electrically connected in parallel with one bonding pad 81, plural protection circuits 84 reducing overvoltages are arranged in parallel with each other between the one bonding pad 81 and the plural I/O cells 82 and, in addition, the wiring between the circuits 84 and cells 82 is short-circuited.

Description

Detailed Description of the Invention

[0001]

This invention relates to a gate array system,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit represented by a standard type custom LSI, and more particularly to a semiconductor integrated circuit having a protection circuit provided to prevent destruction or deterioration of a MOS structure due to a transient phenomenon of high voltage or high current due to electrostatic discharge. It is a thing.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit having a MOS structure, it has been general to provide a protection circuit to protect the built-in I / O cell from static electricity. Recent semiconductor integrated circuits, especially gate array type custom L
ASIC (Application Spacific Inte) represented by SI
grated circuit), for example, Japanese Patent Laid-Open No. 1-289138
As disclosed in Japanese Patent Publication No. JP-A-2003-242, by making the width of each I / O cell (I / O buffer) narrower, a plurality of I / O cells are connected to one bonding pad and output. A so-called slice type I / O cell, which earns a current, is being used.

On the other hand, as a conventional protection circuit for a semiconductor integrated circuit, conventionally, the following two types of structures have been selectively adopted.

(1) In the first structure, complementary protection circuits are arranged at the opposite pole positions with respect to the bonding pad. The complementary protection circuit referred to here is, for example, a combination of a protection circuit having a protection function against a positive polarity electrostatic pulse and a protection circuit having a protection function against a negative polarity electrostatic pulse. Say.

FIG. 11 (a) is a specific layout diagram of complementary protection circuits. A primary protection circuit 32a and a secondary protection circuit 33a are provided at opposite electrode positions of the bonding pad 31a, and the primary protection circuit 32a is further provided. V _CC power bus 3
4a and the secondary protection circuit 33a are electrically connected to the GND power supply bus (not shown) and the internal circuit, respectively. Further, FIG. 2B shows an equivalent circuit thereof, which is the primary protection circuit 32b.
Is a P ⁺ / N ^- diode, and the secondary protection circuit 33b is N ⁺ / N-
An example using a P ^- diode is shown.

In such a configuration, the primary protection circuit 32b operates in the forward direction when a positive voltage is applied to the bonding pad 3b.
It functions to lower the voltage of 1b, while the secondary protection circuit 33
b is biased in the forward direction when a negative voltage is applied, and serves to lower the voltage of the bonding pad 31b.

Specifically, as an example of a protection circuit based on the same idea, Robert J. Antionone (Electrical Ov
The protection circuit introduced in ertress Protection for Electronic Devices, pp. 19) is shown in Fig. 12. In this circuit, a guard ring is inserted around the bonding pad 41, and a protection circuit 43 is formed between the P ⁺ diode 42 formed on both surfaces of the bonding pad 41. The adjacent diode 44 is a diode formed by N ⁺ diffusion resistance.

(2) Unlike the above-described first structure, the second structure is not symmetrically arranged with respect to the bonding pad, but each protection circuit is configured in a complementary manner.

As an example of a specific protection circuit, Robert
J.Antionone (Electrical Overtress Protection for Ele
Figure 13 shows the protection circuit introduced in ctronic Devices, pp. 18).
Shown in. In particular, FIG. 7A is a front view of the protection circuits viewed from above, and FIG. 6B is a cross-sectional view of the protection circuits. As is clear from these drawings, two protection circuits are provided. Although 52 and 53 are not placed symmetrically with respect to the bonding pad 51, they perform complementary operations.

[0010]

At present, the MIL standard method or E standard is widely used as a standard for electrostatic breakdown withstanding test.
The IAJ method is used. However, since the ESD pulse used in these test methods has various rise times and pulse widths, it has been difficult to manufacture a semiconductor integrated circuit that can support any of these test methods. In addition, FIG.
An equivalent circuit of an apparatus for performing these electrostatic breakdown withstand tests is shown in (a), and measurement conditions of each test method are shown in (b).

Generally, in the case of the EIAJ method, the resistance R
A large current instantaneously flows as much as 1 is 0 ohm. Therefore, the breakdown occurs with a large current in a short time. On the other hand, in the MIL standard method, it is said that breakdown is likely to occur at a high voltage and a relatively wide pulse width.

As shown in FIG. 15A, a slice type semiconductor integrated circuit including a gate array has a plurality of (three in this figure) I / O cells 62 in order to increase the output current.
a to 62c are electrically connected to one bonding pad 61. When the ASIC having such a structure is protected from static electricity, one primary protection circuit 74 is arranged between the bonding pad 71 and the power supply bus 73 as shown in FIG. One secondary protection circuit 75 is arranged between the bonding pad 71 and the plurality of I / O cells 72a to 72c, and each protection circuit 7 is provided.
A configuration is conceivable in which the potential is reduced when an overvoltage is supplied to 4, 75.

In FIG. 15 (a), the power supply means for the protection circuit is not shown, but FIG. 15 (b) is used.
In one mode, the power supply bus 73 is connected to the primary protection circuit 7.
4 shows a configuration connected to No. 4.

In a semiconductor integrated circuit having such a protection circuit (comparative example for comparison with the present invention), the number of I / O cells (I / O buffer portion) 72a to 72c when the total area is large, sufficient protection cannot be expected, and
The protection circuits 74 of the combination shown in FIG.
When an electrostatic pulse or a large amount of energy that cannot be absorbed by the time constant of 75 is applied, the energy is not sufficiently reduced and the protection functions of these protection circuits 74 and 75 are not fully exerted.

The present invention has been made to solve the above problems and is intended for a semiconductor integrated circuit having a structure in which a plurality of I / O cells are electrically connected in parallel to one bonding pad. Provided is a semiconductor integrated circuit having a protection circuit capable of performing electrostatic protection according to the total area of the internal cells and capable of handling an overvoltage and a transient phenomenon of a large current generated under a complicated condition such as an ESD pulse. The purpose is to

[0016]

In the semiconductor integrated circuit according to the first aspect of the invention, the power supply means to the protection circuit is not particularly limited, but one bonding pad is electrically connected in parallel with a plurality of I / O cells. In the structure, one bonding pad and a plurality of I's connected to this bonding pad
It is characterized in that a plurality of protection circuits for reducing the overvoltage are arranged in parallel with the / O cell with respect to the bonding pad, and the wiring between these protection circuits and the I / O cell is short-circuited.

On the other hand, in the semiconductor integrated circuit according to the second invention, in a structure in which one bonding pad is electrically connected in parallel with a plurality of I / O cells, an overvoltage is generated between the power supply bus and one bonding pad. A plurality of primary protection circuits for reducing the over voltage are arranged in parallel with the bonding pad, and a plurality of secondary protection circuits for reducing the overvoltage are arranged in parallel with the bonding pad between the bonding pad and the I / O cell. I / O of these secondary protection circuits
The feature is that the wiring existing on the O cell side is short-circuited.

The bonding pads in the first and second inventions are characterized in that one common pad is formed by electrically connecting two or more bonding pads.

In particular, the plurality of protection circuits may be the same circuit or circuits having different protection functions. Desirably, the plurality of protection circuits are the same as the plurality of I / O cells. It is better to have a one-to-one correspondence. Further, these protection circuits, regardless of whether or not they have the same circuit configuration, are circuits that reduce the input positive overvoltage,
Alternatively, it is a circuit for reducing the input negative overvoltage, each of which is configured to include one or more switching elements having different operating conditions and elements and characteristics.

Furthermore, as a means for short-circuiting the I / O cell side of the plurality of protection circuits arranged in parallel (the power supply bus side of the primary protection circuit is also the target in the second invention), there are a plurality of protection circuits and a plurality of protection circuits. Each wiring pattern that electrically connects to the I / O cell is connected with a conductive metal, or the wiring pattern itself that connects each part is short-circuited, or each part is connected with a common wiring pattern. It is realized by doing.

In this specification, the protection circuit arranged between the power supply bus and the bonding pad is particularly called a primary protection circuit, and the protection circuit arranged between the bonding pad and the I / O cell is particularly called a secondary protection circuit. The next protection circuit. Further, in this specification, the power supply means includes a power supply bus, and the power supply bus includes a V _CC bus and a GND for supplying power.
It is a concept that includes a bus.

Further, as an application example of the second invention,
The structure may be such that only the I / O cells of the plurality of secondary protection circuits are short-circuited.

[0023]

In the semiconductor integrated circuit according to the first aspect of the invention, when an overvoltage is applied to one bonding pad from the outside, a plurality of I / O cells arranged in parallel are provided between the bonding pad and the plurality of I / O cells. By the secondary protection circuit of
Since the input voltage is reduced and the I / O cell side of each of these secondary protection circuits is short-circuited, the input potential of each I / O cell is kept the same (transiently the same potential). become).

On the other hand, in the semiconductor integrated circuit according to the second aspect of the invention, when an overvoltage is input to the bonding pad, the voltage value is reduced in the plurality of primary protection circuits. At this time, if the input voltage is sufficiently reduced, a plurality of I
/ O cell is supplied with voltage as it is, but when protection is insufficient, a plurality of secondary protection circuits arranged between the bonding pad and a plurality of I / O cells are activated to operate the secondary protection circuits. Since the I / O cell side of the protection circuit is short-circuited, the input potentials of all I / O cells are all kept the same (transiently the same potential).

Next, the plurality of primary protection circuits and secondary protection circuits according to the first and second inventions are arranged in parallel with respect to one bonding pad,
Further, it is characterized in that the wiring connecting each part is short-circuited.

As means for short-circuiting the wirings, the wirings are all connected by a common conductive metal, the wiring pattern is processed into a short-circuited shape, or each wiring is connected by a common wide wiring. According to these means, it is possible to reduce the resistance value of the short-circuited portion without increasing the wiring area. In particular, the means for connecting all the wirings with a common conductive metal is used when the pad pitch is 100 μm or less. It is valid.

As a method of arranging the plurality of protection circuits,
For example, when two types of secondary protection circuits (indicated by 74 and 75 in the figure) are formed between one bonding pad and a plurality of I / O cells as shown in FIG. )
When arranging each secondary protection circuit in series as shown in,
A configuration in which they are arranged in parallel as shown in FIG. It should be noted that FIGS. 1B and 1C show the configuration in the case of three I / O cells, and the power supply means to the secondary protection circuit is omitted in any of the drawings. In addition, the protection circuits shown in FIG.
4, 75, but the circuits may have different protection functions.

As shown in FIG. 1B, each secondary protection circuit 7
In the configuration in which 4, 75 are arranged in series, they are necessarily arranged linearly with respect to the signal flow. in this case,
There is a gap in the time that the ESD pulse is transmitted to each protection circuit,
Since the protection circuit that is transmitted later (the protection circuit at the subsequent stage) is first transmitted to the protection circuit at the previous stage without attenuating the kind of pulse having an effect, the protection circuit may be destroyed.

On the other hand, each secondary protection circuit 7 shown in FIG.
In the configuration in which 4 and 75 are arranged in parallel, the distances from one bonding pad to the respective secondary protection circuits 74 and 75 are substantially equal to each other, so that the time during which the ESD pulse propagates to each secondary protection circuit is substantially uniform. (Each secondary protection circuit operates substantially uniformly). Further, in the present invention, since each wiring is short-circuited by the conductive metal, the adverse effect due to the shift of the switching time of each secondary protection circuit is eliminated.

As the wiring applied in the present invention,
When the bonding pad 71 and the plurality of secondary protection circuits 74 and 75 are independently connected as shown in FIG. 1C, it is particularly effective when the pad pitch is 100 μm or less. The wiring pattern applied in 1. is not limited to this configuration.

That is, as shown in FIG. 2, the bonding pad 71 and each of the secondary protection circuits 74 to 76 may be connected by a common wiring pattern 77 having a large width.

According to this configuration, each secondary protection circuit 74-
Since the output of 76 is automatically short-circuited, it is not necessary to separately provide a conductive metal wiring for short-circuiting.

In practice, the bonding pad 7
1, each secondary protection circuit 74 to 76 and each I / O cell 72a
To 72c are connected to each other by a common wiring pattern (lower Al wiring layer), and power supply buses A and B (upper Al wiring layer, these power supply buses are V _CC or GND) so as to extend directly above these cells. ) Are formed and connected to the lower Al wiring layer at a required position to form a circuit.

In the first and second aspects of the invention, a plurality of protection circuits (both the primary protection circuit and the secondary protection circuit, or only the secondary protection circuit) arranged in parallel are respectively provided as a plurality of I / Os. One configuration is a configuration in which cells are arranged in a one-to-one correspondence.

FIG. 3 shows a comparative example of the present invention (in the figure, the means for supplying power to the secondary circuit is omitted), and one bonding pad 81 and one I / O cell 82 are provided. The configuration of a semiconductor integrated circuit in which only the secondary protection circuit 84 is arranged is shown. In particular, this ASIC is designed such that six I / O cells correspond to one bonding pad 81, and the allowable current of each I / O cell 32 is shown as 3 mA. At this time, each bonding pad 81 is supplied with the total allowable current of the I / O cells electrically connected in parallel. For example, three I / O cells 82
When electrically connected in parallel, the current of 9mA is 1
Will be applied to one bonding pad 81.

However, since the number of I / O cells 82 electrically connected in parallel with one bonding pad 81 varies depending on design specifications, a secondary protection circuit 84 arranged in advance is provided.
Must be formed so as to correspond to the maximum value (in this FIG. 3, all the secondary protection circuits 84 are formed so as to correspond to the current value of 27 mA).

In this case, the area efficiency is reduced and
If all the secondary protection circuits 84 are formed to have a small area in advance, the protection capability will be insufficient when the protection function is omitted or a maximum output current is given to a specific ESD pulse. .

On the other hand, as shown in FIG. 4 (the power supply means for the secondary protection circuit is omitted in the figure), one secondary protection circuit 84 for one I / O cell 82. With the configuration in which is arranged, the maximum area efficiency can be obtained. Further, if the number of I / O cells connected to one bonding pad is large, the distance between the bonding pad and each secondary protection circuit cannot be made substantially constant, but in such a case, As shown in the lower side of FIG. 4, by connecting a plurality of bonding pads 81 together with a common wiring pattern having a large width, the bonding pads 81 can be used as a common bonding pad and the distance (bonding pad Even in the worst case, it is possible to suppress the variation of each I / O cell) to the pad interval or less.

Further, by disposing a plurality of types of secondary protection circuits 84 in advance as shown in FIG. 4, it is possible to cope with all possible ESD pulses. The symbols A to L shown in the figure indicate the types of the secondary protection circuits 84, and it is not necessary that they are all different types of protection circuits (for example, three different types of protection circuits are arranged and protection circuits are provided). If the protection circuits A and D, G, and J, the protection circuits B and E, H, and K, and the protection circuits C and F, I, and L are protection circuits of the same type, The same number of three types of protection circuits are connected to each bonding pad to obtain the best protection performance against various ESD pulses.In this case, the bonding pad and three types of secondary circuits are also provided. By making the distances between the protection circuits approximately the same, it is possible to prevent the occurrence of adverse effects due to the deviation of the ESD pulse transmission time, which is effective when the number of I / O cells connected to one bonding pad is large.) .

It is also possible to combine a plurality of types of secondary protection circuits 84 with the required secondary protection circuits 84 according to user needs.

Further, FIGS. 3 and 4 explained above are the first
Although only the configuration of the invention of 1 is disclosed, the configuration of the second invention also has similar characteristics.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be explained. In the figure, the same parts are designated by the same reference numerals and the description thereof is omitted.

FIG. 5 is a diagram showing the structure of the main part of an embodiment of the semiconductor integrated circuit according to the first invention, in which the power supply means is omitted.

In the figure, between the bonding pad 11 and the three I / O cells 14a to 14c, the secondary protection circuits 15a to 15a are provided in parallel with the bonding pad 11 in parallel.
5c is arranged. In addition, the secondary protection circuits 15a-1
5c is a combination of circuits having different operating principles or the same circuit.

In FIG. 5, I / O cells 14a-1
Although the secondary protection circuits 15a to 15c are arranged in parallel by the number of 4c, it is not necessarily technically required that the I / O cells and the secondary protection circuits have a one-to-one correspondence. . In addition, each of the secondary protection circuits 15a to 15c is, for example, a circuit that reduces the voltage value when a positive overvoltage is input to its input side, or a voltage value that is reduced when a negative overvoltage is input. It is any one of the circuits to be operated, and is formed by arbitrarily combining a plurality of switching elements having different operating conditions and parameters such as a time constant and an ON resistance value.

Further, the wiring (for example, formed of the first Al layer) connecting each of the secondary protection circuits 15a to 15c and the I / O cell is made of a conductive metal (for example, the third Al layer).
It is short-circuited by the wiring 16 formed in. Therefore, when an overvoltage such as a surge voltage is applied from the bonding pad 11 side, these secondary protection circuits 15a to 15c operate to reduce the voltage of the bonding pad 11, but the I / O of these secondary protection circuits 15a to 15c is reduced. Since it is short-circuited by the metal wiring 16 provided on the cell side, I /
The input potentials to the O cells 14a to 14c are all the same (transiently the same potential). In addition, it is possible to avoid a situation where an excessive voltage is input only to a specific I / O cell to cause electrostatic breakdown.

In the first invention described above (FIG. 5), the secondary protection circuits 15a to 15c and the I / O cells 14a to 14c are formed by the wiring 16 formed of a conductive metal.
Although and are short-circuited, the structure for short-circuiting is not particularly limited to this configuration. That is, as shown in FIG. 6, the wiring patterns that electrically connect the respective secondary protection circuits 15a to 15c and the respective I / O cells 14a to 14c may be processed into a shape in which they are short-circuited. Further, as shown in FIG. 4 described above, one bonding pad and each secondary protection circuit may be connected by a common wiring pattern having a large width. The effects obtained by this configuration are as described above.

However, the pad pitch is, for example, 100 μm.
When reduced to the following, the secondary protection circuit and I
The wiring connecting to the / O cell becomes thin and the impedance becomes high. Therefore, when a short circuit occurs in the same wiring layer pattern, a situation occurs in which the input potentials of the I / O cells 14a to 14c are transiently different, and the I / O cells may not be sufficiently protected. obtain. When the bonding pad-secondary protection circuit-I / O cell is connected by a common thick wiring, such a problem is unlikely to occur. Further, as shown in FIG. 5, if a conductive metal for connection is short-circuited, the Al wiring of the third layer generally has a lower sheet resistance than the Al wiring of the first layer, and moreover, there is a margin in area. It is possible to form a short-circuiting wire having a large thickness and a low impedance, which is even more advantageous (in FIG. 5, the wire 16 in this portion is drawn thin for easy viewing). It is also effective to use some short-circuit means together.

Next, FIG. 7 shows the structure of the main part of an embodiment of the semiconductor integrated circuit according to the second invention.

In FIG. 7, between the bonding pad 11 and the power supply bus 12, three primary protection circuits 13a to 13c are arranged in parallel to the bonding pad 11, and the bonding pad 11 and three primary protection circuits 13a to 13c are arranged. I /
Three secondary protection circuits 15a to 15 are provided in parallel with the bonding pads 11 between the O cells 14a to 14c.
c is arranged. The primary protection circuits 13a to 13c and the secondary protection circuits 15a to 15c are circuits each having a different operation principle (or protection function), or a combination of the same circuits.

In FIG. 7, I / O cells 14a-1
The primary protection circuits 13a to 13c and the secondary protection circuits 15a to 15c are arranged in parallel by the number of 4c, but the technical relationship is that the I / O cells and the respective protection circuits have a one-to-one correspondence. It is not required. Here, each protection circuit is connected to V _CC side, GND according to each operation.
Side or both power supply buses. Further, in order to avoid complication in FIG. 7, only one of the power supply buses connected to the primary protection circuits 13a to 13c is disclosed, and the power supply connected to the secondary protection circuits 15a to 15c. Buses are not disclosed.

The primary protection circuits 13a to 13c and the secondary protection circuits 15a to 15c are, for example, circuits for reducing the voltage value when a positive overvoltage is input, and a circuit for reducing a negative overvoltage. It is one of the circuits for reducing the voltage value, and is formed by arbitrarily combining a plurality of switching elements having different operating conditions and parameters (element characteristics) such as a time constant and an ON resistance value.

Further, the secondary protection circuits 15a to 15c and I /
The wiring connecting the O cells 14a to 14c is short-circuited by the metal wiring 16 (pad pitch is 100 μm.
Especially effective in the following cases). When an overvoltage such as a surge voltage is input to the bonding pad 11, first, the primary protection circuits 13a to 13c are activated to form a low impedance path with the power supply bus 12. If this is still insufficient, the secondary protection circuits 15a to 15c operate to reduce the voltage of the bonding pad 11, but the secondary protection circuits 15a to 15c are connected to the I / O cells 14a to 14c. Since the wiring is short-circuited by the wiring 16 made of a conductive metal, the input potentials of the I / O cells 14a to 14c are all the same. Therefore, it is possible to avoid a situation where an excessive voltage is input only to a specific I / O cell to cause electrostatic breakdown.

Further, as an application example of the second invention (FIG. 7), for example, as shown in FIG. 8, a wiring 16 (denoted by 16a and 16b in the figure) formed of a conductive metal is used as a secondary The protection circuits 15a to 15c may be provided not only on the I / O cell side but also on the power supply bus side of the primary protection circuits 13a to 13c. Since the power supply bus 12 includes a power supply bus and a GND bus, each of the primary protection circuits 13a to 13a
Although it is effective to connect 3c to different buses, the structure for short-circuiting with the metal wiring 16b as shown in FIG. 8 is a particularly effective structure when each wiring width is 100 μm or less. is there. As the wiring pattern, as in the above-described first invention, as shown in FIG. 4, a wiring pattern having a large wiring width common to each protection circuit is used.
The wiring pattern may be processed into a short-circuited shape as shown in FIG.

In this application example, the pad pitch is 100 μm.
This is particularly effective when the wiring connecting the primary protection circuits and the power supply bus is thin and long due to the reduction in size or the influence of the structure of the primary protection circuit, and the impedance of that portion becomes high.

If only the secondary protection circuits 15a to 15c are sufficient, the primary protection circuits 13a to 13c can be omitted. Furthermore, as an application example shown in FIG. Pad 1 and 1
The same effect can be obtained by using only one primary protection circuit 13.

In the second aspect of the present invention, it is more effective if the primary protection circuit is composed of a thyristor or the like which has a slow operation speed but absorbs a large amount of energy, and the secondary protection circuit is composed of a diode or the like having a high operation speed. is there.

Next, a more specific configuration of the present invention will be described with reference to FIG. In addition, in FIG. 10, among the above-described configurations (FIGS. 5 to 9), in particular,
Although a configuration in which the configuration shown in FIG. 6 is embodied is shown, the operation principle is the same in other configurations. Further, in FIG. 10, the power supply means to the secondary protection circuit is omitted.

In FIG. 10, the first secondary protection circuit 22
a (indicated by secondary protection circuit A in the figure) is an N ⁺ / P ^- diode, and second secondary protection circuit 22b (indicated by secondary protection circuit B in the figure) is a P ⁺ / N ^- diode; The secondary protection circuit 22c of No. 3 (indicated by the secondary protection circuit B in the figure) is composed of a thyristor. The I / O cells 23a to 23c configured as output buffers are n-channel M, respectively.
It is composed of an OS-FET or a p-channel MOS-FET.

In this structure, when a negative electrostatic pulse is externally applied to the bonding pad 21, the first
When the secondary protection circuit 22a is turned on and a positive electrostatic pulse is applied, the second secondary protection circuit 22b is turned on. As a result, the input voltage of the bonding pad 21 is reduced, and the voltage supplied to each I / O cell 23a-23c approaches the normal level.

On the other hand, the first and second secondary protection circuits 22
The third secondary protection circuit 22c operates when a pulse is applied which cannot be dealt with by the protection capabilities of a and 22b. In this case, since the thyristor has a low on-resistance value, this energy is absorbed and the I / O cells 23a to 23c are absorbed.
The input voltage supplied to is sufficiently reduced. In the above-described embodiments (FIGS. 5 to 10), three primary protection circuits and three secondary protection circuits are provided for three I / O cells. And the number of secondary protection circuits may be greater than the number of I / O cells.

Further, according to the principle of the present invention, in addition to the two kinds of diodes and thyristors in the case of FIG. 10, it is possible to simultaneously arrange switching elements having various operating conditions and parameters. Therefore, the above-mentioned EI
A semiconductor integrated circuit compatible with both the AJ method and the MIL standard method can be constructed. in this case,
In consideration of the MIL standard method, a field type M that absorbs a waveform with a wide pulse width and a high voltage value
In consideration of the OS transistor and the EIAJ method, a thyristor or a diode is connected to the bonding pad for a narrow pulse width and a voltage value of several hundred volts.

The present invention is also characterized in that a plurality of types of circuits are arranged as protection circuits. It is possible to prepare a protection circuit that can cope with a special ESD pulse as a library, and select and customize the protection circuit according to the specifications required by the user.

[0064]

As described above, according to the present invention, I / O
When the number of cells and the area of the pattern increase, it is possible to arrange the protection circuit of the number corresponding to the range that the area permits, and in this case, the conventional problem that the electrostatic discharge protection becomes insufficient. This has the effect of eliminating points.

Specifically, each protection circuit is arranged in parallel to one bonding pad, and the I / O cell side (and power supply bus side) of each protection circuit is short-circuited. It is possible to make the distance from one bonding pad to each protection circuit substantially uniform, that is, to match the time until the ESD pulse propagates to each protection circuit. Therefore, all types of pulses can be attenuated at the same time, and the protection capability can be improved. Note that the current value supplied is one I / O
Even if the cell can handle it, multiple protection circuits
It is also possible to connect and bond to one bonding pad and the I / O cell respectively.

The present invention is also characterized in that a plurality of types of circuits are arranged as protection circuits. This has the effect that it is possible to prepare a protection circuit that can cope with a special ESD pulse as a library and select and customize these protection circuits according to the user's required specifications.

In addition, when the bonding pad interval is reduced, it is not necessary to redesign the interval (or width) of each protection circuit, and the wiring pattern can be changed without changing the protection circuit. Only by doing so, it is possible (Fig. 4).

Further, by arranging each protection circuit corresponding to each I / O cell, a plurality of I / O cells are connected in parallel to one bonding pad in order to increase the output current. However, each protection capability is also increased, and therefore no damage due to overvoltage is applied to each I / O cell. On the contrary, according to the present invention, it is not necessary to dispose a protection circuit having a large area so as to cope with a large output current, so that the area efficiency is much higher than in the conventional case.

Further, a plurality of circuits for performing complementary operations,
Since a plurality of switching elements having different operating conditions can be arranged at the same time as the input cell as a protection circuit, electrostatic pulses generated under complicated conditions can be effectively absorbed.
Therefore, it is possible to prevent circuit breakdown and deterioration due to high voltage or excessive reduction of large current due to discharge of static electricity.

In the present invention, the slice type I / O is used.
This is a particularly effective protection means in the case of a semiconductor integrated circuit having cells, but it is not limited to this and can be widely applied to general semiconductor integrated circuits.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an operation in the present invention of arranging a plurality of protection circuits in parallel with respect to one bonding pad.

FIG. 2 is a diagram for explaining a wiring structure of a plurality of protection circuits in the semiconductor integrated circuit according to the present invention.

FIG. 3 is a diagram showing a comparative example for explaining the operation of arranging a plurality of protection circuits corresponding to a plurality of I / O cells.

FIG. 4 is a diagram for explaining the operation in the present invention of arranging a plurality of protection circuits corresponding to a plurality of I / O cells respectively.

FIG. 5 is a diagram showing a main structure of a semiconductor integrated circuit according to a first embodiment of the first invention.

FIG. 6 is a diagram showing a main structure of a semiconductor integrated circuit according to a second embodiment of the first invention.

FIG. 7 is a diagram showing a main structure of a semiconductor integrated circuit according to a first embodiment of the second invention.

FIG. 8 is a diagram showing a main structure of a semiconductor integrated circuit according to a second embodiment of the second invention.

FIG. 9 is a diagram showing a main structure of a semiconductor integrated circuit according to a third embodiment of the second invention.

FIG. 10 is a diagram showing a main part structure of a semiconductor integrated circuit according to a first embodiment of the invention.

FIG. 11 is a diagram showing a main part configuration and an equivalent circuit including a plurality of protection circuits in a conventional semiconductor integrated circuit.

FIG. 12 is a diagram showing the structure of the main part of another conventional semiconductor integrated circuit including a plurality of protection circuits.

FIG. 13 is a diagram showing another conventional semiconductor integrated circuit, showing a main part structure and a cross-sectional structure including a plurality of protection circuits.

FIG. 14 is an equivalent circuit diagram of a device that performs a typical electrostatic breakdown withstanding test and a diagram showing measurement conditions when performing the electrostatic breakdown withstanding test.

FIG. 15 is a diagram showing a configuration of a main part of a master slice type semiconductor integrated circuit and a diagram showing a configuration of a main part when primary and secondary protection circuits are arranged in the semiconductor integrated circuit.

[Explanation of symbols]

11, 71, 81 ... Bonding pad, 13, 13a
~ 13c ... primary protection circuit, 74 ~ 76, 84, 15a ~
15c ... Secondary protection circuit, 14a-14c, 72a-72
c, 82 ... I / O cells, 16, 16a, 16b ... Metal wiring.

Claims (7)

[Claims] 1. A plurality of I / s on one bonding pad.
In a semiconductor integrated circuit having a structure in which O cells are electrically connected in parallel, a plurality of protection circuits for reducing overvoltage are provided between the one bonding pad and a plurality of I / O cells for the one bonding pad. And a plurality of protection circuits arranged in parallel and a plurality of I / O cells are short-circuited to each other. 2. A semiconductor integrated circuit having a structure in which a plurality of input / output cells are electrically connected in parallel to one bonding pad, wherein a plurality of ones for reducing an overvoltage are provided between the one bonding pad and a power supply bus. A secondary protection circuit is arranged in parallel with the one bonding pad, and a plurality of secondary protection circuits for reducing overvoltage are provided between the one bonding pad and the plurality of I / O cells. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is arranged in parallel with a pad, and wirings between the plurality of secondary protection circuits and a plurality of I / O cells are short-circuited. 3. The semiconductor according to claim 1, wherein the two or more bonding pads are electrically connected to each other to form one common pad with the plurality of connected bonding pads. Integrated circuit. 4. A plurality of protection circuits arranged in parallel to the bonding pad respectively include the I / Os.
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged in a one-to-one correspondence with cells. 5. The plurality of protection circuits arranged in parallel to the bonding pad is either a circuit for reducing a positive polarity overvoltage inputted to each of them or a circuit for reducing a negative polarity overvoltage. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a semiconductor integrated circuit. 6. The semiconductor integrated circuit according to claim 5, wherein the protection circuit includes one or more switching elements each having different operating conditions and element characteristics. 7. The means for short-circuiting the wiring includes connecting each of the connection wirings to a common conductive metal, processing the wiring pattern itself into a short-circuited shape, or connecting each portion with a common wiring. The connection is made according to claim 1.
5. The semiconductor integrated circuit according to claim 4.