JPH0687488B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0687488B2 JPH0687488B2 JP31202986A JP31202986A JPH0687488B2 JP H0687488 B2 JPH0687488 B2 JP H0687488B2 JP 31202986 A JP31202986 A JP 31202986A JP 31202986 A JP31202986 A JP 31202986A JP H0687488 B2 JPH0687488 B2 JP H0687488B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor
- semiconductor device
- convex portion
- piece
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、特に半導体小片の高密度実
装と放熱特性に優れた半導体装置の回路基板に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a circuit board of a semiconductor device which is excellent in high-density mounting of semiconductor chips and excellent in heat dissipation characteristics.
従来の技術 従来例を第４図を用いて説明する。従来の半導体装置の
半導体小片１は平面な形状を有した回路基板２に実装さ
れるものであって（第４図（Ａ））、半導体装置はこれ
らの回路基板２を複数の段を有する枠体７に複数枚積み
上げて構成し、電子機器３の大容量，多機能化を計るも
のであった（第４図（Ｂ））。一方、大電力，高速，高
集積な半導体小片１を回路基板２に多数実装した際、動
作時における半導体小片１の発熱が半導体装置の信頼性
上大きな問題となる。その放熱対策として、半導体小片
１を収納した収納容器３に熱伝導性にすぐれた材料から
成る放熱板４を搭置して放熱を行なう方法（第４図
（Ｃ））と送風機５を設置し、回路基板２に実装された
個々の収納容器３の放熱板４に風６を強制的に送り放熱
する方法（第４図（Ｄ））が主に用いられるものであっ
た。Conventional Technique A conventional example will be described with reference to FIG. A semiconductor piece 1 of a conventional semiconductor device is mounted on a circuit board 2 having a flat shape (FIG. 4 (A)), and the semiconductor device has a frame having a plurality of steps on the circuit board 2. It was constructed by stacking a plurality of sheets on the body 7 to increase the capacity and multifunction of the electronic device 3 (Fig. 4 (B)). On the other hand, when a large number of high-power, high-speed, highly-integrated semiconductor pieces 1 are mounted on the circuit board 2, heat generation of the semiconductor pieces 1 during operation poses a serious problem in reliability of the semiconductor device. As a heat dissipation measure, a method (FIG. 4 (C)) for placing a heat dissipation plate 4 made of a material having excellent thermal conductivity in the storage container 3 accommodating the semiconductor piece 1 to dissipate heat and a blower 5 are installed. The method (FIG. 4 (D)) forcibly sending the air 6 to the heat radiating plate 4 of each housing 3 mounted on the circuit board 2 to radiate heat has been mainly used.
発明が解決しようとする問題点 従来の半導体装置では下記の問題点を有するものであっ
た。Problems to be Solved by the Invention The conventional semiconductor device has the following problems.
１）半導体小片は平面な回路基板上に整列して実装され
るため、半導体小片の実装数が限られ、高密度実装がき
わめて困難となる。1) Since the semiconductor pieces are mounted in alignment on a flat circuit board, the number of semiconductor pieces mounted is limited, and high-density mounting becomes extremely difficult.
２）半導体小片から発生する熱を外部に放出するための
放熱板が必要となり、その結果、半導体装置が大型化す
る。2) A heat radiating plate for radiating heat generated from the semiconductor pieces to the outside is required, and as a result, the semiconductor device becomes large.
３）送風機の騒音，振動で周囲環境が阻害され、又、送
風機を用いることにより、半導体装置も大型化し、消費
電力や製造コストが著しく増大する。3) Noise and vibration of the blower hinder the surrounding environment, and the use of the blower also increases the size of the semiconductor device, resulting in a significant increase in power consumption and manufacturing cost.
等の問題点を有するもので、本発明は、半導体小片を回
路基板にきわめて高密度に実装し、又、放熱効果が高
く、小型，大容量，高機能な半導体装置を低コストで提
供することを目的とするものである。SUMMARY OF THE INVENTION The present invention has a problem that the semiconductor chips are mounted on a circuit board at an extremely high density, and a semiconductor device having a high heat dissipation effect, small size, large capacity, and high function is provided at low cost. The purpose is.
問題点を解決するための手段 本発明は以上の問題点を解決するために、回路基板の主
面に所定の深さ，幅，間隔で複数本の溝を形成し、凹部
の両側壁部，底面部及び凸部の上面部にそれぞれ半導体
小片を搭載することで高密度化を計り、さらに前記凸部
内部に空洞部を設けて冷媒を流入することで放熱効果を
高めるものである。Means for Solving the Problems In order to solve the above problems, the present invention forms a plurality of grooves with a predetermined depth, width, and interval on a main surface of a circuit board, The semiconductor pieces are mounted on the bottom surface and the top surface of the convex portion to increase the density, and a cavity is provided inside the convex portion to allow the refrigerant to flow therein, thereby enhancing the heat dissipation effect.
作用 回路基板の主面に設けられた回路基板の一部から成る凹
凸状段差の凹部の両側壁部，底面部及び凸部の上面部に
それぞれ半導体小片を実装することで実質的に凹部の両
側壁部と底面部が実装有効面積として得られ、半導体小
片の実装数が増大し、回路基板当りの実装密度を高める
ことが出来る。又、凸部の内部の空洞部に冷媒を流入す
ることによって半導体小片直下の回路基板の熱抵抗を小
さく出来、すぐれた放熱効果を得ることが可能となるも
のである。The semiconductor chip is mounted on both side walls, the bottom surface and the upper surface of the convex portion of the concave and convex steps formed by a part of the circuit board provided on the main surface of the circuit board, and substantially both sides of the concave portion are mounted. The wall portion and the bottom portion are obtained as the mounting effective area, the number of semiconductor small pieces mounted is increased, and the mounting density per circuit board can be increased. Further, by flowing the refrigerant into the hollow portion inside the convex portion, it is possible to reduce the thermal resistance of the circuit board immediately below the semiconductor small piece, and it is possible to obtain an excellent heat dissipation effect.
実施例 本発明の実施例を図面を用いて詳しく説明する。本発明
の一実施例における半導体装置の回路基板を第１図に示
す。11は回路基板、12は溝、13は電極・導体配線、14は
空洞部、15は半導体小片である。回路基板11の主面には
回路基板11の一部から成る所定の深さ，幅，間隔の溝を
形成し、凹凸の連続体を設け、凹部の両側壁部a,a′と
底面部ｂ及び、凸部の上面部ｃには実装する半導体小片
15の電極（図示せず）と相対した電極及び延在する導体
配線13が形成されている。又、回路基板11の凸部の内部
には空洞部14が設けられている。Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a circuit board of a semiconductor device according to an embodiment of the present invention. 11 is a circuit board, 12 is a groove, 13 is an electrode / conductor wiring, 14 is a cavity, and 15 is a semiconductor piece. The main surface of the circuit board 11 is formed with a groove having a predetermined depth, width, and interval, which is formed of a part of the circuit board 11, and is provided with a concavo-convex continuous body. And a semiconductor piece to be mounted on the upper surface c of the convex portion.
Electrodes facing 15 electrodes (not shown) and extending conductor wiring 13 are formed. In addition, a hollow portion 14 is provided inside the convex portion of the circuit board 11.
次にこの回路基板における半導体小片の実装構造を第２
図に説明する。半導体小片15は、回路基板11の凹部の両
側壁部a,a′と底面部ｂ及び凸部の上面部ｃにそれぞれ
所定の位置に実装され、半導体小片15の電極（図示せ
ず）と回路基板11の電極13とは互いに金属細線16で電気
的な接続が行なわれる。そして、回路基板11の凸部の空
洞部14には半導体小片15から発生する熱を放熱するため
の冷媒17が流入される。冷媒17は回路基板11の空洞部14
と接続された熱交換器（図示せず）によって熱交換が行
なわれ、再び回路基板11の空洞部14に循環，流入するも
のである。Next, the mounting structure of the semiconductor piece on this circuit board
This will be explained with reference to the figure. The semiconductor piece 15 is mounted at predetermined positions on both side walls a, a ′ of the recess of the circuit board 11, the bottom surface b and the upper surface c of the projection, respectively, and the electrodes (not shown) of the semiconductor piece 15 and the circuit are mounted. The electrodes 13 of the substrate 11 are electrically connected to each other by the thin metal wires 16. Then, the refrigerant 17 for radiating the heat generated from the semiconductor piece 15 flows into the cavity 14 of the convex portion of the circuit board 11. The refrigerant 17 is the cavity 14 of the circuit board 11.
The heat is exchanged by a heat exchanger (not shown) connected to and is circulated and flows into the cavity 14 of the circuit board 11 again.
以上のことから、回路基板11の凹部の両側面部a,a′と
底面部ｂ及び、凸部の上面部ｃにそれぞれ半導体小片15
を実装することにより、実質的に凹部の両側面部と底面
部が、実装有効面積として得られ、従来の平面な回路基
板と比較して、約２倍の高密度実装が可能となる。さら
に、凸部内の空洞部14に冷媒17を流入することで、実装
された半導体小片15直下の回路基板11の熱抵抗を低下さ
せることが出来、半導体小片15の発熱をきわめて効果的
に放散出来、半導体装置の信頼性を大幅に向上すること
が可能となる。又、本発明の第２の実施例として第３図
に示す通り、回路基板11の他面に放熱板18を設けること
で、さらに効果的な放熱を行なうことも可能である。From the above, the semiconductor piece 15 is formed on each of the side surface portions a, a'and the bottom surface portion b of the concave portion of the circuit board 11 and the upper surface portion c of the convex portion.
By mounting, the side surface portion and the bottom surface portion of the recess are substantially obtained as the mounting effective area, and it is possible to perform high-density mounting about twice as high as that of the conventional planar circuit board. Further, by flowing the refrigerant 17 into the cavity 14 in the convex portion, it is possible to reduce the thermal resistance of the circuit board 11 directly below the mounted semiconductor piece 15, and to dissipate the heat generated by the semiconductor piece 15 extremely effectively. Therefore, the reliability of the semiconductor device can be significantly improved. Further, as a second embodiment of the present invention, as shown in FIG. 3, by providing a heat dissipation plate 18 on the other surface of the circuit board 11, it is possible to perform more effective heat dissipation.
なお、本発明の実施例における半導体小片の実装は上記
に限るものではなく、たとえば、半導体小片を収納容器
に収納して回路基板に実装しても同様な効果が得られる
ものである。The mounting of the semiconductor piece in the embodiment of the present invention is not limited to the above. For example, the same effect can be obtained by mounting the semiconductor piece in a storage container and mounting it on a circuit board.
発明の効果 以上の説明で明らかな通り、本発明によれば、回路基板
の主面に溝を設け、凸部の内部に空洞部を設け、半導体
小片を凹部の両側壁部と底面部及び、凸部の上面部にそ
れぞれ実装することで、従来の平面な回路基板と比較
し、約２倍の高密度実装が可能となる。さらに、凸部の
内部の空洞部に冷媒を流入させることで回路基板の熱抵
抗を低下出来、半導体小片の放熱効果を高め、小型で高
信頼性な半導体装置を低コストで実現することが可能と
なるものである。EFFECTS OF THE INVENTION As is clear from the above description, according to the present invention, the main surface of the circuit board is provided with the groove, the cavity is provided inside the convex portion, and the semiconductor piece is provided with both side wall portions and the bottom surface portion of the concave portion, and By mounting each on the upper surface of the convex portion, it is possible to perform high-density mounting that is about twice as high as that of a conventional planar circuit board. Furthermore, the heat resistance of the circuit board can be reduced by injecting the coolant into the cavity inside the convex portion, the heat dissipation effect of the semiconductor chip can be improved, and a compact and highly reliable semiconductor device can be realized at low cost. It will be.
第１図の本発明の一実施例における半導体装置の斜視
図、第２図は本実施例における半導体装置の断面図、第
３図は本発明の他の実施例における半導体装置の断面
図、第４図（Ａ）は従来における半導体装置の斜視図、
第４図（Ｂ）は同装置の断面図、第４図（Ｃ）は同装置
の他の例を示す断面図、第４図（Ｄ）は第４図（Ｃ）の
装置の製造方法を示す構成図である。 11……回路基板、13……電極・導体配線、14……空洞
部、15……半導体小片、16……金属細線、17……冷媒、
18……放熱板。1 is a perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of the semiconductor device according to the present embodiment, and FIG. 3 is a sectional view of a semiconductor device according to another embodiment of the present invention. FIG. 4A is a perspective view of a conventional semiconductor device,
FIG. 4 (B) is a sectional view of the same device, FIG. 4 (C) is a sectional view showing another example of the same device, and FIG. 4 (D) is a method for manufacturing the device of FIG. 4 (C). It is a block diagram shown. 11 …… Circuit board, 13 …… Electrode / conductor wiring, 14 …… Cavity, 15 …… Semiconductor piece, 16 …… Metal wire, 17 …… Refrigerant,
18 ... Heat sink.
Claims (3)
幅，間隔で複数本の溝を形成し凸部の内部が空洞で前記
凸部の上面部と凹部の側壁部及び底面部に半導体小片を
設置し、前記凸部の内部の空洞内へ冷媒を流入するよう
にしてなる半導体装置。1. A flat circuit board having a predetermined depth on a main surface thereof,
A plurality of grooves are formed at widths and intervals, the inside of the convex portion is hollow, and semiconductor pieces are installed on the upper surface portion of the convex portion, the side wall portion and the bottom surface portion of the concave portion, and the refrigerant is introduced into the cavity inside the convex portion. A semiconductor device that is designed to flow in.
の範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, further comprising a heat radiator provided on the other surface of the circuit board.
設けられた電極に半導体小片の電極が接合されている特
許請求の範囲第１項記載の半導体装置。3. The semiconductor device according to claim 1, wherein the electrode of the semiconductor piece is joined to the electrodes provided on the upper surface of the convex portion, the side wall portion and the bottom portion of the concave portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31202986A JPH0687488B2 (en) | 1986-12-26 | 1986-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31202986A JPH0687488B2 (en) | 1986-12-26 | 1986-12-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63164348A JPS63164348A (en) | 1988-07-07 |
| JPH0687488B2 true JPH0687488B2 (en) | 1994-11-02 |
Family
ID=18024363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31202986A Expired - Fee Related JPH0687488B2 (en) | 1986-12-26 | 1986-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0687488B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8091614B2 (en) * | 2006-11-10 | 2012-01-10 | International Business Machines Corporation | Air/fluid cooling system |
-
1986
- 1986-12-26 JP JP31202986A patent/JPH0687488B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63164348A (en) | 1988-07-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |