JPH0669504A - Structure and manufacture of high-mobility thin film @(3754/24)tft) - Google Patents
Structure and manufacture of high-mobility thin film @(3754/24)tft)Info
- Publication number
- JPH0669504A JPH0669504A JP24592792A JP24592792A JPH0669504A JP H0669504 A JPH0669504 A JP H0669504A JP 24592792 A JP24592792 A JP 24592792A JP 24592792 A JP24592792 A JP 24592792A JP H0669504 A JPH0669504 A JP H0669504A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- gate electrode
- insulating film
- tft
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は,高電界効果移動度を実
現するTFTに関するものである.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TFT which realizes high field effect mobility.
【0002】[0002]
【従来の技術】TFTはアクティブマトリックス方式の
液晶ディスプレイの駆動用スイッチング素子として用い
られており,通常はガラス基板上に形成されている.そ
のためシリコン基板を用いたプロセスのような300度
を越える処理ができない.シリコン薄膜の堆積について
は単結晶シリコンや多結晶シリコンよりも堆積温度が低
いアモルファスシリコンが用いられている.しかしアモ
ルファスシリコンは単結晶シリコンと比較して電界効果
移動度が低く,スイッチング速度が遅くなるという欠点
があった.2. Description of the Related Art A TFT is used as a switching element for driving an active matrix type liquid crystal display, and is usually formed on a glass substrate. Therefore, it is not possible to perform treatments exceeding 300 ° C, such as the process using a silicon substrate. Amorphous silicon, which has a lower deposition temperature than single-crystal silicon or polycrystalline silicon, is used for the deposition of silicon thin films. However, amorphous silicon has lower field effect mobility and slower switching speed than single crystal silicon.
【0003】プロセスが低温化できないことにより,イ
オン打ち込み後のアニールができない.従ってソース及
びドレイン領域にLSIで用いられているような拡散層
を作り込むことが不可能であり,このことがソース及び
ドレイン電極とシリコンのコンタクト抵抗を増加させて
おり,この事も素子の電界効果移動度を悪化させるとい
う問題があった.Since the process cannot be performed at a low temperature, annealing after ion implantation cannot be performed. Therefore, it is impossible to form a diffusion layer as used in LSI in the source and drain regions, which increases the contact resistance between the source and drain electrodes and silicon, which is also the electric field of the device. There was a problem that the effective mobility deteriorated.
【0004】半導体膜及び絶縁膜をCVDにより堆積す
る際,プラズマによる高エネルギー粒子により下地の膜
にダメージがはいり,このことが原因となり電界効果移
動度が低下するという問題があった.When depositing a semiconductor film and an insulating film by CVD, there is a problem in that high-energy particles caused by plasma damage the underlying film, which causes a reduction in field-effect mobility.
【0005】[0005]
【発明が解決しようとする課題】解決しようとする問題
点は,コンタクト抵抗の上昇,製膜時に下地に加えられ
るダメージ,良好な界面を得るための半導体の表面処
理,従来のプロセス条件により制約を受けていたデバイ
ス構造,以上の原因により引き起こされていた電界効果
移動度の低下である.The problems to be solved are: increase in contact resistance, damage to the underlying layer during film formation, surface treatment of the semiconductor for obtaining a good interface, and restrictions due to conventional process conditions. It is the decrease in field effect mobility that was caused by the device structure that had been received and the above causes.
【0006】[0006]
【課題を解決するための手段】本発明は製膜時に基板に
加えられるダメージを,プラズマと光のエネルギーを併
用したCVDにより低減した.また,アンモニアプラズ
マ処理による主体半導体表面の窒化により表面劣化部を
実質的に除去した.さらに,ゲート電極形成後に半導体
の低比抵抗層を堆積により作製することにより自己整合
的にソース及びドレイン領域の形成を可能とし,高温処
理を行わずコンタクト抵抗の低下を実現した.その上ソ
ース及びドレイン領域とゲート領域の重なり部分をセル
フアラインにより設けることにより,ゲートによって形
成されるチャネルとソース及びドレイン領域が確実に接
続するようにし,一連のシリーズ抵抗を低減することに
より高電界効果移動度を実現した.According to the present invention, damage to a substrate during film formation is reduced by CVD using both plasma and light energy. Also, the surface-deteriorated part was substantially removed by nitriding the main semiconductor surface by the ammonia plasma treatment. Furthermore, by forming a low resistivity layer of semiconductor after deposition of the gate electrode, it became possible to form the source and drain regions in a self-aligned manner, and the contact resistance was reduced without high temperature treatment. In addition, the overlap of the source / drain region and the gate region is provided by self-alignment so that the channel formed by the gate and the source / drain region are surely connected to each other, and a series series resistance is reduced to increase the high electric field. Realized effective mobility.
【0007】[0007]
【実施例】図1は,本発明のTFTの断面図である.EXAMPLE FIG. 1 is a sectional view of a TFT of the present invention.
【図1】[Figure 1]
【0008】図2はその製法を示したものである.絶縁
基板201上に,半導体薄膜202を堆積した.次にこ
の半導体表面をアンモニアプラズマで処理し,表面を窒
化し半導体と絶縁膜との良好な界面を形成した.この後
にプラズマと光のエネルギーを併用したCVDで絶縁膜
203を堆積した.アルミニウムからなるゲート電極2
04を堆積し,フォトリソグラフィーのプロセスを用い
て,パターンを形成しエッチングによりゲート電極を形
成した.次に,ゲート電極部以外の部分の絶縁膜を除去
し,半導体表面を露出させておいた.この表面を酸化
し,ゲート電極のアルミニウムの酸化膜205及び半導
体の酸化膜206を形成した.この後半導体の酸化膜を
除去し,ゲート電極両端部の真下にノッチを形成した.
この後,低抵抗の半導体膜207を光CVDにより堆積
し,フォトリソグラフィーのプロセスを用いて,ソース
及びドレイン低抵抗領域を形成した.この上に層間絶縁
膜208を堆積し,フォトリソグラフィーのプロセスを
用いて,コンタクトホールを形成した.この上よりアル
ミニウム膜を堆積し,フォトリソグラフィーのプロセス
によりソース及びドレイン電極を形成し,図1に示した
TFTを作製した.FIG. 2 shows the manufacturing method. A semiconductor thin film 202 was deposited on the insulating substrate 201. Next, the surface of this semiconductor was treated with ammonia plasma, and the surface was nitrided to form a good interface between the semiconductor and the insulating film. After that, the insulating film 203 was deposited by CVD using both plasma and light energy. Gate electrode 2 made of aluminum
04 was deposited, a pattern was formed using a photolithography process, and a gate electrode was formed by etching. Next, the insulating film except for the gate electrode part was removed to expose the semiconductor surface. This surface was oxidized to form an aluminum oxide film 205 for the gate electrode and a semiconductor oxide film 206. After that, the oxide film of the semiconductor was removed, and notches were formed just under both ends of the gate electrode.
After that, a low-resistance semiconductor film 207 was deposited by photo-CVD, and the source and drain low-resistance regions were formed by using a photolithography process. An interlayer insulating film 208 was deposited on this, and a contact hole was formed by using a photolithography process. An aluminum film was deposited on top of this, and the source and drain electrodes were formed by a photolithography process to fabricate the TFT shown in FIG.
【0009】図2は本発明のTFTの製造方法である.FIG. 2 shows a method of manufacturing the TFT of the present invention.
【図2】[Fig. 2]
【0010】半導体を堆積した後に,アンモニアのプラ
ズマで半導体表面を処理することにより半導体の表面が
窒化され,実質的な半導体と絶縁膜の界面が半導体バル
ク中に形成されることになる.これにより半導体上に絶
縁膜を単純に堆積してできた界面より,汚染やダメージ
が少ない良好な界面を形成することができた.After the semiconductor is deposited, the surface of the semiconductor is nitrided by treating the surface of the semiconductor with ammonia plasma, and a substantial interface between the semiconductor and the insulating film is formed in the semiconductor bulk. As a result, it was possible to form a good interface with less contamination and damage than the interface formed by simply depositing an insulating film on the semiconductor.
【0011】絶縁膜の堆積時に,プラズマと光のエネル
ギーを併用したCVDを用いる事により,下地の半導体
層に入るダメージを低減することができた.ダメージを
減らすことにより,電界効果移動度を向上させることが
できた.When depositing the insulating film, it was possible to reduce damage to the underlying semiconductor layer by using the CVD that uses plasma and light energy in combination. By reducing the damage, the field effect mobility could be improved.
【0012】ソース及び,ドレイン電極と半導体層との
コンタクト抵抗を低減させるには,不純物濃度が高い,
即ち抵抗値が低い半導体層をアルミニウム配線と,半導
体層の間に設けることにより可能である.しかし不純物
濃度が高い拡散層は,通常イオン打ち込みと,その後の
処理により形成される.しかしガラス基板を用いた時の
ように,熱処理ができない時は,堆積による低抵抗半導
体層の形成が適している.In order to reduce the contact resistance between the source and drain electrodes and the semiconductor layer, the impurity concentration is high,
That is, it is possible to provide a semiconductor layer having a low resistance value between the aluminum wiring and the semiconductor layer. However, a diffusion layer with a high impurity concentration is usually formed by ion implantation and subsequent processing. However, when heat treatment is not possible, such as when using a glass substrate, the formation of a low-resistance semiconductor layer by deposition is suitable.
【0013】予め形成したゲート電極をマスクとして,
ソース及びドレイン領域を形成することにより,マスク
枚数を減らすことができる上に,加工精度を向上させる
ことができる.加えてソース及びドレイン領域とゲート
電極により形成されるチャネルが確実に接触するため,
シリーズ抵抗が低減される効果がある.Using the gate electrode formed in advance as a mask,
By forming the source and drain regions, the number of masks can be reduced and the processing accuracy can be improved. In addition, the source and drain regions and the channel formed by the gate electrode are surely in contact with each other,
It has the effect of reducing series resistance.
【0014】[0014]
【発明の効果】以上説明したように本発明の高移動度T
FTは,高温処理ができない条件で高い電界効果移動度
を持つTFTを実現するために,その製造方法及び構造
に改良を加えたものである.そのためガラスの様な高温
に弱い基板の上に,高移動度のTFTを作り込むことが
できるようになった.As described above, the high mobility T of the present invention is obtained.
FT is an improvement of the manufacturing method and structure of the FT in order to realize a TFT having a high field effect mobility under conditions where high temperature processing cannot be performed. As a result, it has become possible to fabricate TFTs with high mobility on substrates such as glass that are susceptible to high temperatures.
【図1】本発明のTFTの断面図である.FIG. 1 is a cross-sectional view of a TFT of the present invention.
【図2】TFTの製造方法の説明図である.FIG. 2 is an explanatory diagram of a method of manufacturing a TFT.
101 絶縁基板 102 半導体薄膜 103 絶縁膜 104 ゲート電極 105 酸化絶縁膜 106 低抵抗半導体層 107 層間絶縁膜 108 ソース電極 109 ドレイン電極 201 絶縁基板 202 半導体薄膜 203 絶縁膜 204 ゲート電極 205 アルミニウム酸化膜 206 半導体酸化膜 207 低抵抗半導体層 208 層間絶縁膜 Reference Signs List 101 insulating substrate 102 semiconductor thin film 103 insulating film 104 gate electrode 105 oxide insulating film 106 low resistance semiconductor layer 107 interlayer insulating film 108 source electrode 109 drain electrode 201 insulating substrate 202 semiconductor thin film 203 insulating film 204 gate electrode 205 aluminum oxide film 206 semiconductor oxide Film 207 Low resistance semiconductor layer 208 Interlayer insulating film
フロントページの続き (72)発明者 中村 潤二 名古屋市緑区相川2丁目43番地ベラビスタ 相川203号Front page continued (72) Inventor Junji Nakamura 2-43 Aikawa, Midori-ku, Nagoya Bella Vista No. 203 Aikawa
Claims (4)
るゲート電極部を持つ電界効果トランジスタにおいて,
ゲート電極表面の少なくとも一部に絶縁膜を形成して,
ゲート電極の必要とする絶縁を行いつつ,その膜上の一
部または側面に低比抵抗の導体層または半導体層を形成
して,ソース及びドレイン領域の一部とした薄膜トラン
ジスタ(以下TFTと記す)の構造.1. A field effect transistor having a gate electrode portion made of a metal or a semiconductor on a main semiconductor,
An insulating film is formed on at least a part of the gate electrode surface,
A thin film transistor (hereinafter referred to as a TFT) formed as a part of a source and drain region by forming a low resistivity conductor layer or a semiconductor layer on a part or side surface of the film while performing necessary insulation of the gate electrode. The structure of.
形成したゲート電極上の絶縁膜を酸化物により作ると同
時に,主体半導体の表面を酸化する.ゲート電極及びゲ
ート絶縁膜の端部直下の主体半導体部分にアンダーカッ
トを形成し,アンダーカット部も含む主体半導体の表面
の一部に低比抵抗層を形成することにより,ゲート電極
端部近傍のゲート部直下に低比抵抗層を持つことを特徴
とするTFTの構造.2. The TFT structure according to claim 1, wherein the insulating film on the gate electrode made of metal is made of oxide, and at the same time, the surface of the main semiconductor is oxidized. By forming an undercut in the main semiconductor portion immediately below the edges of the gate electrode and the gate insulating film, and forming a low resistivity layer on a part of the surface of the main semiconductor that also includes the undercut portion, the vicinity of the edge of the gate electrode is formed. TFT structure characterized by having a low resistivity layer directly under the gate.
少なくともゲート電極と主体半導体との間の絶縁膜を,
プラズマのエネルギーと光エネルギーにて励起された原
料ガスを用いたCVDによって製膜することを特徴とす
るTFTの製造方法.3. In manufacturing the TFT according to claim 1,
At least the insulating film between the gate electrode and the main semiconductor,
A method for manufacturing a TFT, which comprises forming a film by CVD using a source gas excited by plasma energy and light energy.
たプラズマによって主体半導体が,少なくとも製膜時ま
たは製膜後に処理されることを含むことを特徴とする製
造方法.4. The manufacturing method according to claim 3, wherein the main semiconductor is treated at least during or after film formation by the plasma using ammonia gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24592792A JPH0669504A (en) | 1992-08-21 | 1992-08-21 | Structure and manufacture of high-mobility thin film @(3754/24)tft) |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24592792A JPH0669504A (en) | 1992-08-21 | 1992-08-21 | Structure and manufacture of high-mobility thin film @(3754/24)tft) |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0669504A true JPH0669504A (en) | 1994-03-11 |
Family
ID=17140924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24592792A Pending JPH0669504A (en) | 1992-08-21 | 1992-08-21 | Structure and manufacture of high-mobility thin film @(3754/24)tft) |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0669504A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0766294A2 (en) * | 1995-09-29 | 1997-04-02 | Canon Kabushiki Kaisha | Thin film semiconducteur devices and methods of manufacturing the same |
JP2009267425A (en) * | 2009-06-08 | 2009-11-12 | Lg Display Co Ltd | Method of manufacturing semiconductor device |
-
1992
- 1992-08-21 JP JP24592792A patent/JPH0669504A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0766294A2 (en) * | 1995-09-29 | 1997-04-02 | Canon Kabushiki Kaisha | Thin film semiconducteur devices and methods of manufacturing the same |
EP0766294A3 (en) * | 1995-09-29 | 1998-03-04 | Canon Kabushiki Kaisha | Thin film semiconducteur devices and methods of manufacturing the same |
US6214684B1 (en) | 1995-09-29 | 2001-04-10 | Canon Kabushiki Kaisha | Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator |
JP2009267425A (en) * | 2009-06-08 | 2009-11-12 | Lg Display Co Ltd | Method of manufacturing semiconductor device |
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