JPH0665731A - Apparatus for production of semiconductor - Google Patents

Apparatus for production of semiconductor

Info

Publication number
JPH0665731A
JPH0665731A JP22408192A JP22408192A JPH0665731A JP H0665731 A JPH0665731 A JP H0665731A JP 22408192 A JP22408192 A JP 22408192A JP 22408192 A JP22408192 A JP 22408192A JP H0665731 A JPH0665731 A JP H0665731A
Authority
JP
Japan
Prior art keywords
collimator
metal
wafer
target
sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22408192A
Other languages
Japanese (ja)
Inventor
Yasuhito Momotake
康仁 百武
Tomoo Takayama
智生 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22408192A priority Critical patent/JPH0665731A/en
Publication of JPH0665731A publication Critical patent/JPH0665731A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the peeling of the deposits from a collimator and to improve the reliability of a wafer at the time of sticking the metal to be deposited onto the wafer by collimation sputtering. CONSTITUTION:A negative bias is impressed to a target 1, by which sputtering is started. The metal 8 which is to be deposited and is injected from the target 1 jumps out in random directions. This metal 8 to be deposited is controlled in the directions by the collimator 7 en route. The metal partly adheres to the collimator 7 and partly passes the collimator and sticks onto the wafer 2. The surface of the collimator 7a in this collimation sputtering is coated 7b with the same material as the metal 8 to the deposited. The metal 8 to be deposited, therefore, sticks well and the particles spraying to the wafer 2 by peeling decrease. The high-reliability semiconductor is thus obtd.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体製造装置の特
にコリメーションスパッタに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus, and more particularly to collimation sputtering.

【0002】[0002]

【従来の技術】近年の半導体装置の高集積化及び微細化
に伴って、素子間を電気的に相互に接続するためのコン
タクトホール及びスルーホールは、非常に小さく且つ高
アスペクト(コンタクト径とコンタクト深さの比)化し
てきている。通常素子間を結ぶ金属配線はスパッタ法に
より形成されるが、高アスペクトのコンタクトに対して
段差被覆性いわゆるステップカバレッジの悪さが大きな
問題となってきた。
2. Description of the Related Art With the recent high integration and miniaturization of semiconductor devices, contact holes and through holes for electrically connecting elements are very small and have a high aspect ratio (contact diameter and contact diameter). Depth ratio). Usually, the metal wiring connecting the elements is formed by the sputtering method, but the step coverage, so-called step coverage, has become a serious problem for high aspect contacts.

【0003】そこでこのスパッタによるステップカバレ
ッジの悪さを改善するために用いられている技術がコリ
メーションスパッタである。図3はコリメーションスパ
ッタを行う場合のスパッタチャンバーの模式構成を示す
断面図である。図において、1は被付着金属のチタン例
えば(Ti)よりなるターゲット、2はウエハ、3はタ
ーゲット1とウエハ2間に設けられたコリメータ、4は
排気孔4aを有し全体を収納する真空容器のチャンバ、
5はチャンバ4の内面に沿って設けられたシールド、6
はターゲット1とコリメータ3間に配置されたシャッタ
である。なお、図4はコリメーションスパッタの模式図
をAに示し、コリメータのハニカム状のメッシュ拡大図
をBで示している。
Therefore, a technique used to improve the poor step coverage due to this sputtering is collimation sputtering. FIG. 3 is a cross-sectional view showing a schematic configuration of a sputtering chamber when performing collimation sputtering. In the drawing, 1 is a target made of titanium (Ti), which is a metal to be adhered, 2 is a wafer, 3 is a collimator provided between the target 1 and the wafer 2, 4 is a vacuum container having an exhaust hole 4a and accommodating the whole. Chamber of the
5 is a shield provided along the inner surface of the chamber 4, 6
Is a shutter arranged between the target 1 and the collimator 3. Note that FIG. 4 shows a schematic diagram of the collimation sputtering in A, and an enlarged view of the honeycomb-shaped mesh of the collimator in B.

【0004】次に動作について説明する。窒化チタン
(TiN)を成膜する場合、チャンバ4内に窒素ガス
(N2ガス)及びアルゴンガス(Arガス)が所望の比
率(ArN2=0〜50/100〜50)及び所望の圧
力(通常数mTorr)まで導入される。この常態でタ
ーゲット1に負バイアス(通常−500U程度)が印加
されるとスパッタが開始される。シャッタ6によりプロ
セス時間がコントロールされターゲット1から射出され
たTi原子はN2と反応してTiNとしてウエハ2に向
かう。TiN分子は途中コリメータ3により方向を制御
されウエハには垂直方向成分の分子のみ入射し付着す
る。当然多くのTiN分子がコリメータ3に付着しコリ
メータ3上で膜を形成する。この付着状態は位置的に表
面部3a、中間部3b、背面部3cでサンプリングした
観察結果(図示なし)では特に背面部3cに数多く付着
しその付着力は弱く剥離が生じやすくなっている。これ
はコリメータ3を通過する際TiN分子はターゲット1
側の表面部3aではエネルギーの高いTiNが付着する
のに対しウエハ2側の背面部3cではコリメータ3内部
で何回か散乱を受けエネルギーの低い状態で付着するた
めである。
Next, the operation will be described. When depositing titanium nitride (TiN), a desired ratio of nitrogen gas (N 2 gas) and argon gas (Ar gas) (ArN 2 = 0 to 50/100 to 50) and desired pressure ( Usually up to a few mTorr). When a negative bias (usually about -500 U) is applied to the target 1 in this normal state, sputtering is started. The process time is controlled by the shutter 6, and the Ti atoms emitted from the target 1 react with N 2 and travel toward the wafer 2 as TiN. The direction of the TiN molecules is controlled by the collimator 3 on the way, and only the molecules of the vertical component are incident and attached to the wafer. Naturally, many TiN molecules adhere to the collimator 3 and form a film on the collimator 3. According to the observation result (not shown) sampled in the surface portion 3a, the intermediate portion 3b, and the back surface portion 3c, the adhesion state is particularly large on the back surface portion 3c, and the adhesion force is weak and peeling easily occurs. This is because the TiN molecule is the target 1 when passing through the collimator 3.
This is because TiN having high energy adheres to the surface portion 3a on the side thereof, whereas TiN having high energy adheres to the rear surface portion 3c on the side of the wafer 2 in a state of low energy due to scattering several times inside the collimator 3.

【0005】図5は従来のコリメーションスパッタによ
りTiN膜を成膜した場合のウエハ2上のパーティクル
発塵の個数を表したグラフであり、横軸が処理ウエハ枚
数、縦軸がパーティクル数を示している。処理枚数が増
加するに従いウエハ2上のパーティクル数が急激に増大
していることがわかる。
FIG. 5 is a graph showing the number of particle dust particles on the wafer 2 when a TiN film is formed by conventional collimation sputtering. The horizontal axis shows the number of processed wafers and the vertical axis shows the number of particles. There is. It can be seen that the number of particles on the wafer 2 rapidly increases as the number of processed wafers increases.

【0006】[0006]

【発明が解決しようとする課題】従来の半導体製造装置
でのコリメーションスパッタは以上のようになされるの
で特にコリメータ背面部からのパーティクルが多くなり
ウエハ上でのメタル配線にパターン欠陥(断線ショー
ト)が生じるばかりでなく、配線、しいては半導体装置
そのものの信頼性が低下するという問題点があった。
Since the collimation sputtering in the conventional semiconductor manufacturing apparatus is performed as described above, the number of particles from the back surface of the collimator increases, and pattern defects (disconnection short circuit) occur on the metal wiring on the wafer. Not only does this occur, but the reliability of the wiring, and thus of the semiconductor device itself, deteriorates.

【0007】この発明は上記のような問題点を解消する
ためになされたもので、コリメーションスパッタでパー
ティクル発生が少なく高信頼度の半導体製造装置を得る
ことを目的とする。
The present invention has been made to solve the above problems, and an object thereof is to obtain a highly reliable semiconductor manufacturing apparatus in which particles are less likely to be generated by collimation sputtering.

【0008】[0008]

【課題を解決するための手段】この発明に係る半導体製
造装置は、ウエハに付着する被付着金属に方向性を付け
るコリメータは少なくとも被付着金属と接する表面を被
付着金属と同一材料で構成したものである。
In a semiconductor manufacturing apparatus according to the present invention, a collimator for directing an adhered metal adhered to a wafer has at least a surface in contact with the adhered metal made of the same material as the adhered metal. Is.

【0009】[0009]

【作用】この発明における半導体製造装置は、コリメー
タの表面を構成する被付着金属と同一材料が被付着金属
と密着性を良くし剥離して飛散するパーティクルを減少
する。
In the semiconductor manufacturing apparatus according to the present invention, the same material as the adhered metal forming the surface of the collimator improves the adhesion to the adhered metal and reduces particles that are separated and scattered.

【0010】[0010]

【実施例】【Example】

実施例1.以下、この発明の実施例1を図に基づいて説
明する。図1はこの発明の実施例1における半導体製造
装置の模式構成を示す断面図で、Aにスパッタチャンバ
の全体をBにコリメータの部分拡大を示している。図に
おいて、1、2、4〜6は従来と同様でありその説明は
省略する。7は例えばステンレス鋼(SUS)でなるコ
リメータ本体7aとこのコリメータ本体の表面を被覆す
るターゲット1の材料即ち被付着金属と同一材料の被覆
材ここではTiのコーティング7bで形成されたコリメ
ータである。8は被付着金属の金属粒子ここではTiN
分子でその軌跡を9で示している。
Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a cross-sectional view showing a schematic configuration of a semiconductor manufacturing apparatus according to Embodiment 1 of the present invention, in which A shows the entire sputtering chamber and B shows a partially enlarged collimator. In the figure, reference numerals 1, 2, 4 to 6 are the same as the conventional ones, and the description thereof is omitted. Reference numeral 7 denotes a collimator body 7a made of, for example, stainless steel (SUS), and a coating material made of the same material as the material of the target 1 that covers the surface of the collimator body, that is, the metal to be adhered, here, a Ti coating 7b. 8 is metal particles of the adhered metal, here TiN
The locus is indicated by 9 in the molecule.

【0011】次に動作について説明する。通常スパッタ
法はターゲット1に負バイアスを印加し、ウエハ2との
間にプラズマを立てて行う。ウエハ2、シールド5、シ
ャッター6はグランドのため、プラズマ中のアルゴンイ
オン、窒素イオンはすべてターゲット1に向かう。アル
ゴンイオンがターゲット1に衝突すると、ターゲット1
を構成する原子がランダムな方向をもって飛び出してく
る。実施例1では、アルゴンガスに窒素ガスをまぜTi
N膜を形成する反応性スパッタリングを示したが、この
場合窒素イオンはターゲット1表面もしくは気相中でT
iと反応しTiNとなりウエハ2に付着する。図1−B
は、コリメータ7の部分拡大図である。コリメータ7も
電気的にグランドである。ターゲット1近傍もしくは気
相中で形成されたTiN分子8のうち一部はコリメータ
7に付着し、一部はコリメータ7を通過しウエハ3に付
着する。コリメータ7に付着したTiNはウエハ2側で
特に低エネルギー状態で付着するため付着強度は一般的
に低下し剥離が生じやすくなる傾向にあるが、TiNも
しくはTiと非常に密着性の良いTiでコーティングさ
れているコリメータ7であるためエネルギーの低いTi
N分子の密着性も非常に良い。
Next, the operation will be described. Normally, the sputtering method is performed by applying a negative bias to the target 1 and establishing a plasma between the target 2 and the wafer 2. Since the wafer 2, the shield 5, and the shutter 6 are grounded, all argon ions and nitrogen ions in the plasma go to the target 1. When the argon ions collide with the target 1, the target 1
The atoms that make up pop out in random directions. In Example 1, nitrogen gas was mixed with argon gas to Ti.
Reactive sputtering to form an N film was shown, but in this case, the nitrogen ions are T
It reacts with i to become TiN and adheres to the wafer 2. Figure 1-B
FIG. 4 is a partially enlarged view of the collimator 7. The collimator 7 is also electrically grounded. Part of the TiN molecules 8 formed in the vicinity of the target 1 or in the vapor phase adheres to the collimator 7, and part of the TiN molecule 8 passes through the collimator 7 and adheres to the wafer 3. The TiN adhering to the collimator 7 adheres in a particularly low energy state on the wafer 2 side, so that the adhesion strength generally decreases and peeling tends to occur easily. However, TiN or Ti which has a very good adhesion with Ti is coated. Since the collimator 7 is used, Ti with low energy
The adhesion of N molecules is also very good.

【0012】この構成で実施した場合のパーティクル結
果をグラフにして図2に示す。このグラフは、コリメー
ションスパッタにTiNをウエハ上に約1000オング
ストローム成膜をした時の膜中、もしくは膜上のパーテ
ィクルをレーザ光散乱方式のパーティクルカウンタにて
測定したものである。従来例図5では10枚目から急に
パーティクルが増大し最大で0.8個/cm2になるの
に対し、この場合は50枚目でも0.2個/cm2と1
/4以下に減少していることが確認された。
FIG. 2 is a graph showing the results of particles in the case of implementation with this configuration. This graph is obtained by measuring particles in or on the film when TiN is deposited on the wafer by collimation sputtering to a thickness of about 1000 angstroms using a laser light scattering type particle counter. In the conventional example FIG. 5, the number of particles suddenly increases from the 10th sheet to a maximum of 0.8 particles / cm 2 , whereas in this case the 50th sheet has 0.2 particles / cm 2 and 1
It was confirmed that the number was decreased to / 4 or less.

【0013】実施例2.実施例1では、TiNをスパッ
タする場合、コリメータをTiでコーティングする場合
について述べたが、Tiをスパッタする場合にも適用可
能である。またさらにコリメータをTiWもしくはTi
/TiWでコーティングした場合はTiWをスパッタす
る場合に、コリメータをTi/Al係合金もしくはAl
係合金でコーティングした場合はAl係合金をスパッタ
する場合に、コリメータをW、もしくはTi/Wもしく
はTi/TiW/Wでコーティングした場合はWスパッ
タに、コリメータをWSixでコーティングした場合
は、WSixスパッタにそれぞれ応用可能である。一般
的にターゲット材料と同一の材料でコリメータの全表面
をコーティングしてあれば同様のパーティクル低減効果
が得られる。
Example 2. In the first embodiment, the case where TiN is sputtered and the case where the collimator is coated with Ti has been described, but the present invention is also applicable to the case where Ti is sputtered. In addition, the collimator is TiW or Ti
When coating with Ti / TiW, the collimator is Ti / Al engaging gold or Al when spattering TiW.
Al when the engagement gold is coated, when Al engagement gold is sputtered, when the collimator is W, or when Ti / W or Ti / TiW / W is coated, W spatter, when the collimator is coated by WSix, WSix sputter Can be applied to each. Generally, if the same material as the target material is coated on the entire surface of the collimator, the same particle reduction effect can be obtained.

【0014】実施例3.実施例1及び2では、ステンレ
ス鋼等により構成されたコリメータをターゲット材料と
同一の材料でコーティングする場合について述べたが、
コリメータそのものを、ターゲット材料と同一の物質で
作成する場合も同一の効果が得られる。例えばコリメー
タをTiで作成すればコーティングをすることなしで、
TiN、Tiスパッタ時のパーティクル低減を計ること
ができる。
Example 3. Although the first and second embodiments describe the case where the collimator made of stainless steel or the like is coated with the same material as the target material,
The same effect can be obtained when the collimator itself is made of the same material as the target material. For example, if the collimator is made of Ti without coating,
It is possible to reduce particles during TiN and Ti sputtering.

【0015】実施例4.実施例1〜3ではスパッタ法に
よる装置の場合について述べたが、蒸着法による装置に
ついても適用可能でこの場合、真空容器内に配置され被
付着金属である蒸着金属の方向性をそろえるコリメータ
について、蒸着金属が接する全ての表面が蒸着金属と同
一材料でコーティングしたものであるか、又はコリメー
タが蒸着金属と同一材料で作成されていれば上記各実施
例と同等の効果を上げることができる。
Example 4. In Examples 1 to 3, the case of the apparatus by the sputtering method was described, but it is also applicable to the apparatus by the vapor deposition method, and in this case, the collimator for arranging the directionality of the vapor deposition metal which is the metal to be deposited and is placed in the vacuum container, If all surfaces contacting the vapor deposition metal are coated with the same material as the vapor deposition metal, or if the collimator is made of the same material as the vapor deposition metal, it is possible to obtain the same effect as each of the above embodiments.

【0016】[0016]

【発明の効果】以上のようにこの発明によれば、ウエハ
に付着する被付着金属に方向性を付けるコリメータは少
なくとも被付着金属と接する表面を被付着金属と同一材
料で構成したのでコリメータに付着した被付着金属が密
着性を強くし剥離してウエハに飛散するパーティクル発
生が少なくなり高信頼度の半導体製造装置が得られる効
果がある。
As described above, according to the present invention, since the collimator for directing the adhered metal adhered to the wafer has at least the surface in contact with the adhered metal made of the same material as the adhered metal, the collimator adheres to the collimator. There is an effect that the adhered metal has a strong adhesiveness, is less likely to be peeled off and scattered on the wafer, and a highly reliable semiconductor manufacturing apparatus can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例1における半導体製造装置の
模式構成を示す断面図で、Aにスパッタチャンバの全体
構成図をBにコリメータの部分拡大図を示している。
FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor manufacturing apparatus according to a first embodiment of the present invention, in which A is an overall configuration diagram of a sputtering chamber and B is a partially enlarged view of a collimator.

【図2】この発明の実施例1によるパーティクル発生結
果を示すグラフである。
FIG. 2 is a graph showing a result of particle generation according to the first embodiment of the present invention.

【図3】従来の半導体製造装置の模式構成を示す断面図
である。
FIG. 3 is a sectional view showing a schematic configuration of a conventional semiconductor manufacturing apparatus.

【図4】図3におけるコリメーション模式図を示したも
のでAにコリメーション状況図をBにコリメータのハニ
カム状のメッシュを示したものである。
4 is a schematic diagram of the collimation in FIG. 3, in which A is a collimation situation diagram and B is a honeycomb mesh of the collimator.

【図5】従来の半導体製造装置におけるパーティクル発
生結果を示すグラフである。
FIG. 5 is a graph showing a result of particle generation in a conventional semiconductor manufacturing apparatus.

【符号の説明】[Explanation of symbols]

1 ターゲット 2 ウエハ 4 真空容器(チャンバ) 7 コリメータ 7a コリメータ本体 7b 被覆材(被付着金属と同一材料) 8 被付着金属 1 Target 2 Wafer 4 Vacuum Container (Chamber) 7 Collimator 7a Collimator Main Body 7b Coating Material (Same Material as Metal to Be Adhered) 8 Metal to Adhere

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 被付着金属に方向性を付けるコリメータ
を備え上記被付着金属をウエハに付着する半導体製造装
置において、上記コリメータは少なくとも上記被付着金
属と接する表面を上記被付着金属と同一材料で構成して
いることを特徴とする半導体製造装置。
1. A semiconductor manufacturing apparatus, comprising: a collimator for directing a metal to be adhered, for adhering the metal to be adhered onto a wafer, wherein the collimator is made of the same material as the metal to be adhered at least on a surface in contact with the metal to be adhered. A semiconductor manufacturing apparatus characterized by being configured.
【請求項2】 コリメータは被付着金属と接する全表面
を上記被付着金属と同一材料でコーティングしているこ
とを特徴とする請求項1に記載の半導体製造装置。
2. The semiconductor manufacturing apparatus according to claim 1, wherein the collimator has the entire surface in contact with the metal to be adhered coated with the same material as the metal to be adhered.
JP22408192A 1992-08-24 1992-08-24 Apparatus for production of semiconductor Pending JPH0665731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22408192A JPH0665731A (en) 1992-08-24 1992-08-24 Apparatus for production of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22408192A JPH0665731A (en) 1992-08-24 1992-08-24 Apparatus for production of semiconductor

Publications (1)

Publication Number Publication Date
JPH0665731A true JPH0665731A (en) 1994-03-08

Family

ID=16808266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22408192A Pending JPH0665731A (en) 1992-08-24 1992-08-24 Apparatus for production of semiconductor

Country Status (1)

Country Link
JP (1) JPH0665731A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0718423A (en) * 1993-07-06 1995-01-20 Japan Energy Corp Thin film forming device
JPH08124857A (en) * 1994-10-20 1996-05-17 Nec Corp Sputtering device and manufacture of semiconductor by use of it
US5565708A (en) * 1994-10-06 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising composite barrier layer
KR20020091336A (en) * 2001-05-30 2002-12-06 주식회사 코미코 method for removing titanium and titanium nitride deposited on titanium collimator using sacrificeal layer
KR100474983B1 (en) * 1997-05-26 2005-04-14 삼성전자주식회사 Sputter with collimator for manufacturing semiconductor device

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JPS545882A (en) * 1977-06-17 1979-01-17 Hitachi Ltd Evaporating device
JPS62218557A (en) * 1986-03-19 1987-09-25 Nec Kansai Ltd Device for vapor deposition
JPS63238263A (en) * 1987-03-25 1988-10-04 Seiko Epson Corp Dustproof plate for vacuum film forming device
JPH01116070A (en) * 1987-10-29 1989-05-09 Internatl Business Mach Corp <Ibm> Sputtering apparatus

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS545882A (en) * 1977-06-17 1979-01-17 Hitachi Ltd Evaporating device
JPS62218557A (en) * 1986-03-19 1987-09-25 Nec Kansai Ltd Device for vapor deposition
JPS63238263A (en) * 1987-03-25 1988-10-04 Seiko Epson Corp Dustproof plate for vacuum film forming device
JPH01116070A (en) * 1987-10-29 1989-05-09 Internatl Business Mach Corp <Ibm> Sputtering apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0718423A (en) * 1993-07-06 1995-01-20 Japan Energy Corp Thin film forming device
US5565708A (en) * 1994-10-06 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising composite barrier layer
JPH08124857A (en) * 1994-10-20 1996-05-17 Nec Corp Sputtering device and manufacture of semiconductor by use of it
KR100474983B1 (en) * 1997-05-26 2005-04-14 삼성전자주식회사 Sputter with collimator for manufacturing semiconductor device
KR20020091336A (en) * 2001-05-30 2002-12-06 주식회사 코미코 method for removing titanium and titanium nitride deposited on titanium collimator using sacrificeal layer

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