JPH065771A - Multilayer lead frame and semiconductor device - Google Patents

Abstract

PURPOSE:To provide a multilayer lead frame having excellent electric characteristics for high rate signal which can be manufactured easily and a semiconductor device excellent in high rate characteristics. CONSTITUTION:The multilayer lead frame comprises a platelike first layer 10 to be used as a ground layer or a power supply layer, a framelike second layer 12 laminated on the first layer to be used as a power supply layer or a ground layer, and a signal layer 14 laminated on the second layer, wherein a decoupling capacitor 18 comprising a dielectric part 18a having predetermined capacitance is provided at a position on the first layer 10 other than the joint to the second layer 12 while being connected electrically with the first layer 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer lead frame and a semiconductor device.

[0002]

2. Description of the Related Art Multi-layer lead frames are used for signal layers, power layers,
A plurality of layers such as ground layers are laminated with an electrically insulating layer such as polyimide sandwiched between the layers. In this multilayer lead frame, the power supply layer and the ground layer are formed in a plane shape, but this can reduce the self-inductance of the power supply layer and the ground layer, and it is possible to avoid current concentration on specific leads. As a result, there is an effect of reducing noise due to current fluctuations. As a result, it is possible to mount high-speed elements of several tens of MHz in semiconductor devices that use multi-layer lead frames.

However, when a high-speed element such as 100 MHz or more is mounted, the influence of noise due to potential fluctuations appears more significantly, so it is necessary to further reduce noise. Therefore, a decoupling capacitor is inserted between the power supply lead and the ground lead. When providing a decoupling capacitor, it has been conventionally provided in a circuit outside the semiconductor device.However, if the connection distance between the semiconductor chip and the decoupling capacitor becomes longer, the self-inductance becomes larger. It is effective to arrange them.

Since the multilayer lead frame is formed by laminating power source layers and the like, it is possible to function as a decoupling capacitor by sandwiching a material having a high dielectric constant between the layers. The present applicant has previously proposed a multilayer lead frame in which a decoupling capacitor is arranged between the layers (Japanese Patent Application No. 3-350212). Since the semiconductor chip can be mounted close to the semiconductor chip in the multi-layered lead frame incorporating the decoupling capacitor, it is possible to effectively improve the electrical characteristics for high-speed signals.

[0005]

However, it is not easy to form a high dielectric constant material between layers in a multilayer lead frame in an actual manufacturing process. For example, in a method of forming a decoupling capacitor by mixing a material having a high dielectric constant with an electrical insulator that joins layers and joining the layers, the capacitance may fluctuate due to variations in film thickness. Even when a film having a dielectric constant of 2 is sandwiched, it is not easy to stack a power source layer or the like with a film interposed therebetween. Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to easily manufacture a multi-layer lead frame incorporating a decoupling capacitor and to obtain electrical characteristics for high-speed signals. Another object of the present invention is to provide an excellent multilayer lead frame and semiconductor device.

[0006]

The present invention has the following constitution in order to achieve the above object. That is, a plate-shaped first layer used as a ground layer or a power supply layer, a frame-shaped second layer used as a power supply layer or a ground layer laminated on the first layer, and the first layer In a multilayer lead frame having a signal layer laminated on two layers, a dielectric layer having a required electric capacitance value on a portion of the first layer, which is outside the bonding range of the second layer to the first layer. It is characterized in that a decoupling capacitor having a body portion is installed so as to be electrically connected to the first layer. Further, the decoupling capacitor is installed outside the joining range and outside the mounting range of the semiconductor chip. In addition, a plate-shaped first layer used as the ground layer or the power supply layer, and a frame-shaped second layer used as the power supply layer or the ground layer laminated on the first layer, In a multilayer lead frame having a signal layer laminated on a second layer, a dielectric having a required electric capacitance value on a portion of the second layer, which is outside the bonding range of the signal layer to the second layer, on the second layer. Decoupling condenser with
It is characterized in that it is installed by being electrically connected to the second layer. Also, in a multi-layer lead frame in which a signal layer is laminated on a first layer formed in the shape of a plate used as the ground layer or the power layer, the signal layer is bonded to the first layer on the first layer. A decoupling capacitor having a dielectric portion having a required electric capacitance value is electrically connected to the first layer and installed at a portion outside the range. Further, as the decoupling capacitor, the decoupling capacitors are separated and arranged in an island shape, or are formed in a frame shape, or directly on the bonding surface of the ground layer or the like by a sputtering method or the like. It is effective to use a bonding sheet in which a metal via is formed on an insulating sheet having electrical insulation and an adhesive function on the bonding surface such as a ground layer or the like. . In a semiconductor device having a semiconductor chip mounted on the multilayer lead frame, the decoupling capacitor is relayed to electrically connect the semiconductor chip to a required ground layer, power supply layer, and signal layer by wire bonding. Is characterized by.

[0007]

[Operation] By arranging the decoupling capacitor at a relay position when joining the semiconductor chip and the power supply layer or the like on the ground layer or the power supply layer, the decoupling capacitor is formed between the ground layer and the power supply layer by wire bonding. It can be inserted and connected as a circuit. Accordingly, it is possible to provide a multi-layer lead frame having excellent electrical characteristics for high speed signals. Further, the decoupling capacitor can be easily manufactured by providing the decoupling capacitor outside the joining range where the ground layer and the power supply layer are joined.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a sectional view showing the structure of an embodiment of a multilayer lead frame according to the present invention. In the figure, 10 is a ground layer of a multi-layer lead frame, 12 is a power layer, 1
4 is a signal layer. The ground layer 10 is formed in a rectangular plate shape, and the power supply layer 12 is formed in a frame shape having the same outer size as the ground layer 10. The ground layer 10, the power supply layer 12, and the signal layer 14 are laminated with an electrically insulating layer 16 interposed therebetween. In this embodiment, the ground layer 10 is the first layer, the power supply layer 12 is the second layer, and the signal layer 14 is the third layer. Ground layer 10 and power layer 1
Connecting pieces 10a and 12a are respectively provided on the outer edges of 2,
The connection piece 10a is resistance-welded to the ground lead of the signal layer 14,
The connection piece 12a is resistance-welded to the power supply lead of the signal layer 14. As a result, the ground layer 10 is set to the ground potential and the power layer 1
2 is set to a predetermined power supply potential.

In FIG. 1, reference numeral 18 is a decoupling capacitor formed on the ground layer 10. The decoupling capacitor 18 is installed inside the power supply layer 12 and outside the mounting position of the semiconductor chip 20. FIG. 2 shows a planar arrangement of the decoupling condenser 18. In this embodiment, the decoupling capacitor 18 is formed in a discontinuous island shape, but it may be formed by connecting in a frame shape. Reference numeral 22 is an inner lead of the signal layer. As shown in FIG. 1, the decoupling capacitor 18 has a layered electrode portion 18b for electrical connection with the dielectric portion 18a by wire bonding in the thickness direction.

FIG. 3 shows a method of forming the decoupling capacitor 18 on the ground layer 10. In FIG. 3A, the dielectric portion 18a is directly formed by the sputtering method using the ground layer 10 as a base, and the electrode portion 18b is further formed thereon. FIG. 3 (b) shows a component in which the dielectric portion 18a is formed on one surface of the electrode 18b in advance and is joined to the ground layer 10 with solder or conductive paste. FIG. 3 (c) shows a structure in which electrodes 18b are previously formed on both surfaces of the dielectric part 18a and the parts are joined to the ground layer 10 by using solder or conductive paste 18c. It is effective in that it is possible to obtain the electric capacitance required as the decoupling capacitor without variation, whether the dielectric part is formed by the above-mentioned sputtering method or when the dielectric part is formed on the electrode in advance.

As shown in FIG. 1, after mounting the semiconductor chip 20 on the ground layer 10, the decoupling capacitor 18 is relayed by the decoupling capacitor 18 when the semiconductor chip 20 and the power supply layer 12 are connected. Wire bonding is used between them. By wire bonding in this way, a circuit configuration is obtained in which a decoupling capacitor is inserted between the ground layer 10 and the power supply layer 12. Thus, by inserting the decoupling capacitor 18 between the ground layer 10 and the power supply layer 12, it is possible to suitably suppress the fluctuation of the power supply potential and improve the high-speed signal characteristics of the semiconductor device. In addition, the decoupling capacitor 18 is the semiconductor chip 2
Since it is installed close to 0, the inductance component can be effectively reduced.

When the semiconductor chip 20 and the ground layer 10 are connected, and when the semiconductor chip 20 and the signal layer 14 are connected, they are connected by wire bonding as in the conventional case. Although the bottom layer is the ground layer in the above embodiment, the ground layer and the power layer may be reversed and the bottom layer may be the power layer and the intermediate layer may be the ground layer. The multi-layered lead frame of the above embodiment can be provided as a lead frame having excellent high-speed signal characteristics by incorporating a decoupling capacitor, and it is possible to suitably cope with mounting an extremely high-speed element.

FIG. 4 shows another embodiment of a multilayer lead frame incorporating a decoupling capacitor. This embodiment is characterized in that the decoupling capacitor 18 is arranged at the inner peripheral edge portion on the power supply layer 12 laminated on the ground layer 10. When the decoupling capacitor 18 is formed, as described above, the dielectric part may be directly formed on the power supply layer 12 to form an electrode, or the decoupling capacitor formed as a separate component may be bonded to the power supply layer 12. It depends on how to do. By wire-bonding the decoupling capacitor 18 and the ground layer 10 as shown in the figure, the decoupling capacitor can be inserted between the ground layer 10 and the power supply layer 12 in a circuit manner.

FIG. 5 shows an embodiment of a multi-layer lead frame consisting of two layers, the ground layer 10 and the signal layer 14. In this embodiment, similarly to the embodiment shown in FIG. 1, the decoupling capacitor 18 is installed on the ground layer 10 and the semiconductor chip 20 and the signal layer 14 are connected by relaying the decoupling capacitor 18. In the signal layer 14, the decoupling capacitor 18 is relayed to the power supply lead for wire bonding. As a result, a decoupling capacitor can be inserted between the ground layer 10 and the power supply lead in a circuit manner.

FIG. 6 shows a ground layer 10, a power source layer 12, and a signal layer 1.
This is an example in which the decoupling capacitor 18 is incorporated in the lower surface of the semiconductor chip 20 in the multilayer lead frame having the three-layer structure of No. 4 in FIG. Since a relatively large area can be secured on the lower surface of the semiconductor chip 20, there is an advantage that a large electric capacitance value can be obtained as a decoupling capacitor. When the decoupling capacitor 18 is installed on the ground layer 10 as shown in this embodiment and the other embodiments described above, it is necessary to electrically connect and bond to the ground layer. As shown in b) and (c), it is usual to use solder or a conductive adhesive for joining. However, in the case of joining using solder or the like, the adhesive may flow out to the end face of the joined object, causing an electrical short circuit at the end face.

In the embodiment shown in FIG. 6, the decoupling capacitor 18 is installed using a bonding sheet 30 in which a metal via is provided on an insulating sheet having adhesiveness in order to prevent such an electric short circuit. FIG. 7 shows the joining sheet 3
The state where the decoupling capacitor 18 is bonded onto the ground layer 10 by using 0 is shown in an enlarged manner. Joining sheet 30
Is an insulating sheet 30a formed of a material having an electrical insulating property and an adhesive function, and a large number of minute through holes are formed in the insulating sheet 30a.
b is formed. When the decoupling capacitor 18 is joined to the ground layer 10, the joining sheet 3
0 is sandwiched between the ground layer 10 and the decoupling capacitor 18 and joined by heating and pressurizing. The insulating sheet 30a of the joining sheet 30 joins each other, and the metal via 30b electrically connects the ground layer 10 and the electrode 18b.

Since the above-mentioned joining sheet 30 is formed in a thin thickness of about several tens of μm, it can be suitably used in a thin device. Further, since it is formed in a sheet shape, it is easy to handle, and it is possible to obtain a product having no variation in thickness when joined. Further, even if the products are joined by heating and pressurizing, the products do not run off from the end faces of the joined products and cause an electrical short circuit, and a highly reliable product can be reliably produced. In the bonding sheet 30, the decoupling capacitors are arranged on the lower surface of the semiconductor chip 20 as shown in FIG. 6, and the island-shaped decoupling capacitors are provided on the ground layer 10 as in the embodiment shown in FIG. The same can be applied to cases.

[0018]

The multi-layered lead frame according to the present invention is, for example, a multi-layered lead frame in which a power supply layer is joined to a ground layer, and a decoupling capacitor is installed outside the joining range to connect the semiconductor chip to the power supply layer and the like. By connecting the decoupling capacitor and wire-bonding it when performing the decoupling capacitor, the decoupling capacitor can be easily inserted in the ground layer and the power supply layer in terms of a circuit. Also,
Since the decoupling capacitor can be arranged close to the mounting position of the semiconductor chip, it can be provided as a multi-layer lead frame having excellent electrical characteristics for high-speed signals. It also facilitates the incorporation of decoupling capacitors. Further, by using the multilayer lead frame according to the present invention, it becomes possible to mount a high-speed element, and it is possible to provide a semiconductor device having excellent high-speed characteristics, which is remarkably effective.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of an example of a multilayer lead frame.

FIG. 2 is an explanatory diagram showing a planar arrangement of decoupling capacitors.

FIG. 3 is an explanatory diagram showing a method for forming a decoupling capacitor.

FIG. 4 is a cross-sectional view showing the configuration of another embodiment of the multilayer lead frame.

FIG. 5 is a cross-sectional view showing an example of a two-layer lead frame.

FIG. 6 is an explanatory diagram showing the configuration of still another embodiment of the multilayer lead frame.

FIG. 7 is an explanatory diagram showing a state in which a decoupling capacitor is joined using a joining sheet.

[Explanation of symbols]

 10 Ground Layer 12 Power Layer 14 Signal Layer 16 Electrical Insulation Layer 18 Decoupling Capacitor 18a Dielectric Part 18b Electrode Part 18c Conductive Paste 20 Semiconductor Chip 22 Inner Lead 30 Bonding Sheet 30a Insulation Sheet 30b Metal Via

Claims (9)

[Claims] 1. A plate-shaped first layer used as a ground layer or a power supply layer, and a frame-shaped second layer used as a power supply layer or a ground layer laminated on the first layer. A multi-layer lead frame having a signal layer laminated on the second layer, wherein a required electric capacitance value is provided on a portion of the first layer outside the bonding range of the second layer with respect to the first layer. A multi-layered lead frame, wherein a decoupling capacitor having a dielectric part having: is installed so as to be electrically connected to the first layer. 2. The multi-layered lead frame according to claim 1, wherein a decoupling capacitor is provided outside the joining range and outside the mounting range of the semiconductor chip. 3. A plate-shaped first layer used as a ground layer or a power supply layer, and a frame-shaped second layer used as a power supply layer or a ground layer laminated on the first layer. A multi-layer lead frame having a signal layer laminated on the second layer, having a required electric capacitance value on a portion of the second layer outside the bonding range of the signal layer to the second layer. A multi-layered lead frame, wherein a decoupling capacitor having a dielectric part is installed by being electrically connected to the second layer. 4. A multi-layer lead frame in which a signal layer is laminated on a plate-shaped first layer used as a ground layer or a power supply layer, wherein the first layer of the signal layers is provided on the first layer. A multi-layer lead frame, wherein a decoupling capacitor having a dielectric part having a required electric capacitance value is electrically connected to the first layer and installed at a portion outside the junction range with respect to. 5. The decoupling capacitor is arranged in an island-shaped manner so as to be separated from each other.
The multilayer lead frame according to 3 or 4. 6. The multilayer lead frame according to claim 1, wherein the decoupling capacitor is formed in a frame shape. 7. The decoupling capacitor has a dielectric portion directly formed on a bonding surface such as a ground layer by a sputtering method or the like.
The multi-layered lead frame described in 2, 3, or 4. 8. The decoupling capacitor is bonded on a bonding surface such as a ground layer by using a bonding sheet in which a metal via is formed on an insulating sheet having an electrical insulating property and an adhesive function. The multilayer lead frame according to claim 1, 2, 3, or 4. 9. A semiconductor device in which a semiconductor chip is mounted on the multilayer lead frame according to claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein the semiconductor chip is formed by relaying the decoupling capacitor. A semiconductor device characterized in that required ground layers, power layers, and signal layers are electrically connected by wire bonding.