JPH0654802B2 - Solid-state imaging device - Google Patents

Solid-state imaging device

Info

Publication number
JPH0654802B2
JPH0654802B2 JP60072891A JP7289185A JPH0654802B2 JP H0654802 B2 JPH0654802 B2 JP H0654802B2 JP 60072891 A JP60072891 A JP 60072891A JP 7289185 A JP7289185 A JP 7289185A JP H0654802 B2 JPH0654802 B2 JP H0654802B2
Authority
JP
Japan
Prior art keywords
solid
adhesive
chip
angle
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60072891A
Other languages
Japanese (ja)
Other versions
JPS61231757A (en
Inventor
哲義 竹下
修一 松尾
一 栗原
秀明 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60072891A priority Critical patent/JPH0654802B2/en
Publication of JPS61231757A publication Critical patent/JPS61231757A/en
Publication of JPH0654802B2 publication Critical patent/JPH0654802B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/042Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/1446Devices controlled by radiation in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数個のチップを配列した固体撮像装置の実装
構造に関する。
The present invention relates to a mounting structure of a solid-state imaging device in which a plurality of chips are arranged.

〔発明の概要〕[Outline of Invention]

本発明は複数個のチップを配列した固体撮像装置におい
て、チップの接続面が素子面と90゜以外の角度を有す
ることにより、接着剤の逃げ場が作られ接着剤の素子面
への影響が無くなるとともに接続部での乱反射を減少
し、なおかつ線接続に近くなり配列精度が向上するよう
にしたものである。
According to the present invention, in a solid-state image pickup device in which a plurality of chips are arranged, when the connecting surface of the chips has an angle other than 90 ° with the element surface, an escape area for the adhesive is created and the effect of the adhesive on the element surface is eliminated. At the same time, the diffused reflection at the connection portion is reduced, and the arrangement accuracy is improved because it is close to the line connection.

〔従来の技術〕[Conventional technology]

固体撮像装置に用いられる素子チップの大型化が進んで
いるこの項であるが、ファクシミリなどの応用分野にお
いて装置全体の小型化、経済化のすぐれた等倍型で原稿
幅大の撮像素子の有用性が注目されている。さらに受光
素子の駆動部分も同一チップ内に形成することで外部へ
の引き出し配線数の少ない高速高性能で経済性のすぐれ
た固体撮像装置となる。しかし現在の高性能な半導体能
動素子を形成する装置を用いて原稿幅の大きさの素子チ
ップを形成することは困難を極める。そこで複数個のチ
ップを配列するマルチチップ型固体撮像装置が考えられ
るが、チップの配列精度や配列方法に未解決な問題が多
い。
In this section, the size of element chips used in solid-state image pickup devices is increasing, but in the field of application such as facsimiles, it is useful to use image pickup devices of the same size and wide original size, which are excellent in downsizing of the entire device and economy. The sex is drawing attention. Further, by forming the driving portion of the light receiving element in the same chip, a solid-state image pickup device with a small number of wirings leading to the outside, high speed and high performance, and excellent economy can be obtained. However, it is extremely difficult to form an element chip having the size of the document width using the present apparatus for forming a high-performance semiconductor active element. Therefore, a multi-chip type solid-state imaging device in which a plurality of chips are arranged is conceivable, but there are many unsolved problems in the chip arrangement accuracy and the chip arrangement method.

従来、接続部で第2図に示すように接続面(23)は素
子面(22)に垂直に切断されており2つの接続面は面
と面が平行に向かい合っていた。
Conventionally, as shown in FIG. 2, the connecting surface (23) is cut perpendicularly to the element surface (22) at the connecting portion, and the two connecting surfaces face each other in parallel with each other.

〔発明が解決しようとする問題点及び目的〕[Problems and Objectives to be Solved by the Invention]

しかし、従来技術では基板(21)にチップを接着剤で
固定する際に2つの接続面の間を伝わって接着剤が素子
面(22)にまで回り込んでしまい素子面の受光素子に
光学的悪影響をおよぼすばかりでなく能動素子を含めて
信頼性にまで影響をおよぼした。この傾向は素子面同士
を近づけて隣接素子の配置精度をよくすればするほど強
くなるものである。また、さらに面同士の接続のため接
続面の表面の凹凸をミクロンオーダにおとすことは頗る
困難であり、配置精度が悪くなって隣接素子間距離に大
きな誤差を生じる。これはまた、接続面間に入り込んだ
接着剤の厚みでも生じる誤差である。以上のように、従
来技術では接続する2つのチップ上の隣接素子(ビッ
ト)を近づけることも精度よく配置することもできない
というマルチチップ固体撮像装置の本質的な問題点とな
っていた。
However, in the prior art, when the chip is fixed to the substrate (21) with an adhesive, the adhesive propagates between the two connecting surfaces and wraps around to the element surface (22), and the light receiving element on the element surface is optically affected. Not only does it have an adverse effect, but it also affects the reliability, including active devices. This tendency becomes stronger as the element surfaces are brought closer to each other to improve the placement accuracy of the adjacent elements. In addition, it is extremely difficult to make the surface irregularities of the connection surface on the order of microns because of the connection between the surfaces, and the placement accuracy deteriorates, causing a large error in the distance between adjacent elements. This is also an error caused by the thickness of the adhesive that has entered between the connection surfaces. As described above, the conventional technique has an essential problem of the multi-chip solid-state imaging device in which the adjacent elements (bits) on the two chips to be connected cannot be brought close to each other or accurately arranged.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところはマルチチップ固体撮像装置におい
て、2つのチップの隣接素子を近づけて精度よく配置で
きる構造を提供するところにある。
Therefore, the present invention solves such a problem, and an object of the present invention is to provide a structure capable of accurately arranging adjacent elements of two chips close to each other in a multi-chip solid-state imaging device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、複数個の撮像素子が配置された素子チップ
が、平面的に接続されてなる固体撮像装置において、該
素子チップが形成する面のうち、該撮像素子の配置され
た素子面と、該素子面に隣接する面でかつ他の素子チッ
プと接続するための接続面とがなす角度を90゜未満と
し、該角度により形成される空間を素子チップを接続す
るための接着剤の塗布空間とし、該塗布空間によって該
素子面への接着剤のはみ出しを防止することを特徴とす
る。
The present invention is a solid-state imaging device in which element chips having a plurality of imaging elements arranged are planarly connected, and among the surfaces formed by the element chips, an element surface on which the imaging element is arranged, An angle formed by a surface adjacent to the element surface and a connection surface for connecting to another element chip is less than 90 °, and a space formed by the angle is applied with an adhesive for connecting the element chips. The application space prevents the adhesive from protruding to the element surface.

〔実施例〕〔Example〕

第1図は本発明により配列された2つのチップの接続部
の図面である。この図で画素A(17)と画素B(1
8)同一チップ上の隣接素子間隔(16ドット/mmの装
置で62.5μm)と同一間隔にする必要がある。つまり、
それぞれ素子幅を50μmとすると素子端では12.5μm
幅で接続しなければならない。本発明では素子面(1
2)と接続面(14)とで作られる角(15)の角度を
90゜未満の鋭角として、チップ側面から見ると逆くさ
び状の空間を有して接続されることになる。この角度の
大きさについては後に述べるが、この様な形状にするこ
とで2つのチップの接触部分は13の接続線となり線接
触となる。このことで接続間隔は接続面の凹凸にほとん
ど影響されずにゼロに近くなる。チップ材料として厚さ
1mm程度の石英板を用いたときにこの凹凸を切断のみで
10μm以下にすることは困難である。2つのチップを
単につき合わせるだけで十分な配列精度を得ることがで
きる。
FIG. 1 is a drawing of a connecting portion of two chips arranged according to the present invention. In this figure, pixel A (17) and pixel B (1
8) It is necessary to have the same spacing as the spacing between adjacent elements on the same chip (62.5 μm in a 16-dot / mm device). That is,
If the element width is 50 μm, the edge is 12.5 μm.
Must connect in width. In the present invention, the element surface (1
When the angle (15) formed by 2) and the connecting surface (14) is an acute angle of less than 90 °, they are connected with an inverted wedge-shaped space when viewed from the side surface of the chip. The magnitude of this angle will be described later, but by making such a shape, the contact portions of the two chips become 13 connection lines and are in line contact. As a result, the connection interval is close to zero without being affected by the unevenness of the connection surface. When a quartz plate having a thickness of about 1 mm is used as a chip material, it is difficult to reduce the unevenness to 10 μm or less only by cutting. Sufficient alignment accuracy can be obtained by simply aligning two chips.

上記の構造でチップを基板(11)に固定する訳である
が、固定に接着剤を用いると従来例では第2図で25の
接着剤が接続面を伝わって22の素子面にまで回り込ん
でしまい、レンズ作用などをして画素に影響を及ぼす。
本発明では接続が線接触となるばかりでなく、この接着
剤の回り込みが互いの接続面(14)の間の逆くさび状
の隙間で緩和され、素子面(12)へ回り込むことはな
くなる。つまり、画素などの素子への影響が無くなる訳
である。
With the above structure, the chip is fixed to the substrate (11). However, if an adhesive is used for fixing, in the conventional example, the adhesive 25 in FIG. 2 travels along the connection surface and reaches the element surface 22. This will affect the pixels by acting as a lens.
In the present invention, not only the connection becomes a line contact, but also the wraparound of the adhesive is alleviated by the inverted wedge-shaped gap between the connecting surfaces (14), so that the adhesive does not wrap around to the element surface (12). In other words, the influence on elements such as pixels is eliminated.

ここで、基板(11)及びチップの材料に透明なものを
用いて11の基板側から光を入射するタイプの固体撮像
装置を考えた場合、接続面に近づけて画素を配置するこ
と(第1図の画素A,Bなど)は接続面で光の乱反射を
生じる。このために、たとえば接続面間に基板材料の屈
折率に近い接着剤を充填する方法が考えられるが、前記
の理由で素子面に回り込んでしまい実装上で重要な問題
となっていた。本発明の構造を用いれば、この問題も必
然的に解決され難無く接着剤をチップ間(接続面間)に
充填可能である。
Here, when considering a solid-state imaging device of a type in which light is incident from the substrate side of 11 using transparent materials for the substrate (11) and the chip, pixels should be arranged close to the connection surface (first Diffuse reflection of light occurs at the connection surface of the pixels A and B in the figure). Therefore, for example, a method of filling an adhesive between the connection surfaces with an adhesive having a refractive index close to that of the substrate material can be considered, but it has been an important problem in mounting because it wraps around the element surface for the above reason. By using the structure of the present invention, this problem is inevitably solved and the adhesive can be filled between the chips (between the connecting surfaces) without difficulty.

第1図で15の角であるが、チップの材料や接着剤の種
類、またチップの形状によって変わってくる。例とし
て、チップ材料して石英の厚さが0.2mmから3.0mmのもの
を用い、接着剤として粘度が10poiseでUV硬化型を
用いて配列した結果を示す。第1図の15の角度を89.5
度(上記の条件で接続線(13)が完全に接触している
とチップ下部での隙間は20μm程度となる角度)以上
とすると、そろそろ素子面への接着剤の回り込みが現わ
れるとともに接続面(14)(切断面)の凹凸(10μ
m程度)が影響して配列精度が悪くなってくる。また、
84.5度(チップ下部での隙間が200μm程度となる角
度)以上になるとチップ間の接続部分である接続線
(B)の強度が不足しはじめて、チップ材料である石英
が欠けて画素などの素子に影響を与えはじめる。したが
って素子面と接続面がなす角度は84.5度から89.5度まで
が上記材料、形状では最適である。しかし、材料や形
状、接着剤の種類などによって適する角度は大きく変化
する。
In FIG. 1, there are 15 corners, but they vary depending on the material of the chip, the type of adhesive, and the shape of the chip. As an example, the results of arranging using a chip material having a quartz thickness of 0.2 mm to 3.0 mm and using an UV curing type with an adhesive having a viscosity of 10 poise are shown. The angle of 15 in Fig. 1 is 89.5
When the contact line (13) is completely contacted under the above conditions, the gap at the bottom of the chip is about 20 μm), the wraparound of the adhesive to the element surface is about to occur and the connection surface ( 14) Unevenness of (cut surface) (10μ
(about m) affects the array accuracy. Also,
When the angle exceeds 84.5 degrees (the angle at which the gap at the bottom of the chip is about 200 μm) or more, the strength of the connecting line (B), which is the connecting part between chips, begins to become insufficient, and quartz, which is the chip material, is lacking, and it becomes an element such as a pixel. Begin to influence. Therefore, the angle between the element surface and the connection surface is optimally 84.5 to 89.5 degrees for the above materials and shapes. However, the suitable angle varies greatly depending on the material, shape, type of adhesive, and the like.

〔発明の効果〕〔The invention's effect〕

以上述べたように本発明によれば、素子面と接続面で作
られる角度を90°未満とすることで接続面間に逆くさ
び状の隙間を作り、接続面の凹凸の接続精度への影響を
無くし、接着剤の素子面への回り込みを防ぐとともにチ
ップ間の実質的な接着剤の詰り(接着剤がスペーサとな
るのを実質的に防ぐ)を無くす。また、基板側から光を
入れるタイプの固体撮像装置では、隙間を接着剤で確実
に埋めることができるので、光学特性の劣化を防ぐこと
ができる。
As described above, according to the present invention, the angle formed between the element surface and the connection surface is less than 90 ° to form an inverted wedge-shaped gap between the connection surfaces, and the unevenness of the connection surface affects the connection accuracy. To prevent the adhesive from wrapping around the element surface and to substantially prevent clogging of the adhesive between the chips (substantially preventing the adhesive from acting as a spacer). Further, in the solid-state imaging device of the type that allows light to enter from the substrate side, the gap can be reliably filled with the adhesive, so that deterioration of optical characteristics can be prevented.

このように、マルチチップ型の固体撮像装置でのチップ
配列精度は著しく向上し、接着剤が素子面に回り込むと
いう問題も解決されるという優れた効果を有する。
As described above, the chip arrangement accuracy in the multi-chip type solid-state imaging device is significantly improved, and the problem of the adhesive wrapping around the element surface is solved, which is an excellent effect.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による構造での接続部の拡大図であり、
第2図は従来の接続部の拡大図である。
FIG. 1 is an enlarged view of a connecting portion in the structure according to the present invention,
FIG. 2 is an enlarged view of a conventional connecting portion.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】複数個の撮像素子が配置された素子チップ
が、平面的に接続されてなる固体撮像装置において、 該素子チップが形成する面のうち、該撮像素子の配置さ
れた素子面と、該素子面に隣接する面でかつ他の素子チ
ップと接続するための接続面とがなす角度を90゜未満
とし、該角度により形成される空間を素子チップを接続
するための接着剤の塗布空間とし、該塗布空間によって
該素子面への接着剤のはみ出しを防止することを特徴と
する固体撮像装置。
1. A solid-state image pickup device comprising a plurality of image pickup devices arranged in a plane, wherein the device chips are connected to each other. An angle between the surface adjacent to the element surface and a connection surface for connecting to another element chip is less than 90 °, and an adhesive agent for connecting the element chip to the space formed by the angle is applied. A solid-state imaging device, characterized in that a space is provided, and the application space prevents the adhesive from protruding to the element surface.
【請求項2】前記素子チップは、厚さ0.2mm乃至0.3m
mの石英板であり、前記角度は、84.5゜以上89.5゜以下
であることを特徴とする特許請求の範囲第1項記載の固
体撮像装置。
2. The element chip has a thickness of 0.2 mm to 0.3 m.
The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is a quartz plate of m, and the angle is 84.5 ° or more and 89.5 ° or less.
JP60072891A 1985-04-05 1985-04-05 Solid-state imaging device Expired - Lifetime JPH0654802B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60072891A JPH0654802B2 (en) 1985-04-05 1985-04-05 Solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60072891A JPH0654802B2 (en) 1985-04-05 1985-04-05 Solid-state imaging device

Publications (2)

Publication Number Publication Date
JPS61231757A JPS61231757A (en) 1986-10-16
JPH0654802B2 true JPH0654802B2 (en) 1994-07-20

Family

ID=13502422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60072891A Expired - Lifetime JPH0654802B2 (en) 1985-04-05 1985-04-05 Solid-state imaging device

Country Status (1)

Country Link
JP (1) JPH0654802B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4668333A (en) * 1985-12-13 1987-05-26 Xerox Corporation Image sensor array for assembly with like arrays to form a longer array
JPH0740609B2 (en) * 1985-12-20 1995-05-01 セイコー電子工業株式会社 Method for manufacturing semiconductor device
JPS63139473A (en) * 1986-12-01 1988-06-11 Seiko Epson Corp Solid-state image pickup device
JP2609670B2 (en) * 1988-03-14 1997-05-14 株式会社東芝 Semiconductor chip for CCD linear sensor and method of manufacturing the same
JPH07122776A (en) * 1993-08-31 1995-05-12 Seiko Instr Inc Light-radiation-electricity conversion semiconductor device and application thereof
FR2712693B1 (en) * 1993-11-17 1995-12-15 Commissariat Energie Atomique Radiation detection device, with butted detection elements, and method of manufacturing this device.
JP5511181B2 (en) * 2008-12-25 2014-06-04 京セラ株式会社 Manufacturing method of optical element head

Also Published As

Publication number Publication date
JPS61231757A (en) 1986-10-16

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