JPH0653311A - Semiconductor intergrated circuit device - Google Patents

Abstract

PURPOSE:To prevent troubles caused due to a mutual noise interference between both circuits which lead to erroneous operations in a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted on the same substrate. CONSTITUTION:An insulating film 17 is formed on the entire surface of a P-type silicon substrate 16 and an N-type epitaxial layer 18 is formed on the insulating film 17 by SIO technology. P-type impurities having the same polarity as the substrate are implanted or diffused in the longitudinal direction of this N-type epitaxial layer 18 to form a P-type diffusion belt 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, at least one set of digital circuits and analog circuits are mixedly mounted on the same chip, and digital noise interference including low frequency noise output from the digital circuits is provided. The present invention relates to a semiconductor integrated circuit device provided with a separating means for preventing a trouble of an analog circuit due to the above.

[0002]

2. Description of the Related Art In recent years, along with the demand for miniaturization of equipment, a technique for integrating various circuits constituting the equipment or mixing a plurality of integrated circuits having different characteristics has been widely used. In this technological trend,
The combination of circuits, which are conventionally composed of digital circuits and analog circuits, which are separated from problems such as noise interference, is no exception, and mixed mounting on the same chip is being considered. However, it is impossible to shield each built-in circuit in a composite integrated circuit in which a digital circuit and an analog circuit are mixed, and since the circuits are adjacent to each other in a very close range, it is very necessary to take measures against noise contamination. It was very difficult.

For this reason, a special circuit for removing noise is often required, which raises the manufacturing cost and restricts miniaturization. That is, if digital noise including low-frequency noise emitted from a digital circuit leaks into the analog circuit, noise may be added to the analog circuit section that is uncomfortable with the mixing of noise to cause a malfunction. In particular, when analog circuits and digital circuits coexist on the same board, the board as a power supply is common, so measures such as installing a bypass capacitor between power supplies will provide a sufficient solution. Absent. Therefore, it becomes necessary to take some measures on the substrate.

For this purpose, a technique for separating a semiconductor integrated circuit has been conventionally proposed, and the technique is roughly divided into two techniques, a PN junction isolation and a high insulation layer isolation (IOP isolation). Among them, in the PN junction separation, the circuits are separated by utilizing the reverse breakdown voltage of P-type silicon and N-type silicon. For example, in the conventional semiconductor integrated circuit shown in FIG. 2, as a method of mitigating noise transmission between circuits, a method for reducing noise transmission between circuits is provided between a digital circuit area and an analog circuit area provided on a first semiconductor substrate having a first conductivity type. To some extent,
FIG. 2 is a cross-sectional view of a semiconductor integrated circuit to which a technique of mitigating noise transmission by providing a separation region (diffusion belt or insulating film belt) at the boundary is applied.

That is, in FIG. 2, the conventional semiconductor device has an N-type diffusion belt 12 between a digital circuit region and an analog circuit region provided on a P-type silicon substrate 11.
The noise transmission is alleviated by providing the. However, in the conventional semiconductor integrated circuit shown in FIG. 2, noise transmission between the digital circuit and the analog circuit is alleviated to a certain extent by the N-type diffusion belt 12, but the P-type silicon substrate 16 is completely separated. This method is not sufficient when a highly accurate analog circuit is required because it does not exist.

Therefore, as a method of completely separating the substrates of the digital circuit region and the analog circuit region to prevent noise interference, (1) the silicon substrate on which the digital circuit is formed and the silicon substrate on which the analog circuit is formed are separately provided. After creating, how to bond these boards,
(2) Like the conventional second semiconductor integrated circuit shown in FIG. 3, an N-type epitaxial layer 14 having a polarity opposite to that of the substrate is formed on the P-type silicon substrate 13, and the epitaxial layer 1 is formed.
4, a P-type impurity having the same polarity as that of the substrate is vertically injected or diffused to form a diffusion belt 15, and a digital circuit is formed on one side of the separated N-type epitaxial layer 14 and an analog circuit is formed on the other side. According to the method, the boards in the digital circuit area and the analog circuit area are separated.

[0007]

However, in the case of the method used in the above-mentioned conventional semiconductor integrated circuit device, that is, the method (1) in which the substrates for the digital circuit area and the analog circuit area are separately prepared, There is a problem that the manufacturing process of the semiconductor integrated circuit becomes complicated and the manufacturing cost increases. Further, in the case of the method (2) of forming the isolation region of opposite polarity in the epitaxial layer by diffusion, P
Since the area of the PN junction portion between the n-type silicon substrate portion and the n-type epitaxial layer is large, there is a problem that the parasitic capacitance in the pn reverse bias portion becomes large.

The present invention has been made to solve the above problems, and prevents noise interference between circuits in a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted on the same chip, and It is an object of the present invention to obtain a semiconductor integrated circuit device provided with a separating means capable of effectively preventing malfunction.

[0009]

In order to solve the above-mentioned problems, the first invention is a first semiconductor layer having a first conductivity type, and a first semiconductor layer laminated on the first semiconductor layer. An insulating film,
A second semiconductor layer laminated on the insulating film, the second semiconductor layer having a second conductivity type having a polarity opposite to that of the first conductivity type, wherein the second semiconductor layer is the first conductivity type. And a separation region that divides the second semiconductor layer into two regions, and a circuit is formed independently in each of the two regions.

In order to solve the above-mentioned problems, a second aspect of the present invention provides a first semiconductor layer having a first conductivity type and the first semiconductor layer.
An insulating film laminated on the semiconductor layer, and a second semiconductor layer laminated on the insulating film and having the first conductivity type, wherein the second semiconductor layer is the first semiconductor layer. Having a second conductivity type having a polarity opposite to that of the conductivity type, including a separation region that divides the second semiconductor layer into two regions, and a circuit being formed independently in each of the two regions. Is a semiconductor integrated circuit device.

[0011]

Therefore, according to the semiconductor integrated circuit device of the present invention, the respective circuits on the two regions formed in the second semiconductor layer have isolation regions of opposite polarities to the conductivity type of the second semiconductor layer. And the parasitic capacitance due to the reverse bias of the junction between the second semiconductor layer and the isolation region is
Since the semiconductor layer and the second semiconductor layer are insulated by the insulating film, they do not affect each other through the first semiconductor layer, and noise interference between both circuits can be completely prevented.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor integrated circuit device according to this embodiment.

Referring to FIG. 1, the semiconductor integrated circuit device of this embodiment has a P-type silicon substrate 16, an N-type epitaxial layer 18 formed on the substrate 16, a P-type silicon substrate 16 and an N-type epitaxial layer 18. Insulation film 1 for separating
7 and the N type epitaxial layer 18 are divided into a digital circuit region and an analog circuit region, respectively, and a P type diffusion belt 1
It is composed of 9 and 9.

In manufacturing such a semiconductor integrated circuit device, first, the insulating film 17 is formed on the entire surface of the P-type silicon substrate 16, and the N-type epitaxial layer 18 is formed on the insulating film 17. As a technique for forming a semiconductor crystal on such an insulating substrate (so-called SIO technique), a deposited film recrystallization method, an epitaxial deposition method, a single crystal separation method, or the like is used.

That is, first, the deposited film recrystallization method (re
crystallization of deposition
The ed film) includes a zone melting method and a solid phase epitaxy method. In the zone melting method, an amorphous or polycrystalline semiconductor thin film is deposited on an insulating substrate that is not crystalline in most cases, and the deposited film is partially removed by a method such as furnace heating or beam irradiation. It is a method of increasing the size of crystal grains in the recrystallization process or increasing the single crystal of the entire deposited film. In addition, solid phase epitaxy (so
Lid phase epitaxy is a method in which amorphous or polycrystalline Si deposited on a Si substrate crystal having a clean surface is heated at a relatively low temperature of about 550 to 600 ° C. by a method such as furnace heating or continuous laser beam irradiation. This is a method based on single crystallization by solid phase epitaxial growth.

In addition, the epitaxial deposition method (epita)
xial grow hurting deposi
is a method of growing a semiconductor crystal film on an insulating material while inheriting the crystallinity of the substrate, and is generally a method of epitaxially growing the entire surface on a sapphire or spinel crystal substrate. Furthermore, single crystal separation method (singl
E crystal isolation is a method in which an insulating material region such as an oxidized region is partially formed in a wafer-shaped Si single crystal itself and the surface or a part thereof is used as an active region.

The N type epitaxial layer 18 epitaxially grown by such a semiconductor crystal forming technique on an insulating substrate is separated into a digital circuit region and an analog circuit region by a P type diffusion belt 19. The P-type diffusion belt 19 is formed by implanting or diffusing P-type impurities having the same polarity as the P-type silicon substrate 16 in the vertical direction of the N-type epitaxial layer 18. For example, when implanting P-type impurities, the P-type impurities are implanted until they hit the insulating film 17.

The digital circuit region and the analog circuit region of the N type epitaxial layer 18 thus formed are
Mutual noise interference can be prevented by the PN reverse bias portion of the PN junction. In addition, the P-type silicon substrate 1
Since the insulating film 17 is formed over the entire surface between 6 and the N-type epitaxial layer 18, parasitic capacitance due to PN reverse bias does not occur, and there is no fear of trouble due to parasitic capacitance.

Furthermore, in the above embodiment, the first semiconductor layer and the second semiconductor layer are described as being formed with opposite conductivity types (the silicon substrate 16 is P type, and the epitaxial layer 18 is N type). In the semiconductor integrated circuit device of the present invention, since the first semiconductor layer and the second semiconductor layer are completely separated by the insulating film which is the separation region, the polarities of the substrate and the epitaxial layer may be the same.

[0020]

As described above, according to the semiconductor integrated circuit device of the present invention, the two circuits independently formed in the respective regions of the second semiconductor layer have the conductivity of the second semiconductor layer. It is completely separated by an isolation region having a polarity opposite to that of the mold, and the parasitic capacitance of the junction between the second semiconductor layer and the isolation region is insulated by an insulating film over the entire surface of the first semiconductor layer and the second semiconductor layer. Since it is configured as described above, there is an effect that noise interference between both circuits can be completely prevented.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment.

FIG. 2 is a sectional view of a conventional semiconductor integrated circuit device to which a technique for mitigating noise transmission is applied.

FIG. 3 is a cross-sectional view of a conventional semiconductor integrated circuit device to which a technique for separating a substrate in a digital circuit region and a substrate in an analog circuit region is applied.

[Explanation of symbols]

 11, 13, 16 P-type silicon substrate 12, 15, 19 Diffusion belt 14, 18 N-type epitaxial layer 17 Insulating film

Claims (2)

[Claims] 1. A first semiconductor layer having a first conductivity type, an insulating film laminated on the first semiconductor layer, and a first conductivity type laminated on the insulating film. A second semiconductor layer having a second conductivity type of opposite polarity, the second semiconductor layer having the first conductivity type, and dividing the second semiconductor layer into two regions. A semiconductor integrated circuit device, wherein a circuit is formed independently in each of the two regions. 2. A first semiconductor layer having a first conductivity type, an insulating film laminated on the first semiconductor layer, and an insulating film laminated on the insulating film and having the first conductivity type. Second
And a second semiconductor layer having a second conductivity type having a polarity opposite to that of the first conductivity type and dividing the second semiconductor layer into two regions. A semiconductor integrated circuit device including a region, wherein a circuit is formed independently in each of the two regions.