JPH0637311A - Mos transistor - Google Patents

Abstract

PURPOSE:To increase ability to drive a MOS transistor without increasing the area of a chip. CONSTITUTION:A linear channel region is arranged in the form of lattice and mesh (See a bold line in Figure). And then two regions are consituted by being divided with the channel region so as to adjacently contain it therebetween, one of which is formed to act as a source region (S) and the other of which is formed to act as a drain region (D). Thereby, the length of whole channels is increased to increase ability to drive even with a chip in same size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, and more particularly, to an improvement in the structure of a MOS transistor having a large driving capability used in a power circuit, a low resistance analog switch circuit or the like.

[0002]

2. Description of the Related Art MOS transistors include a P-channel MOS and an N-channel MOS depending on the type of carrier, and further a CMOS having a pair of these. In any case, a three-terminal element that controls the current flowing between the source region (S) and the drain region (D) by the voltage applied to the gate (G) on the channel region sandwiched between these regions or It is the combination. FIG. 4 shows a basic symbol of a MOS transistor having three terminals of a drain D, a source S and a gate G. In the basic symbol, it looks as if there is a single area corresponding to each terminal,
In the case of an actual power transistor or low resistance transistor, a large number of small transistors are connected in parallel to form one MOS transistor having a large driving capacity in appearance.

A conventional M in which a large number of drain regions and source regions of transistors to be connected in parallel are arranged in a plane.
A schematic view of an example of the OS transistor is shown in FIG. The drain regions (D) and the source regions (S) are alternately arranged in a striped pattern, and a linear channel region is provided sandwiched between these adjacent regions, each of which operates as a small transistor. However, to operate as a transistor,
Gate wiring is required on the channel region, and the gate wiring is shown in the figure. Then, each drain region (D) is connected to the drain terminal D, each source region (S) is connected to the source terminal S, and the gate wiring is connected to the gate terminal G. The parallel operation by this parallel connection results in a MOS transistor having a large driving capability.

FIG. 6 shows another structural example of a conventional MOS transistor. In this structure, a small source region (S) is arranged in an island shape in a large drain region (D), and a linear channel region is provided in the peripheral portion of this source region. The gate wiring and the connection of each region to the corresponding terminal are the same as in the above example. Again, due to this parallel connection, one MOS transistor of large drive capacity is apparently provided. By arranging the drain region and the source region in this way, providing a large number of small transistors and operating them in parallel, it is attempted to increase the driving capability beyond that obtained by simply proportionally expanding a single transistor.

[0005]

SUMMARY OF THE INVENTION Such conventional MO
In the S transistor, many small transistors are connected in parallel on the same chip. Therefore, in order to increase the power or reduce the resistance under the same manufacturing process, it is necessary to increase the number of small transistors, which inevitably increases the chip area. However, an increase in the chip area immediately leads to a decrease in the yield and the yield. This is a problem because it causes a cost increase due to a decrease in productivity.
An object of the present invention is to solve the above-mentioned problems of the prior art, and to increase the chip area without increasing the chip area.
The purpose is to increase the drive capability of the MOS transistor.

[0006]

The structure of the MOS transistor of the present invention which achieves the above object is a MOS transistor in which a plurality of source regions and drain regions are arranged in a plane without overlapping each other. And a series of or a group of regions consisting of all or a part of the drain region, each region in this region group is respectively divided by a linear channel region, each channel region is The number of the channel regions connected to the connection portion of the channel regions inside the region group is an even number,
In the two regions adjacent to each other across the channel region in the region group, one is one of the source regions and the other is one of the drain regions.

[0007]

In the MOS transistor of the present invention having such a structure, the linear channel regions are arranged in a grid or a net. As a result, the channel region is increased not only in the case of mere proportional expansion but also in the conventional stripe-shaped or island-shaped arrangement and even in the case of chips of the same size. Further, each channel region inside one region group is sandwiched by any drain region and source region. Therefore,
All of these channel regions contribute to the operation of the MOS transistor.

Therefore, the channel region, which is the deciding factor of the driving capability of the MOS transistor, increases and all of it participates in driving, so that the driving capability of the MOS transistor can be increased without increasing the chip area. Since each of the connection parts of the channel regions inside the region group is connected with an even number of channel regions, the possibility of associating regions with drains / sources corresponds to a mathematical two-color painting problem. To do. And the solution of this is known. Therefore, it is not inconvenient to use one of the two regions sandwiching the internal channel region as the source region and the other as the drain region.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the MOS transistor having the structure of the present invention will be described below. FIG. 1 is a schematic diagram for explaining a general-purpose case, and is an example of area arrangement for one area group. The entire region group is divided by straight or curved channel regions (shown by thick lines in the figure), and each drain region (D) or source region (S) has various shapes such as a triangle, a quadrangle, and a spindle shape. . At the connecting points existing inside this region group, the ends of four or six channel regions are connected. Further, based on this, the drain regions (D) and the source regions (S) are alternately arranged so as to be adjacent to each other.

Although the gate wiring is arranged above the channel region, it is omitted in the figure to avoid complexity, and only the connection G to the gate terminal is shown. Further, the connection between the drain regions (D) and the connection between the source regions (S) are omitted, and only the connection S to the source terminal and the connection D to the drain terminal are shown. With such a mesh-like arrangement, the peripheral portion of each drain or source region can contribute to the operation of the transistor without waste.

FIG. 2 shows another arrangement example. In this example, the linear channel regions are arranged in a grid. In the figure, the corresponding upper gate wiring is shown, from which the connection G to the gate terminal is made. With such a grid-like wiring, the resistance of the gate wiring is reduced and high-speed operation becomes possible. Further, the drain regions (D) and the source regions (S) are alternately arranged in a checkered pattern in the regions of each section in the lattice. Then, the drain regions are connected to each other, and the connection D to the drain terminal is further performed. Similarly, each source region is connected to each other,
Furthermore, the connection S to the source terminal is made.

Although the regions are connected in series in the figure, these regions may also be connected in a grid pattern or a mesh pattern. In that case, the wiring resistance becomes smaller, and further high-speed operation and low resistance can be achieved. With such a grid-like arrangement, the total channel length for a group of regions having the same area is, for example, the amount of the channel region corresponding to the division by the horizontal lines, as compared with the conventional striped arrangement divided by the vertical lines. Only the length is increasing. Further, as compared with the conventional island-shaped arrangement, the channel area corresponding to the outer peripheral portion of the outer area and the intermediate portion of each island also increases.

Here, the driving capability of a transistor manufactured by a semiconductor manufacturing process under the same conditions, in other words, a transistor having a channel region of the same cross-sectional structure, follows the channel length. Therefore, the MOS transistor of the present invention, which has a large total channel length for the small transistor groups operating in parallel, can exhibit a larger driving capability under a limited chip area.

In addition, the grid-like arrangement is suitable for patterning using a stepper, cutting using a dicer, etc., and is also most suitable for actual production. Further, FIG. 3 shows a specific example in which the total channel length is further increased in consideration of the diagonal line portion of the grating. In addition to the division by the horizontal lines, each region divided into two sets of diagonal lines having different directions and divided into triangles is alternately defined as a drain region or a source region. In this case, the channel length is increased by the amount corresponding to the two sets of diagonal lines.

In addition, actually, other necessary elements such as an oxide film, a protective film, a terminal portion, etc., are not directly involved in the present invention, and therefore omitted. Further, although the P-channel MOS and the N-channel MOS are not distinguished from each other in the above description,
These are relative ones that are determined by the correspondence between each region and the P-type and N-type of the semiconductor, and in any case, the mutual arrangement which is the feature of the present invention has the same operational effect.

[0016]

As can be understood from the above description, in the MOS transistor having the structure of the present invention, it is possible to secure a longer total channel length than in the past even with chips of the same size. Therefore, the drive capability of the MOS transistor can be increased without increasing the chip area. As a result, high power and low resistance can be realized while suppressing the generation of extra cost.

[Brief description of drawings]

FIG. 1 is a layout example of an embodiment of a MOS transistor having the configuration of the present invention.

FIG. 2 is a grid-like arrangement example as another embodiment of the MOS transistor having the configuration of the present invention.

FIG. 3 is a net-like arrangement example as another embodiment of the MOS transistor having the configuration of the present invention.

FIG. 4 is a basic symbol of a MOS transistor.

FIG. 5 is a striped arrangement example as an example of a conventional MOS transistor.

FIG. 6 is an island-shaped arrangement example as an example of a conventional MOS transistor.

[Explanation of symbols]

 D drain S source G gate

Claims (1)

[Claims] 1. A MOS transistor in which a plurality of source regions and drain regions are arranged in a plane without overlapping each other, wherein a series or a group of all or a part of the source region and the drain region is formed. Area group,
Each region in this region group is divided by a linear channel region, and the channel regions are connected in a lattice or net shape, and the channels connected to the connection part of the channel regions inside the region group are connected. The number of regions is an even number, and in two regions adjacent to each other with the channel region sandwiched in the region group, one is one of the source regions and the other is one of the drain regions.
OS transistor.