JPH0636599A - Two-port rom circuit - Google Patents

Abstract

PURPOSE:To simplify a test pattern and to shorten the making time of a test pattern by performing the test of a ROM circuit without using a user circuit in the periphery of the ROM circuit. CONSTITUTION:A decoder 12-2 is selected by a decoder selecting circuit 16 when a ROM circuit is tested. The decoder 12-2 decodes an address AD2 for testing, and selects a memory cell in a memory cell array. This selected memory cell is detected and amplified by a sense amplifier 13-2, and outputted to an external section. Read out data DA2 for testing outputted to the external section is compared with the expected value, and normal/defective of the ROM circuit is discriminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a user-specific user circuit for inputting an address and outputting read data, and has an input / output port for testing a ROM circuit in addition to a normal input / output port. Read-only 2-port ROM (Read
Only Memory) circuit.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram showing a configuration example of a conventional ROM circuit incorporated in a semiconductor integrated circuit such as a processor. This ROM circuit has a memory cell array 1 in which a plurality of memory cells storing data are arranged in a matrix, and in the memory cell array 1, a decoder 2 for decoding an address to select the memory cell and a selection A sense amplifier 3 that detects and amplifies the read signal from the memory cell is connected. The decoder 2 is connected to an address buffer 4 which takes in an address and supplies it to the decoder 2. The user circuit 5 is connected to the input / output sides of the address buffer 4 and the sense amplifier 3. The user circuit 5 has an address AD
Is a circuit unique to the user that controls the input and output of the read data DA, and is composed of various circuits such as a controller. When the data DA is read by this type of ROM circuit, the address AD is supplied to the address buffer 4 through the user circuit 5. The supplied address AD is fetched by the address buffer 4 and sent to the decoder 2. The decoder 2 decodes the address AD fetched by the address buffer 4 and selects a memory cell in the memory cell array 1. The stored data of the selected memory cell is detected and amplified by the sense amplifier 3, and is output through the user circuit 5 in the form of read data DA.

When performing a test for the quality of stored data,
A test pattern including test addresses is created in advance, and the test addresses are supplied to the address buffer 4 through the user circuit 5. The supplied test address is fetched by the address buffer 4 and supplied to the decoder 2. The decoder 2 selects a memory cell in the memory cell array 1 based on the fetched test address. The stored data of the selected memory cell is detected and amplified by the sense amplifier 3, and is output as test read data through the user circuit 5. This test read data is compared with the expected value by the comparing means, and the ROM
The quality of the circuit is determined.

[0004]

However, in the ROM circuit having the above structure, when a test is performed, the test address cannot be directly input to the address buffer 4, but must be input through the user circuit 5. Moreover, the read data from the memory cell array 1 can be taken out only after passing through the user circuit 5. Therefore, when creating a test pattern for testing the ROM circuit, not only the logical function of the ROM circuit,
The test pattern must be created in consideration of the logical function of the user circuit 5 around the ROM circuit, and the test pattern to be created becomes complicated and the number of steps required to create the test pattern increases. It was difficult to solve it. SUMMARY OF THE INVENTION The present invention provides a 2-port ROM circuit that solves the problems of the above-mentioned conventional technique that the test pattern of the ROM circuit is complicated and the number of steps for creating the test pattern is large.

[0005]

In order to solve the above-mentioned problems, the present invention provides a memory cell array in which memory cells respectively connected to intersections of a plurality of word lines and bit lines are arranged in a matrix, and an address. Input / output user circuit connected to the input side and read data output side, a first decoder for decoding the address from the user circuit and selecting the memory cell, and a selection by the first decoder In the ROM circuit provided with the first sense amplifier which detects and amplifies the read signal of the stored memory cell and outputs it to the user circuit, the following measures are taken. That is, according to the present invention, in the conventional ROM circuit, the second decoder for decoding the test address to select the memory cell and the read signal of the memory cell selected by the second decoder are detected and amplified. And a decoder selection circuit for selecting one of the first and second decoders according to a mode switching signal.
It constitutes an OM circuit.

[0006]

According to the present invention, as described above, the 2-port ROM is used.
Since the circuit is configured, the second decoder is selected by the decoder selection circuit when testing the ROM circuit. Then, the second decoder decodes the test address and selects the memory cell in the memory cell array. The stored data of the selected memory cell is detected and amplified by the second sense amplifier and output to the outside. The output read data for testing is compared with the expected value and R
The quality of the OM circuit is determined. As a result, the ROM circuit can be tested without passing through the user circuit around the ROM circuit. Therefore, the above problem can be solved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, which is a two-port RO incorporated in a semiconductor integrated circuit such as a processor.
It is a schematic block diagram which shows one structural example of M circuit. This 2-port ROM circuit includes a memory cell array 11 in which memory cells connected to intersections of a plurality of word lines and bit lines are arranged in a matrix. A first decoder 12-1 for decoding a normal address to select a memory cell is connected to one side of the memory cell array 11 in the word line direction, and a test decoder 12-1 for the other side of the word line direction is used for testing. A second decoder 12-2 for decoding an address and selecting the memory cell is connected. The first decoder 12-1 is the output buffer 1
It is connected to one side in the word line direction via 2a, and
The second decoder 12-2 is connected to the other in the word line direction via the output buffer 12b.

The first sense amplifier 13-1 for outputting normal read data is connected to one side of the memory cell array 11 in the bit line direction, and the test read data is connected to the other side of the bit line direction. The second sense amplifier 13-2 for outputting is connected. Address buffers 14-1 and 14-2 for fetching addresses are connected to the first and second decoders 12-1 and 12-2, respectively. The user circuit 1 for inputting the normal address AD1 and outputting the normal read data DA1 is input to the address buffer 14-1 and the first sense amplifier 13-1.
5 is connected.

The address buffer 14-2 is connected to a test terminal (not shown) for inputting the test address AD2, and the second sense amplifier 13-2.
A test terminal (not shown) for outputting the test read data DA2 is connected to. In addition, a decoder selection circuit 16 is provided in this embodiment. The decoder selection circuit 16 receives the mode switching signal MD,
This is a circuit for selecting and activating one of the output buffers 12a or 12b on the first and second decoders 12-1 and 12-2 side, and is configured by a gate circuit or the like.

Next, the normal read operation and test operation will be described. In the case of normal read operation, the mode switching signal M
D is input to the decoder selection circuit 16, and the decoder selection circuit 16 turns on the output buffer 12a on the first decoder 12-1 side and the second decoder 12
The output buffer 12b on the −2 side is turned off. When the normal read address AD1 is supplied to the address buffer 14-1 through the user circuit 15, the address buffer 14-1 takes in the address AD1 and supplies it to the first decoder 12-1. The first decoder 12-1 decodes the address AD1 fetched by the address buffer 14-1 and selects a memory cell in the memory cell array 11 via the output buffer 12a. The storage data of the selected memory cell is detected and amplified by the first sense amplifier 13-1, and is output as normal read data DA1 through the user circuit 15. When performing a test operation,
The mode switching signal MD is input, and the decoder selection circuit 16 outputs the output buffer 12b on the second decoder 12-2 side.
Is turned on and the output buffer 12a on the first decoder 12-1 side is turned off. This gives R
The input side of the OM circuit is disconnected from the peripheral user circuit 15. When a test pattern composed of test addresses is created in advance and the test address AD2 is input to the address buffer 14-2, the address AD2 is taken into the address buffer 14-2 and the second decoder 12-
Sent to 2.

The second decoder 12-2 decodes the test address AD2 fetched by the address buffer 14-2 and selects the memory cell in the memory cell array 11 via the output buffer 12b. The stored data of the selected memory cell is the second sense amplifier 13-2.
Is detected and amplified by and is output from the output terminal as test read data DA2. The read data DA2 for the test is compared with an expected value by a comparison means (not shown) or the like to determine the quality of the ROM circuit. In the present embodiment, since the second decoder 12-2 for testing, the second sense amplifier 13-2, and the decoder selection circuit 16 are provided, the second decoder 12-2 is switched by the decoder selection circuit 16 during the test. By selecting, the peripheral user circuit 15 is separated from the ROM circuit, and the user circuit 15 is disconnected.
The ROM circuit can be tested without passing through. Therefore, R
The test pattern of the OM circuit can be easily created, and the test pattern creation time can be shortened.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, in FIG. 1, the decoders 12-1 and 12-2 are output according to the output of the decoder selection circuit 16.
Although the output buffers 12a and 12b on the side are turned on and off, the operations of the decoders 12-1 and 12-2 themselves may be activated / deactivated. Further, other components such as an output buffer provided on the output side of the sense amplifiers 13-1 and 13-2 may be added.

[0013]

As described above in detail, according to the present invention, the decoder selection circuit selects the second decoder at the time of testing, and the second decoder decodes the test address to select the memory cell. However, the data stored in the memory cell can be detected and amplified by the second sense amplifier and output to the outside. Therefore, the ROM circuit can be tested without passing through the user circuit around the ROM circuit.
The test pattern for the OM circuit can be easily created, and the time for creating the test pattern can be shortened.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of a 2-port ROM circuit showing an embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of a conventional ROM circuit.

[Explanation of symbols]

 11 memory cell array 12-1, 12-2 first and second decoders 13-1, 13-2 first and second sense amplifiers 14-1, 14-2 address buffer 15 user circuit 16 decoder selection circuit

Claims (1)

[Claims] 1. A memory cell array having memory cells arranged in a matrix in which memory cells are respectively connected to intersections of a plurality of word lines and bit lines, and for input / output connected to an address input side and a read data output side. User circuit, a first decoder that decodes an address from the user circuit to select the memory cell, and a read signal of the memory cell selected by the first decoder is detected and amplified to detect the user circuit. A read-only ROM circuit including a first sense amplifier for outputting to a second decoder for decoding a test address to select the memory cell; and a memory cell selected by the second decoder. Second sense amplifier which detects and amplifies the read signal of the second sense amplifier and outputs test data, and the first or second sense amplifier according to the mode switching signal. And a decoder selection circuit for selecting one of the two decoders.