JPH06351225A - Driving method of insulated-gate thyristor - Google Patents

Abstract

PURPOSE:To expand a safely operating region in a turn-off operation by a method wherein a voltage is applied simultaneously to a first gate electrode and a second gate electrode in the turn-on operation, the applied voltage to the second gate electrode is cut off in a turn-off operation and the applied voltage to the first gate electrode is cut off so as to be delayed. CONSTITUTION:In a thyristor, gate electrodes 81, 82 are covered with an insulating film 71, a contact hole is made, an emitter electrode 10 is brought into contact with a p-base region 2 and an n<+> emitter region 4, and a collector electrode 13 is brought into contact with the whole face of a p<+> collector layer 11. In addition, the emitter electrode 10 is connected to an emitter terminal E, the collector electrode is connected to a collector terminal C, the first gate electrode 81 is connected to a first gate terminal G1 and the second gate electrode 82 is connected to a second gate terminal G2. Then, a voltage is applied simultaneously to both gate electrodes in a turn-on operation, the applied voltage to the terminal G2 is first cut off in a turn-off operation, and the terminal G1 is cut off so as to be delayed a little. As a result, a safely operating region in the turn-off operation can be expanded to two times or higher.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an insulated gate thyristor used as a voltage driven switching element used in a power supply device or the like.

[0002]

2. Description of the Related Art A semiconductor element for switching is ideally low in both steady loss and switching loss, and various semiconductor elements have been proposed for this purpose. However, in general, the steady loss and the switching loss have a trade-off relationship, and there is a problem that the switching loss increases when trying to reduce the steady loss. In order to reduce the steady loss, it is necessary to perform thyristor operation using conductivity modulation accompanied by the injection of minority carriers, but in the case of thyristor operation, it takes time until the minority carriers disappear. This increases the turn-off time, that is, the switching loss. If a lifetime killer is introduced to promote the recombination of the minority carriers and reduce the switching loss, the conductivity modulation is reduced and the on-voltage, that is, the steady loss is increased. On the other hand, there has been proposed an insulated gate thyristor in which the thyristor operation which has been conventionally driven by current is driven by voltage which extremely reduces the input loss.

FIG. 2 shows the basic structure of an insulated gate thyristor. In this insulated gate thyristor, p ⁺
The n base layer 1 is formed on the surface of the collector layer 11 via the n ⁺ buffer layer 12, and the p base region 2 is selectively selected as the surface layer of the n ⁻ base layer 1 as the surface layer of the region 2. Accordingly, the n ⁺ emitter region 3 is formed, and the n ⁺ source region 4 is further formed inside thereof. Then, in order to form a first channel in the region 5 sandwiched between the emitter region 3 of the p base region 2 and the exposed portion of the n ⁻ base layer 1, the gate terminal G is formed on the surface through the gate oxide film 7. The first gate electrode 81 connected by the wiring 91 is formed. Further, in order to form a second channel in the region 6 of the p base region 2 sandwiched between the emitter region 3 and the source region 4, a gate oxide film 7 is formed on the surface.
The second gate electrode 82 connected to the gate terminal G by the wiring 92 is formed via the. The p-base region 2 is in contact with the n ⁺ source region 5 and the emitter electrode 10 connected to the emitter terminal E by the wiring 93, and the p ⁺ collector layer 11 is connected to the collector electrode C by the wiring 94.
13 are in contact. The emitter electrode 10 is a gate electrode
It is insulated by 81 and 82 and the insulating film 71.

With a positive voltage applied to the collector electrode 13 of such an insulated gate thyristor, a positive voltage is applied to the first and second gate electrodes 81 and 82 via the G terminal as shown in FIG. Is applied, an inversion layer is formed in both the first and second channel regions 5 and 6, and first, electrons are supplied from the source region 4 to the emitter region 3 via the channel region 6,
The n ⁺ source region 4 and the n ⁺ emitter region 3 are short-circuited.
However, at the same time, since the inversion layer is generated in the channel region 5,
Electrons flow from the emitter electrode 10 through the n ⁺ source region 4 and the n ⁺ emitter region 3 to the n ⁻ base layer 1. A positive voltage is applied to the collector electrode 1, and p
Injecting holes from the ⁺ collector layer 11 causes conductivity modulation in the n ⁻ base layer 1. This hole current becomes the base current of the npn transistor composed of the n ⁻ base layer 1, the p base region 2, the shorted n ⁺ emitter region 3 and the n ⁺ source region 4. This npn transistor is an n-channel insulated gate bipolar transistor (IGB
Unlike the parasitic npn transistor T), n emitter layer made of n ⁺ emitter region 3 and the n ⁺ source region 4 has become a positively driven structure is longer in the lateral direction of the drawing, n ⁺ emitter Injection of electrons from the region 3 and the n ⁺ source region 4 is likely to occur. Like this pn
By driving the p-transistor and the npn-transistor, the p ⁺ collector layer 11, the n ⁺ buffer layer 12 and the n ^{− are formed.}
The pnpn thyristor structure composed of the base layer 1, the p base region 2, the n ⁺ emitter region 3 and the n ⁺ source region 4 can be turned on. To clear this device, first, as shown in FIG. 3, n ⁺ emitter region 3 and n by the gate voltage of the second gate electrodes 81 and 82 to 0
⁺ It can be performed by stopping the injection of electrons from the source region 4 and removing the formation of the inversion layers of the first and second channel regions 5 and 6.

[0005]

In this insulated gate thyristor, the MOSFET formed by the n ⁺ regions 3 and 4 and the second gate electrode 82 has a large on-resistance as a large current flows, and Unlike the above thyristor structure, it maintains the characteristic that the current capacity is saturated, and has a wider safe operation area than the voltage drive type thyristor, but has a drawback that the safe operation area at turn-off is narrower than the IGBT because of the thyristor structure.

An object of the present invention is to provide a method for driving an insulated gate thyristor which eliminates this drawback and can widen the safe operation area at turn-off.

[0007]

In order to achieve the above object, the present invention selects the surface layer on the other side of the base layer of the first conductivity type on which the collector layer of the second conductivity type is provided on one side. A base region of the second conductivity type is formed, and an emitter region and a source region of the first conductivity type are selectively formed on the surface layer of the base region through a space from a side close to the edge of the base region. First and second gate electrodes formed in order on the part of the base region sandwiched between the emitter region and the base layer and on the part sandwiched between the emitter region and the source region via a gate insulating film, respectively. Is provided, the emitter electrode is in common contact with the source region surface and the base region exposed surface, and the collector electrode is in contact with the collector layer surface. At the same time a voltage is applied to the gate electrode, blocks the voltage applied to the second gate electrode at the time of off, it shall be cut off the voltage applied to the first gate electrode with a delay. And, it is effective that the delay time is 1 μsec or more,
Further, it is effective that the first conductivity type is n-type and the second conductivity type is p-type.

[0008]

Operation: The collector layer is p-type, that is, the first conductivity type is n-type.
Type, the second conductivity type is p-type
In the ON state, holes are injected from the collector layer into the n ⁻ base layer, but when the voltage applied to the second gate electrode is cut off first, the injection of electrons from the n ⁺ source region is stopped and The amount of electric current is reduced, and further, the Coulomb force of electrons against the hole current is reduced. After that, all the current is cut off in order to cut off the applied voltage to the first gate electrode and turn it off, but compared with the case where the applied voltages to the first and second gate electrodes are turned off at the same time, the hole current, The safe operating area is expanded because the device turns off when the amount of electron current is reduced.
In other words, by blocking the voltage applied to the second gate electrode, the function of the source region is lost, and the insulated gate thyristor has an IGBT structure in which the emitter region is the source. To turn off this IGBT, n ⁺
Since the resistance of the portion just below the emitter region is smaller than the resistance of the portion just below the n ⁺ source region,
The voltage drop caused by the hole current flowing through this portion is small, and the parasitic thyristor of the IGBT does not operate even by the hole current flowing by dv / dt at the time of turn-off, so that the safe operation area is widened.

[0009]

FIG. 1 shows an insulated gate thyristor according to an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. The sectional structure of this insulated gate thyristor is the same as that of the conventional one shown in FIG. 2 and is manufactured as follows. That is, the n ⁺ buffer layer 12 is formed on one surface of the n ⁻ silicon substrate 1.
And the p ⁺ collector layer 11 and the p base region 2 are selectively formed on the surface layer on the other surface side, and a polycrystalline silicon layer is further deposited on the other surface via the gate oxide film 7 and patterned. As a result, the first gate electrode 81 and the second gate electrode 82 are formed. Then, the n ⁺ emitter region 3 is formed by ion implantation using the first and second gate electrodes 81 and 82 as a mask,
The n ⁺ source region 4 is formed by ion implantation using the second gate electrode 82 as a part of the mask. After that, the gate electrodes 81 and 82 are covered with an insulating film 71, contact holes are opened, and the emitter electrode 10 is formed into the p base region 2 and the n ⁺ emitter region 4.
Contact. The collector electrode 13 is brought into contact with the entire surface of the p ⁺ collector layer 11. The emitter electrode 10 is connected to the emitter terminal E, and the collector electrode is connected to the collector terminal C. In the case of FIG. 2, the first and second gate electrodes 81 and 82 are all connected to the gate terminal G, but in this embodiment, the first gate electrode 81
Is connected to the first gate terminal G1 by the wiring 91 and the second gate electrode
82 is connected to the second gate terminal G2 by the wiring 92.

FIG. 4 shows a method of driving this insulated gate thyristor. As shown in the figure, when turning on, G1, G2
Positive voltage is simultaneously applied to the first and second gate electrodes via the terminals, but when turned off, the applied voltage via the G2 terminal is cut off first, and then delayed by at least 1 μsec and then via the G1 terminal. Shut off the applied voltage. By doing so, the safe operating area at turn-off was more than doubled.

[0011]

According to the present invention, the thyristor operation is temporarily stopped by providing a time difference between the turn-off interruptions of the voltages applied to the first and second gate electrodes of the insulated gate thyristor.
By turning off after turning to T operation, the safe operation area at turn off could be expanded more than twice.

[Brief description of drawings]

FIG. 1 is a sectional view of an insulated gate thyristor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional insulated gate thyristor.

3 is a waveform diagram of a gate voltage applied to the device of FIG.

4 is a waveform diagram of a gate voltage applied to the device of FIG.

[Explanation of symbols]

1 n ^- base layer 2 p base region 3 n ⁺ emitter region 4 n ⁺ source region 7 gate oxide film 81 first gate electrode 82 second gate electrode 10 emitter electrode 11 p ⁺ collector layer 12 n ⁺ buffer layer 13 collector electrode

Claims (3)

[Claims] 1. A base region of the second conductivity type is selectively formed on a surface layer on the other side of the base layer of the first conductivity type having a collector layer of the second conductivity type on one side, and a base region of the base region is formed. An emitter region and a source region, both of which are of the first conductivity type, are selectively formed on the surface layer in order from the side close to the edge of the base region with a gap, and the emitter region of the base region and the exposed surface portion of the base layer are formed. First and second gate electrodes are provided respectively on the sandwiched portion and the portion sandwiched between the emitter region and the source region via a gate insulating film, and the emitter electrode serves as the source region surface and the base region. In a method of driving an insulated gate thyristor in which the collector electrode is in common contact with the exposed surface and the collector electrode is in contact with the collector layer surface,
A voltage is simultaneously applied to the first and second gate electrodes when turned on, and a voltage applied to the second gate electrode is cut off when turned off,
A method for driving an insulated gate thyristor, characterized in that the voltage applied to the first gate electrode is cut off with a delay. 2. The method for driving an insulated gate thyristor according to claim 1, wherein the delay time is 1 μsec or more. 3. The method for driving an insulated gate thyristor according to claim 1, wherein the first conductivity type is n type and the second conductivity type is p type.