JPH06334196A - Mos type semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a MOS type semiconductor memory device capable of reducing the size of a memory cell, and what is more, source resistance. CONSTITUTION:This invention relates to a MOS type semiconductor device which is provided with a semiconductor substrate 1 and a source region 3 and a drain region 2 formed on the semiconductor substrate 1 and a MOS transistor having gate means 6 and 7 formed in the region on the substrate between the source region and the drain region and insulated from the substrate and a source conducting film 11 which comes in direct contact with the source region, and what is more, insulated from the gate means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor memory device, and more particularly to a nonvolatile MOS type semiconductor memory device represented by EPROM and flash EEPROM.

[0002]

2. Description of the Related Art In a conventional MOS semiconductor memory device, for example, a nonvolatile semiconductor memory device typified by EPROM and flash EEPROM has a structure mainly shown in FIGS. Various measures have been taken to reduce the size of each memory cell for high-density integration. The main factors limiting the size reduction of the memory cell of the EPROM are the gate length of the memory cell and the drain diffusion layer 2 as shown in FIG.
2 is the contact margin required to prevent contact between the contact and the floating gate 26 when forming the contact 32 between 2 and the bit line, and the source width of the source diffusion layer 23. Of these, the gate length is 1.0
If it is smaller than μm, punch-through occurs between the source diffusion layer 23 and the drain diffusion layer 22 provided on the semiconductor substrate 31, so that it becomes difficult to shorten the gate length and hence the channel length.

Therefore, various proposals have recently been made to solve the problems related to the other two factors. First, as shown in FIG. 10, the drain diffusion layer 22
In order to prevent contact between the floating gate 26 and the drain contact 32 that connects the drain contact with the bit line, it is proposed to provide a silicide pad 35 as a conductive film to minimize the design margin when forming the drain contact. ing. As a result, at least as long as the drain contact is formed in the area of the silicide pad 35,
No short circuit will occur between the floating gate and the bit line. According to this proposal, a margin for matching between the drain contact and the silicide film may be taken into consideration as a design margin for preventing contact between the drain contact and the floating gate. It is possible to reduce the distance.

On the other hand, with respect to the reduction of the source width, it is necessary to prevent the source resistance from increasing due to the reduction of the source width. Therefore, as shown in FIG. 11, a silicide layer 35a is provided in parallel on the source diffusion layer 23, and a strap region is provided for every several bits as shown in FIG. 12, so that the source region 23 and the silicide layer 35a are formed. It has been proposed to provide a contact 39 for connecting the. In addition,
In FIGS. 11 and 12, 30 is an interlayer insulating film, and 34, 3
Reference numerals 7 and 38 denote gate interlayer insulating films, and FIG. 11 is a sectional view taken along line XI-XI of FIG.

However, there is a limit to the size reduction of the memory cell by the conventional structure as described above, and it is difficult to achieve a satisfactory size reduction. For example, the design margin x shown in FIG. 10 for preventing contact between the drain contact connecting the silicide pad 35 and the drain diffusion layer 22 and the floating gate 26 or the control gate 27 is at least during exposure in lithography. Alignment margin (alignm
It is necessary to consider ent tolerance).

Further, the silicide layer 35a is provided in order to prevent an increase in the source resistance, and an extra strap region for providing the contact 39 for connecting the source region and the silicide layer needs to be additionally provided, which reduces the size of the memory cell. There is a problem of hindering.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOS type semiconductor memory device capable of reducing the memory cell and reducing the source resistance.

[0008]

In order to achieve the above object, a MOS type semiconductor memory device according to the present invention comprises a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, and a source. A MOS transistor having gate means formed on the region of the substrate between the region and the drain region so as to be insulated from the substrate;
It further comprises a source conductive film formed in direct contact with the source region and insulated from the gate means.

In order to achieve the above object, a MOS type semiconductor memory device according to a second aspect of the present invention comprises a semiconductor substrate,
A MOS transistor having a source region and a drain region formed on the semiconductor substrate, and a gate means formed on the region of the substrate between the source region and the drain region and insulated from the substrate; A sidewall insulating film formed so as to cover the sidewall of the gate means, a drain conductive film which directly contacts the drain region and extends on the sidewall insulating film, and a direct contact with the source region, And a source conductive film extending over the sidewall insulating film.

In order to achieve the above object, a MOS type semiconductor memory device according to a third aspect of the invention comprises a semiconductor substrate,
A MOS transistor having a source region and a drain region formed on the semiconductor substrate, and a gate means formed on the region of the substrate between the source region and the drain region and insulated from the substrate; It is characterized by comprising a sidewall insulating film formed so as to cover the sidewall of the gate means and a source conductive film which is in direct contact with the source region and extends to one side of the sidewall insulating film. .

[0011]

The MOS type semiconductor memory device according to the present invention is an MO
Since the source conductive film that is in direct contact with the source region of the S transistor is provided, a strap region is additionally provided to provide a contact for connecting the source region and the silicide layer as in the conventional MOS semiconductor memory device. Without reducing the resistance of the source region, and thus
The size of the memory cell can be reduced.

Further, since the drain conductive film is in direct contact with the drain region and extends over the side wall insulating film of the gate means, the drain conductive film is connected to the drain contact in the formation of the drain contact connecting the drain region and the bit line. The margin for preventing contact with the gate means can be reduced, and the size of the memory cell can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An EPROM according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view thereof. The EPROM of FIG. 1 has a source diffusion region 3 and a drain diffusion region 2 formed on a semiconductor substrate 1 and a laminated structure on the semiconductor substrate 1, and includes a first insulating film 4 and a second insulating film 5.
The floating gate 6 and the control gate 7 are insulated from each other. Sidewall insulating films 9 are formed on the sidewalls of the floating gate 6, the control gate 7, the first insulating film 4 and the second insulating film 5.

The source diffusion layer 3, the side wall insulating films 9 and 9 formed to face each other, and the drain diffusion layer 2 to the side wall insulating films 9 and 9 formed to face each other, the conductive film 1 is formed, respectively.
1 is directly coated.

The source diffusion layer 3 extends in the direction perpendicular to the paper surface,
The conductive film 11 formed on the source diffusion layer 3 also extends parallel to the source diffusion layer 3 in the direction perpendicular to the paper surface. Normal EPRO
M has memory cells arranged in a matrix of rows and columns,
The source diffusion regions of a plurality of memory cells in the direction perpendicular to the plane of the drawing, for example in the row direction, are connected to the conductive layer 11 extending in the row direction.

In FIG. 1, 8 is a cap insulating film,
10 is an interlayer insulating film, 13 is a bit line (aluminum wiring)
Is.

Next, a manufacturing process of the above-mentioned semiconductor memory device will be described with reference to FIGS. First, the first insulating film 4, the floating gate 6, the second insulating film 5, the control gate 7, and the cap insulating film 8 are sequentially formed on the P-conductivity type semiconductor substrate 1 in a self-aligned manner to form the cell gate electrode 20. After patterning, an N-conductivity-type impurity is added to the cell gate electrode 20 so as to be self-aligned, for example, 50 to 70 ke
As shown in FIG. 2, the drain diffusion layer 2 and the source diffusion layer 3 are respectively ion-implanted at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² at V and heat-treated at a temperature of 800 to 900 ° C. Form.

Next, 300 to 500 nm is formed by the CVD method.
After forming a film of the same material as that of the cap insulating film 8 with the film thickness of 3, the side wall insulating film 9 is formed on both side wall portions of the cell gate electrode 20 by etching back by the RIE method.

Next, a conductive material made of W silicide, Ti silicide, or polysilicon containing a large amount of the same impurities as the source is deposited by a sputtering method and patterned to diffuse the source, as shown in FIG. Conductive film 11 covering the layer 3 and both side wall insulating films 9
Then, a conductive film 11 that covers the drain diffusion layer 2 and the side wall insulating film 9 is formed. That is, the conductive film 11 is formed directly on the source diffusion layer 3 and the insulating films 9 on both side walls thereof, and on the drain diffusion layer 2 and the insulating film 9 on both side walls thereof. Therefore, it is not necessary to provide a conventional alignment margin as shown by x in FIG.

Further, as shown in FIG. 5, a photoresist film 10 is formed so as to open only above the contact portion between the drain diffusion layer 2 and the conductive film 11, and the drain region 2 and the drain region 2 are electrically conductive using the photoresist film 10 as a mask. 50 to 70 k of N-conductivity type impurities is applied to the portion of the drain region 2 at the contact portion with the film 11.
Ion implantation is performed under the conditions of eV and a dose amount of 1 to 3 × 10 ¹⁵ cm ^-2 . This is to reduce the contact resistance between the drain region 2 and the conductive film 11. Incidentally, the photoresist film 1
0 is left as the interlayer insulating film 10.

Next, as shown in FIG. 6, the drain diffusion layer 2
After forming a plug 12 made of a polycrystalline silicon layer doped with conductive impurities on the upper conductive film 11, a bit line 13 is patterned.

Through the above steps, the non-volatile semiconductor memory device shown in FIG. 1 can be manufactured.

Next, another embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. 7 to 9 are sectional views of an E ² PROM which is a nonvolatile semiconductor memory device according to the second embodiment of the present invention. First, as shown in FIG. 7, the cell gate electrode 20 is formed on the P-type semiconductor substrate 1 similarly to the case shown in FIG.
After the formation, the photoresist film 14 masks other regions except the portion where the source diffusion layer 3a is formed.

Next, N conductivity type impurities are added to the accelerating voltage 40 to 7
Ion implantation is performed under conditions of 0 keV and a dose amount of 1 to 5 × 10 ¹⁴ cm ⁻² , and heat treatment is performed at a temperature of 200 to 900 ° C. to form the low concentration source diffusion layer 3a.

Further, as shown in FIG. 8, this time, the region other than the portion where the drain diffusion layer 2a is formed is masked with the photoresist film 14, and the N-conductivity type impurity is accelerated by the accelerating voltage 5.
Ion implantation is performed under conditions of 0 to 70 keV and a dose amount of 3 to 5 × 10 ¹⁵ cm ⁻² to form a low concentration drain diffusion layer 2 a
To form.

Thereafter, in the same manner as described above, after forming the sidewall insulating film 9 and again masking with the photoresist film 14a so as to open only the source diffusion layer 3a portion, the N conductive type impurity is removed. Is ion-implanted under the conditions of 30 to 50 keV and a dose amount of 3 to 5 × 10 ¹⁵ cm ⁻² to form a high concentration source diffusion layer 3b. Thereby, the high concentration source diffusion layer 3b and the low concentration drain diffusion layer 2a in the flash E ² PROM can be formed. After this,
A flash E ² PROM can be manufactured by performing the same steps as in the case of the EPROM described above.

The present invention is not limited to the above-described embodiments, but various modifications can be made within the scope of the gist thereof.

[0028]

As described above, according to the present invention, since the source conductive film which is in direct contact with the source region of the MOS transistor is provided, the strap region is additionally provided as in the conventional MOS semiconductor memory device. Without providing a contact connecting the source region and the silicide layer,
It is possible to provide a nonvolatile semiconductor memory device capable of reducing the resistance of the source region and thus realizing a reduced memory cell.

According to the present invention described above, since the drain conductive film is in direct contact with the drain region and extends over the side wall insulating film of the gate means, the drain contact for connecting the drain region and the bit line is formed. In the formation of
It is possible to provide a non-volatile semiconductor memory device that can reduce the margin for preventing contact between the drain contact and the gate means, and can realize a reduced memory cell.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of an EPROM according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the structure in each step of manufacturing the EPROM of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a structure in each step of manufacturing the EPROM of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the structure in each step of manufacturing the EPROM of the first embodiment of the present invention.

FIG. 5 is a sectional view showing a structure in each step of manufacturing the EPROM of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the structure in each step of manufacturing the EPROM of the first embodiment of the present invention.

FIG. 7 is a sectional view showing a structure of an EPROM according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the structure in each step of manufacturing the EPROM of the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the structure in each step of manufacturing the EPROM of the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the structure of an example of a conventional EPROM.

FIG. 11 is a cross-sectional view showing the structure of another example of the conventional EPROM.

FIG. 12 is a diagram showing a planar arrangement of the EPROM of FIG.

[Explanation of symbols]

 1, 31 Semiconductor substrate 2, 22 Drain diffusion layer 3, 23 Source diffusion layer 4 First insulating film 5 Second insulating film 6, 26 Floating gate 7, 27 Control gate 8 Cap insulating film 9 Side wall insulating film 10, 30 Interlayer insulation Film 11 Conductive film 13 Bit line (aluminum wiring) 20 Cell gate electrode 32 Drain contact 34, 37, 38 Gate interlayer insulating film 35 Silicide pad 39 Contact

Claims (3)

[Claims] 1. A gate means formed on a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, and a region of the substrate between the source region and the drain region and insulated from the substrate. And a source conductive film formed in direct contact with the source region and insulated from the gate means, the MOS type semiconductor memory device. 2. A gate means formed on a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, and a region of the substrate between the source region and the drain region and insulated from the substrate. A MOS transistor having: a sidewall insulating film formed to cover the sidewall of the gate means; a drain conductive film that directly contacts the drain region and extends on the sidewall insulating film; and a drain conductive film that directly extends to the source region. And a source conductive film which is in contact with and extends over the side wall insulating film of the gate means. 3. A gate means formed on a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, and a region of the substrate between the source region and the drain region, the gate means being insulated from the substrate. A side wall insulating film formed to cover the side wall of the gate means, and a source conductive film that is in direct contact with the source region and extends to one side of the side wall insulating film. A MOS semiconductor memory device characterized by the above.