JPH06326262A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To suppress the subthreshold coefficient and the leak current of a semiconductor device operating at a low voltage. CONSTITUTION:The semiconductor device is constituted of a CMOS transistor comprising a pair of a P-channel MOS transistor having a polysilicon gate 2 and an N-channel MOS transistor having a polysilicon gate. The MOS transistor has a channel doped layer 4 localized in the vicinity of the surface immediately below a gate electrode 2. The channel doped layer also has a very shallow p-n junction depth xj and can suppress the leak current. Consequently, the impurity concentration is decreased at the surface of the substrate below the gate electrode 2 and thereby the subthreshold characteristics are improved to realize high speed operation. Furthermore, low voltage operation is realized because the leak current can be suppressed at low threshold voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. More specifically, the present invention relates to a semiconductor device including a CMOS transistor formed of a pair of a P-channel MOS transistor having a polysilicon gate and an N-channel MOS transistor having a polysilicon gate, and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device capable of high-speed operation at a low voltage of about 1.5 V and a manufacturing method thereof.

[0002]

2. Description of the Related Art Usually, a silicon substrate or a silicon substrate having a well layer formed by ion implantation is used as a gate electrode in which a large amount of phosphorus is added to an N-type polysilicon gate or a large amount of boron is added to a P-type polysilicon. A gate is formed. A gate electrode material of the same type as the channel type of the MOS transistor, for example, an N channel MO
When N-type polysilicon is used for the gate electrode of the S transistor, the work function difference between the substrate and the polysilicon is large, so that the threshold voltage becomes low. Therefore, the same conductivity type impurity as the substrate, for example, boron is usually ion-implanted into the channel region to adjust the threshold voltage.

On the other hand, when a gate electrode material of a type different from the channel type of the MOS transistor, for example, N-type polysilicon is used for the gate electrode in a P-channel MOS transistor, the work function difference between the substrate and the polysilicon becomes small. , The threshold voltage increases in the negative direction.
Therefore, a conductivity type impurity opposite to that of the substrate, for example, boron is usually ion-implanted into the channel region to adjust the absolute value of the threshold voltage. As a result, a pn junction is formed in the channel region. The former is called a surface channel type device and the latter is called a buried channel type device.

The P-channel MOS transistor and the N-channel MOS transistor are combined with each other to form a complementary transistor, so-called CMOS transistor. The CMOS transistor is a basic constituent element of a semiconductor device integrated circuit. As the boron ion implantation amount into the channel region is increased, the threshold voltage of the N channel MOS transistor of the surface channel type device is increased, and the P channel MO of the buried channel type device is increased.
The threshold voltage of the S-transistor decreases.

[0005]

A semiconductor device integrated circuit having a CMOS transistor as a basic constituent element, that is, a CM.
The OSIC is suitable for a one-chip microcomputer, for example. Such a one-chip microcomputer is incorporated in various portable devices and tabletop devices for control. These portable devices and tabletop devices usually use batteries as a power source. From the viewpoint of downsizing of devices and power saving, for example, devices requiring an operation with a power supply voltage (about 1.5 V) of one dry battery are increasing. Therefore, CM
Low voltage operation of OSICs is listed as an important development item.

In order to lower the operating voltage of the CMOS IC, M
It is necessary to keep the threshold voltage of the OS transistor low.
However, when the threshold voltage of the CMOS transistor described above is reduced to about 0.5 V, which is necessary for 1.5 V operation, there is a problem or a problem that the leak current of the MOS transistor increases. If the leak current increases, there is a problem in that the battery is exhausted rapidly even if a portable device using the battery is not operated, and the battery runs out quickly.

In order to facilitate the understanding of the background of the present invention, this problem will be briefly described below. In the MOS transistor, the channel is inverted by applying a constant voltage to the drain and applying a voltage equal to or higher than the threshold voltage to the gate electrode, and a current flows between the source and the drain to operate. However, when the threshold voltage becomes low, the channel weakly inverts without applying the gate voltage, and the battery flows between the source and the drain (leakage current).

In order to make this easier to understand, description will be made with reference to FIG. In the graph, the horizontal axis represents the gate voltage V _G and the vertical axis represents the drain current I _D in a logarithmic memory, and the data measured at the drain voltage V _D = 0.1 V is shown. According to this, when the gate voltage V _G = 0V, the drain current I _D ≠ 0
It is A. That is, the current has flown without operating the MOS transistor. Here, the reciprocal of the slope of this characteristic, V _G / 1 og (I _D ), is called a subthreshold coefficient S and is an important value that determines the switching performance of the MOS transistor.

There is a depletion layer capacitance on the surface of the substrate immediately below the gate electrode of the MOS transistor, and when the depletion layer capacitance is large, the subthreshold coefficient S becomes large, and conversely, when it is small, the subthreshold coefficient S becomes small. .
The depletion layer capacitance increases when the concentration of the substrate surface immediately below the gate electrode is high, and conversely decreases when it is thin. Therefore, the thinner the concentration of the substrate surface immediately below the gate electrode, the smaller the depletion layer capacitance, the smaller the subthreshold coefficient S, and the smaller the voltage range required to operate the MOS transistor. High speed and low power consumption switching operations are possible. Particularly in the case of a P-channel MOS transistor which is an embedded device, when the threshold voltage is suppressed to about 0.5 V, a relatively large amount of boron is ion-implanted, so that the substrate surface concentration is high.

Further, as described above, in the P-channel MOS transistor which is an embedded device using N-type polysilicon as the gate electrode, p-type is formed in the channel region of the n-well.
An n-junction is formed. Therefore, in the P-channel MOS transistor, the position where the potential is minimum exists not inside the interface between the silicon substrate and the gate oxide film but inside the substrate, and a buried channel is formed. The position where the potential is minimized moves to the substrate side as the pn junction depth of the channel region becomes deeper, and the degree of the buried channel increases. As a result, the carriers in the buried channel are less likely to be affected by the surface scattering peculiar to the interface, so that the mobility is increased.
To reduce the threshold voltage, increase the boron implantation amount and p-
The mobility increases as the n-junction depth is increased and the buried channel degree is strengthened.

As described above, the buried channel type device has an advantage of higher mobility than the surface channel type device. However, the biggest problem with this device is that short channel effects are likely to occur. Increases in leakage current, deterioration in subthreshold characteristics, and reduction in punch-through breakdown voltage, which accompany the shortening of the channel, pose particular problems. In order to reduce such a short channel effect in the buried channel type P channel MOS transistor, it is necessary to make the pn junction depth of the channel region as shallow as possible to approach the surface channel type device. However, in reality, it was difficult to achieve an extremely shallow pn junction depth. Conventionally, boron has been ion-implanted to perform channel doping. Since boron has a large diffusion coefficient, it is difficult to form a shallow diffusion layer. In particular, when the threshold voltage is suppressed to about 0.5 V, a relatively large amount of boron is ion-implanted, so that the pn junction depth cannot be made shallow.

In order to suppress the short channel effect of the P channel MOS transistor described above, an N channel MO transistor is used.
Similar to the S transistor, it has been attempted to have a surface channel type structure. That is, unlike the N-type unipolar gate structure,
This is an N-type / P-type bipolar gate structure. In this case, the P-type polysilicon gate electrode material is used for the gate electrode of the P-channel MOS transistor. However, the N-type / P-type bipolar gate structure has a problem that not only the process becomes complicated but also the IC design becomes complicated. In particular, in order to obtain ohmic contact with the gate electrodes of opposite polarities, there is a problem that the structure of the wiring connection portion becomes complicated and the IC chip size increases. On the other hand, the N-type unipolar gate structure is advantageous in that the process and design are simple and the chip size can be kept small.

[0013]

In view of the above-mentioned problems and problems of the conventional technique, the present invention provides a CMOS transistor with high speed operation or low voltage operation while reducing the subthreshold coefficient or suppressing leakage current. The purpose is to In order to achieve this object, the following manufacturing means were taken. That is, in a method of manufacturing a semiconductor device including a CMOS transistor including a pair of a P-channel MOS transistor having a polysilicon gate and an N-channel MOS transistor having a polysilicon gate, BF ₂ ⁺ is ion-implanted to locally near the surface. Means were taken to perform a channel doping step to form a localized channel dope layer. At this time, a measure was taken such that the acceleration energy of the ion implantation is 30 KeV or less. Preferably, the means for forming the gate insulating film of the MOS transistor is taken prior to the channel doping step.

After the channel doping step, the other N
Means were taken to form source / drain regions of the N-channel MOS transistor without implanting phosphorus into the p-type region of the channel MOS transistor and subjecting the N ⁺ source / drain to drive-in heat treatment. More preferably, phosphorus is added to the p ^- type semiconductor substrate in a range of about 1 to 1,
Means were taken to form the n-type region of the P-channel MOS transistor as an n-type well by ion implantation with a dose of 3 × 10 ^{12 and} more preferably 2 × 10 ¹² / cm ² . In addition, the gate insulating film of the MOS transistor is formed to have a film thickness of about 100 to 200Å and an optimized film thickness of 150Å.

[0015]

According to the semiconductor manufacturing method of the present invention, a p-type channel dope layer localized near the surface is formed by ion-implanting BF ₂ ⁺ instead of the conventionally used boron alone. It is possible. BF ₂ ⁺ has a larger molecular weight than boron alone and has a smaller range at the time of ion implantation. Also, the acceleration energy is set to 30 KeV or less. Therefore, the p-type impurity layer can be formed extremely shallow, and the variation of the impurity distribution in the depth direction can be made small, so that the substrate surface concentration immediately below the gate electrode can be made thin.

Further, in the present invention, the gate insulating film of the MOS transistor is formed by thermal oxidation treatment prior to the channel doping step of forming the channel doped layer. Since the p-type channel dope layer formed later is not subjected to thermal oxidation history, thermal diffusion of impurities is suppressed and an extremely shallow pn junction depth can be maintained as it is. In addition, since the substrate surface concentration necessary for adjusting the threshold voltage becomes thinner than the impurity thermal diffusion, it is not necessary to take measures to increase the channel doping amount in advance. Increasing the channel doping amount means increasing the substrate surface concentration. For the same reason, after the channel doping step, phosphorus is ion-implanted in place of the arsenic conventionally used when forming the source / drain regions in the p-type region of the other N-channel MOS transistor. Phosphorus has a larger diffusion coefficient than arsenic, and a sufficient impurity region can be obtained without heat treatment or annealing.

Therefore, it is not necessary to add a thermal history which adversely affects the previously formed channel dope layer. Further, when forming an n-type region of a P-channel MOS transistor, that is, an n-type well, on a p ^- type semiconductor substrate, the dose amount of phosphorus is halved compared to the conventional case. Even if the channel doping amount is smaller than this, the same threshold voltage as the conventional one can be obtained. Therefore, the substrate surface concentration just below the gate electrode becomes thin, and the P-channel MOS transistor subthreshold coefficient can be reduced. It is also possible to suppress an increase in leak current due to the lower threshold voltage. in addition,
In the present invention, the gate insulating film of the MOS transistor is about 15
The film thickness is reduced to 0Å. This makes it possible to miniaturize the device according to the 0.8 μ rule, and at the same time, achieve high-speed operation and low voltage.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings.
The details will be described. FIG. 1 shows a CMOS transistor according to the present invention.
It is a typical fragmentary sectional view showing the structure of a transistor. This
The transistor is a semiconductor substrate p^-Type Si substrate 1 is used
Is formed. An n well 2 is formed on this substrate 1.
Has been. This n-well 2 is optimized for low concentration
For example, phosphorus which is an n-type impurity is ion-implanted to 2 × 1.
0 ¹²/ Cm²It is formed by doping with a dose of. surface
A gate oxide film (Gate Ox) 3 is formed on the
It This gate oxide film 3 is thin and optimized.
It has a film thickness of 150Å. A pattern is formed on the gate oxide film 3.
N-type polysilicon gate electrode (N-type pol)
y Si Gate) 4 is formed. Gate electrode
Immediately below 4 is a channel dope layer through a gate oxide film 3.
5 is formed. This channel dope layer 5 is very
It has a shallow pn junction depth (xj) and is, for example, 0.1.
It is about 5 μm. P channel MOS transistor is n
N-channel MOS transistor p formed in well 2
^-Type Si substrate 1, both of which are field oxide films 6
Are separated by. High concentration on both sides of the channel dope layer 5
P-type / N-type source region S doped with impurities
And a P-type / N-type drain region D is formed
It

For comparison with the structure of the present invention shown in FIG.
The conventional structure corresponding to FIG. 2 is shown. Similar to the structure shown in FIG. 1, the P-channel MOS transistor is formed on the p ⁻ type Si substrate 101. An n-well 102 is provided on the substrate 101. The n-well 102 contains a higher concentration of n-type impurities than the n-well 2 shown in FIG. For example, the impurity phosphorus is 4 × 10 ¹² by ion implantation.
Doping is performed with a dose amount of about / cm ² . The gate oxide film 103 is thicker than the gate oxide film 3 shown in FIG. 1 and is, for example, about 250 Å. The N-type polysilicon gate electrode 104 formed thereon has the same structure as the gate electrode 4 shown in FIG. The P-channel MOS transistor and the N-channel MOS transistor are separated by the field oxide film 106. Finally, the gate electrode 104
The channel dope layer 105 formed immediately below the layer has a relatively deep pn junction depth xj and is, for example, 0.34 μm.
It is a degree.

Next, the features of the present invention will be described in detail by comparing the structure of the present invention shown in FIG. 1 with the conventional MOS structure shown in FIG. FIG. 3 is a graph showing the profile of the impurity boron concentration in the n-well in the depth direction. Here, the ion channel acceleration energies are the same. The vertical axis of the graph represents the depth, and the horizontal axis represents the impurity concentration. In the case of the present invention, the concentration profile curves 31 and 32 sharply fall near the surface of the n-well, and the p-type channel dope layer is localized near the surface. Therefore, the pn junction depth xj1 is extremely shallow. On the other hand, in the conventional case, the profile curves 33 and 34 fall gently, and the p-type channel dope layer has a large spread (variation) in the n-well. Therefore, the pn junction depth xj2 is located relatively deep. As a result, the invention product has a lower total impurity concentration.

FIG. 4 shows a P-channel MOS transistor (P
It is a graph which shows the relationship between the leak current of ch Tr) and pn junction depth xj. The ordinate represents the leak current (A) in logarithmic memory, and the abscissa represents the junction depth xj in μm unit. As described above, the bonding depth xj1 of the invention product shown in FIG. 1 is about 0.15 μm, and the bonding depth xj2 of the conventional product shown in FIG. 2 is about 0.34 μm. As is clear from the graph, the leakage current of the conventional product 42 is 10 ^-8 A
However, the leakage current of the invention product 41 is 10
^It has decreased to about ^-10A . In obtaining this data, the threshold voltage V _TP of the P-channel MOS transistor is set to 0.4V. As is clear from the measurement results, by reducing the pn junction depth xj, the short channel effect and the like can be suppressed and the leak current can be greatly reduced. In order to suppress the leak current by about one order as compared with the related art, it is preferable to control the junction depth xj to 0.2 μm or less.

The second characteristic feature of the present invention is that the gate oxide film is thin and optimized as compared with the conventional one. The gate oxide film thickness of about 250 Å was reduced to about 150 Å. The 150 Å gate oxide film thickness corresponds to the 0.8μ rule, which can facilitate device miniaturization. By thinning the gate oxide film, the operating characteristics of the transistor are improved. Since the channel conductance gm is improved, the current capacity is increased.

FIG. 5 is a graph showing capacitance characteristics in a p ^- type Si substrate doped with p-type impurities (channel doping) in a MOS structure. Here, the implantation conditions were acceleration energy of 25 KeV. The vertical axis of the graph is the capacity (C / C
_OX ) and the horizontal axis represents voltage (BIAS). In this graph, the negative BIAS region indicates the oxide film capacitance, and the positive region indicates the substrate capacitance. As is apparent from the graph, the substrate capacitance of the invention product 43 is smaller than that of the conventional product 44. This is because the depletion layer extends further on the substrate surface. The width of the depletion layer grows better as the impurity concentration decreases. In other words, the impurity concentration of the surface substrate is lower in the invention product.

FIG. 6 shows the relationship between the threshold voltage V _TH of the MOS transistor and the subthreshold coefficient S. The vertical axis of the graph indicates the subthreshold coefficient S (mV / dec)
ade), and the threshold voltage V is plotted on the horizontal axis.
_TH (V) is taken. As described above, the invention product shown in FIG. 1 has a low total impurity concentration directly below the gate electrode at a shallow depth of about 0.15 μm, and the conventional product shown in FIG. 2 has a total impurity concentration immediately below the gate electrode at a depth of about 0.34 μm. Is dark. In addition, since the n-well is thinner in the invention product than in the conventional product, the channel doping amount of the P-channel MOS transistor for adjusting the threshold voltage can be small, so that the total impurity concentration immediately below the gate electrode is reduced. Is thinning. Further, the gate oxide film has been thinned from about 250 Å to about 150 Å. As is clear from the graph, the subthreshold coefficient S of the conventional product 62 is P
When the threshold voltage V _TH of the channel MOS transistor is, for example, 0.5 V, it is 97.2 mV / decade, whereas the subthreshold coefficient S of the invention product 61 is reduced to 77.2 mV / decade. Further, the threshold value V _TH of the N-channel MOS transistor is, for example,
Even when the voltage is 0.5 V, the subthreshold coefficient of the conventional product is 84.7 mV / decade, whereas that of the invention product is reduced to 78.2 mV / decade. In this graph, when the threshold voltage V _TH becomes low, the P channel MO
It can be seen that the subthreshold coefficient S is large in the case of the S transistor and is small in the case of the N-channel MOS transistor. This is as follows.

In the case of the P-channel MOS transistor as shown in FIG. 7, in order to set the threshold voltage V _TH to, for example, 0.6 V, the channel doping amount is set to 1 × 10 ¹² / cm ² , for example, 0. Dopant amount is 2 × 1 to obtain 4V
The threshold voltage V _TH is adjusted to 0 ¹² / cm ² . Also, since the n-well concentration is made thin, the channel doping amount is 1.
It is set to 5 × 10 ¹² / cm ² . In the case of an N-channel MOS transistor, the channel doping amount is set to 2 × 10 ¹² / cm ² in order to set the threshold voltage to 0.6 V, and the doping amount is set to 5 × 10 ¹¹ to set to 0.4 V, for example. / Cm
^Set to ² . The vertical axis of the graph represents the threshold voltage V _TH of the MOS transistor, and the horizontal axis represents the channel doping amount. That is, when the threshold voltage of the P-channel MOS transistor is low and when the threshold voltage of the N-channel MOS transistor is high, the doping amount is large and the substrate surface concentration directly under the gate electrode is high, so that the subthreshold coefficient is When S is large and the threshold voltage of the P-channel MOS transistor is high,
When the threshold voltage of the transistor is low, the doping amount is small and the concentration is low, so that the subthreshold coefficient S is small.

FIG. 8 shows an MO having a threshold voltage V _TH = 0.5V.
The subthreshold characteristic of an S transistor is shown. The horizontal axis of the graph is the gate voltage V _G , and the vertical axis is the drain current I.
_D is taken in logarithmic memory. The data shown in this graph were measured at a drain voltage V _D = 0.1V. The inclination of the characteristic of the conventional product 82 is small (= sub-threshold coefficient S is large), and the inclination of the characteristic of the invention product 81 is large (= sub-threshold coefficient S is small). As is apparent from the graph, for example, when the gate voltage V _G = 0 V, the drain current I of the invention product is higher than the drain current I _D of the conventional product.
_It can be seen that _D is getting smaller. This means that the leak current of the invention product is reduced.

FIG. 9 is a graph showing the relationship between the threshold voltage V _TH of the MOS transistor and the leak current (Leak). The data shown in this graph is the gate voltage V
_G = 0V, which were measured at a drain voltage V _D = 1.5V. The ordinate represents the leak current (A) in a logarithmic memory, and the abscissa represents the threshold voltage V _TH (V). As is clear from the graph, when the threshold voltage is lowered to 0.5 V in order to operate the CMOS IC at a low voltage, the leakage current of the conventional product 92 is the P channel MOS.
While the transistor is 9 × 10 ^-11 A and the N-channel MOS transistor is 7.5 × 10 ^-12 A, the leak current of the invention product 91 is 1.9 × 10 ^-12 A, N for the P-channel MOS transistor. The number of channel MOS transistors is reduced to 1.2 × 10 ^-12 A.

Since the subthreshold coefficient and the leak current can be improved in this way, high speed driving is possible and low voltage driving can be achieved. By the way, the CMOS IC using the structure according to the present invention can respond to the driving frequency up to about 1 MHz. CMOSI having such characteristics
C is most suitable for a one-chip CPU, memory, microcomputer, etc., and is mounted for control of various mobile devices and tabletop devices. Examples of these devices include a portable tape recorder, a portable CD, a pager, and a portable radio.

Next, a specific example of the semiconductor manufacturing method according to the present invention will be described in detail. First, the process of forming a gate oxide film of a CMOS transistor having an N ⁺ single-pole gate structure will be described with reference to FIG. In step A, p-type Si substrate 12
An n well 13 is formed on the surface of the. After forming an oxide film 11 which is patterned in a predetermined shape on the surface of the substrate as a mask, n-type impurity phosphorus is ion-implanted at a dose of 2 × 10 ¹² / cm ² . As described above, this dose amount is half that of the conventional one. After this, 1150
A heat treatment is performed at 6 ° C. for 6 hours to diffuse and activate the implanted impurity phosphorus to form an n well 13 as shown in the figure. A P channel MOS transistor is formed in the n well 13 and an N channel MOS transistor is formed in the adjacent portion.

In step B, field doping is performed. Therefore, first, the silicon nitride film 14 is patterned so as to cover the active region where the transistor element is formed. In particular, a photoresist 15 is also formed on the n-well 13 so as to overlap the silicon nitride film 14. In this state, the impurity boron is accelerating energy of 30 KeV and 2 ×
Ion implantation is performed at a dose of 10 ¹³ / cm ² to perform field doping. As shown, a field dope region is formed in the portion surrounding the device region.

Then, in step C, so-called LOCOS treatment is performed to form a field oxide film 16 so as to surround the element region. After this, sacrificial oxidation and its removal treatment are performed,
The foreign matter left on the surface of the substrate 12 is removed and cleaned. Finally, in step D, the surface of the substrate 12 is thermally oxidized to form a gate oxide film 17 so as to cover the element region. This thermal oxidation treatment is performed by setting the substrate temperature at 860 ° C. in an H ₂ O atmosphere to form an oxide film at a thickness of about 150 Å. Conventionally, the film thickness of this gate oxide film is about 250 Å.

Next, the subsequent process will be described with reference to FIG. First, in step E, channel doping is performed. This channel doping is performed to adjust the threshold voltage of the CMOS transistor, and p-type impurities are implanted. In the present invention, the compound BF ₂ ⁺ of boron is used as the ion species instead of boron alone as the p-type impurity for implantation. The acceleration energy is, for example, 25 KeV
Set to a degree. Since BF ₂ has a larger molecular weight than B alone, the range of ion implantation is small, and a channel dope layer can be formed in an extremely shallow region as shown in the figure. In the present invention, the gate oxide film 17 is first formed and then the channel doping is performed through the gate oxide film 17. Therefore, the channel dope layer is not affected by the history of the heat treatment performed when forming the gate oxide film 17, and the pn junction depth can be maintained as it is. On the other hand, conventionally, since the gate oxide film is formed after the channel doping, there is a problem that diffusion of the impurity B in the channel dope layer progresses.

Next, in step F, an N ⁺ polysilicon gate electrode 18 is patterned on the gate oxide film 17 by a conventional method by CVD or the like. Then, in step G, N
The source / drain regions of the channel MOS transistor are formed. At this time, the upper surface of the n well 13 in which the P channel MOS transistor is formed is masked with the photoresist 15. In this state, n-type impurity phosphorus is ion-implanted by self-alignment using the gate electrode 18 as a mask to form source / drain regions. The ion implantation conditions are, for example, 3.5 × 10 at an acceleration energy of 40 KeV.
Set to a dose of ¹⁵ / cm ² . Unlike prior art, since phosphorus is used as the n-type impurity, it is possible to obtain a predetermined conductivity of the source / drain regions without subsequent heat treatment. Therefore, since no thermal history is applied to the channel dope layer formed in the n-well 13, an extremely shallow pn junction depth can be maintained as it is. On the other hand, since arsenic having a diffusion coefficient smaller than that of phosphorus has been conventionally used as an n-type impurity, a high temperature thermal diffusion process at 950 ° C. for about 30 minutes is required.

Finally, the source / drain regions of the P-channel MOS transistor left in step H are formed. At this time, the portion of the N-channel MOS transistor previously formed is masked with the photoresist 15.
In this state, p-type impurities such as BF ₂ are ion-implanted at a high concentration to form source / drain regions. The condition of this ion implantation is, for example, 5 × 1 with an acceleration energy of 80 KeV.
The dose is set to 0 ¹⁵ / cm ² .

Subsequently, a post process of metal wiring and the like will be described with reference to FIG. Note that FIG. 12 shows C of N ⁺ unipolar gate structure.
The completed state of the MOS transistor is shown. As shown, the BPSG interlayer film 1 is formed after forming the source / drain regions of the P-channel and N-channel MOS transistors.
9 is formed on the entire surface. This interlayer film 19 is formed by CVD, for example.
Formed by a method or the like, and subsequently flattened by heat treatment. Then, the interlayer film 19 is selectively etched to remove the source /
A contact hole communicating with the drain region is formed.
After that, contact reflow treatment is performed at 900 ° C. for about 30 minutes in an O ₂ / N ₂ atmosphere. Subsequently, a metal material or the like is formed on the entire surface by vacuum vapor deposition or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 20. Finally, the entire substrate 12 is covered with the surface protective film 21. The P-channel MOS transistor thus formed has an extremely shallow localized channel dope layer 2 near the surface of the n-well 13.
2 and the pn junction depth is about 0.15 μm.

Finally, an application example of the present invention will be described with reference to FIG. This example is a one-chip type remote control microcomputer composed of CMOS transistors manufactured by the manufacturing method described above.
As shown, the microcomputer 51 has a power supply terminal V _SS.
And the power supply voltage is supplied via V _CC . This microcomputer 51 is operated at a low voltage of 1.5V
It can be operated by an external power source 52 such as a dry battery. A smoothing capacitor 53 is provided between the pair of power supply terminals.
Is externally inserted. An external oscillation source 54 is connected to the pair of clock input terminals CL ₁ and CL ₂ to receive the system clock input. This oscillation source 54
Is made of, for example, CERALOCK and has an oscillation frequency of 1 MHz. Since the microcomputer 51 is operated at a low voltage and at a high speed, it can perform a high speed operation in response to the system clock.

Further, an infrared light emitting diode 56 is connected to the RMO terminal via an external drive circuit 55. A signal for remote control is transmitted via the infrared light emitting diode 56. Also reset terminal RE
An external reset circuit 57 is connected to SET. Switch 58 of the external is connected further to the switch input terminal P ₀₀ ~P _03. In addition, an external key matrix 59 or the keyboard is connected to the interface terminal P ₁₀ to P _43.

FIG. 14 is a block diagram showing the detailed structure of the one-chip microcomputer 51 shown in FIG. As shown, this microcomputer 51 is an AL
It has logic blocks such as U, a decoder, a timer, a counter, etc., and is composed of CMOS transistors according to the present invention. It also has a memory block such as a ROM, a RAM, a table, and a register, which are all composed of CMOS transistors according to the present invention. The same applies to other input / output ports and buffers.

[0039]

As described above, the present invention provides a CMOS transistor comprising a pair of a P-channel MOS transistor having a polysilicon gate and an N-channel MOS transistor having a polysilicon gate as described above.
The pn junction depth of the MOS transistor channel region is formed as shallow as possible, and especially the P channel MOS transistor is made to approach the surface channel type device. For this reason,
There is an effect that the leak current can be significantly suppressed. In addition, the thickness of the gate oxide film was made thin, and the impurity concentration on the substrate surface immediately below the gate electrode was made as thin as possible. For this reason, the subthreshold coefficient is reduced and the switching performance of the MOS transistor is improved, so that there is an effect that high speed operation is achieved. Therefore, even if the threshold voltage is lowered, the leak current can be suppressed, so that the high-speed operation and the low-voltage driving can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view showing a structure of a CMOS transistor according to the present invention.

FIG. 2 is a schematic partial cross-sectional view showing a conventional structure.

FIG. 3 is a graph showing a depth-direction profile of boron concentration in a p-type channel dope layer.

FIG. 4 is a graph showing a relationship between a leak current of a P-channel MOS transistor and a pn junction depth.

FIG. 5 is a capacitance characteristic of a MOS structure doped with p-type impurities.

FIG. 6 is a graph showing a relationship between a subthreshold coefficient and a threshold voltage of a MOS transistor.

FIG. 7 is a graph showing the relationship between the threshold voltage of a MOS transistor and the channel doping amount.

FIG. 8 is a graph showing a subthreshold characteristic of a MOS transistor.

FIG. 9 is a graph showing a relationship between a leak current of a MOS transistor and a threshold voltage.

FIG. 10 is a process drawing showing the manufacturing method of the CMOS transistor according to the present invention.

FIG. 11 is a process drawing showing the same manufacturing method.

FIG. 12 is also a process drawing showing a state of a finished product.

FIG. 13 is a schematic diagram showing a one-chip microcomputer for remote control which is an application example of the present invention.

14 is a schematic block diagram showing the internal structure of the microcomputer shown in FIG.

[Explanation of symbols]

1 p ⁻ type Si substrate 2 n well 3 gate oxide film 4 N ⁺ polysilicon gate electrode 5 channel dope layer 6 field oxide film xj pn junction depth

Claims (11)

[Claims] 1. A CMO comprising a pair of a P-channel MOS transistor having a polysilicon gate and an N-channel MOS transistor having a polysilicon gate.
In a semiconductor device including an S transistor, the CM
The OS transistor includes a source region and a drain region formed apart from each other on a semiconductor surface, a channel dope layer localized near the surface of the semiconductor substrate between the source region and the drain region, and the channel dope. A semiconductor device including a gate insulating film formed on a semiconductor substrate on which a layer is formed. 2. The semiconductor device according to claim 1, wherein the channel dope layer has a pn junction depth of 0.2 μm or less. 3. The semiconductor device according to claim 1, wherein the gate insulating film of the MOS transistor has a thickness of 200 Å or less. 4. The CMOS transistor constitutes a RAM or a ROM, and has an operating voltage of 1.2V to 3.V.
The semiconductor device according to claim 1, wherein the semiconductor device has a voltage of 6V. 5. The semiconductor device according to claim 1, wherein the CMOS transistor constitutes a CPU, and an operating voltage is 1.2V to 3.6V. 6. A P-channel MOS transistor having a polysilicon gate and an N having a polysilicon gate.
In a one-chip type microcomputer provided with a CMOS transistor which is paired with a channel MOS transistor, the P-channel MOS transistor is a p-type source region and a drain region formed separately in an n-type region of a semiconductor substrate. And a p-type channel dope layer formed by being localized near the surface of the semiconductor substrate between the source region and the drain region, and a gate formed on the semiconductor substrate on which the channel dope layer is formed. A one-chip microcomputer including an insulating film. 7. The microcomputer according to claim 6, wherein the CMOS transistor operates at an operating voltage of 1.2V to 3.6V. And P-channel MOS transistor having a 8. N ⁺ polysilicon gate, it consists of a pair of N-channel MOS transistor having an N ⁺ polysilicon gate C
In a method of manufacturing a semiconductor device including a MOS transistor, the P-channel MOS transistor includes a step of separately forming a P-type source region and a drain region on a semiconductor substrate; Channel doping step of forming a localized p-type channel dope layer in the vicinity of the surface of the semiconductor substrate by ion-implanting BF ₂ ⁺ into the semiconductor substrate at an acceleration energy of 30 KeV or less. 9. The semiconductor device according to claim 8, further comprising a step of forming a gate insulating film having a thickness of 200 Å or less on the surface of the semiconductor substrate on which the channel dope layer is formed, prior to the channel dope step. Production method. 10. The semiconductor device according to claim 8, wherein after the channel doping step, phosphorus is ion-implanted into the semiconductor substrate in the p-type region of the N-channel MOS transistor to form the source / drain regions of the N-channel MOS transistor. Manufacturing method. 11. Prior to the channel doping step, P
In the n-type region of the channel MOS transistor, phosphorus is ion-implanted into the semiconductor substrate at a dose of 1 × 10 ¹² / cm ² to 3 × 10 ¹² / cm ² to form an n-type region including an n-type well. The method for manufacturing a semiconductor device according to claim 8.