JPH06315263A - Switching power source circuit - Google Patents

Abstract

PURPOSE:To reduce the driving losses of MOS transistors used for a rectifier in a switching power source circuit. CONSTITUTION:The amplitude of a driving voltage is optimized by respectively applying a divided voltage generated by means of capacitors 7 and 6 and another divided voltage generated by means of capacitors 10 and 11 across the gates of MOS transistors 5 and 9. Then turn-on period of the body diode of the transistor 9 is reduced by installing a voltage divider circuit composed of resistors 12 and 13 to the gate of the transistor 9 and optimizing the DC level of the transistor 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply circuit, and more particularly to a switching power supply circuit using an insulated gate field effect transistor.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional switching power supply circuit of this type. The example shown in FIG. 4 is disclosed in JP-A-55-109.
173 is a circuit disclosed in Japanese Patent No. 173, in which a switching element (MOS transistor) 2 for switching power supplied to a primary winding of a transformer 4 and AC power output to a secondary winding of the transistor 4 are rectified. The rectifying MOS transistors 5 and 9 for performing the rectification, and the choke coil 14 and the smoothing capacitor 15 for smoothing the rectified output are basically included.

The transistors 5 and 9 are both n-channel devices, the channel of the transistor 9 is connected in parallel with the secondary winding of the transformer 4, and the channel of the transistor 5 is connected in series with the secondary winding. It is provided in. The gate of the transistor 5 has a resistor 16
To the drain of the transistor 9 via the transistor 9
Are connected to the drain of the transistor 5 via the resistor 17, respectively.

In such a configuration, the transistors 5 and 9
Is driven by the transformer 4, and when the switching element 2 is on, the transistor 5 is on and the transistor 9 is off. Further, when the switching element 2 is off, the transistor 5 is off and the transistor 9 is on, so that the AC power obtained in the secondary winding of the transformer 4 is rectified to be converted into DC power.

Incidentally, 1 and 3 indicate capacitors.

[0006]

In this conventional switching power supply circuit, since the gate drive voltage of each of the rectifying transistors 5 and 9 is determined by the design of the entire power supply circuit, the gate drive voltage can be optimally set. This may not be possible and the gate drive voltage may have a larger amplitude than necessary, and the transistor drive loss increases.

Now, assuming that the gate capacitance of the MOS transistor is Cgs, the gate voltage is Vgs, and the drive frequency is f, M
The drive power P of the OS transistor is expressed as P = Cgs · Vgs ² · f. Thus, P is the gate drive voltage of 2
Since it is proportional to the power, the transistor drive loss increases in the circuit of FIG.

When the transistors 5 and 9 are off,
Since the gate potential becomes equal to the source potential, it may not be possible to achieve sufficient cutoff, especially when using a 4V drive MOS transistor having a low gate cutoff voltage. In particular, there is a drawback in that noise is superimposed on the gate drive voltage waveform when the transistor is off and the MOS transistor is accidentally turned on, resulting in increased loss and reduced efficiency.

An object of the present invention is to provide a switching power supply circuit capable of reducing the loss of a rectifying MOS transistor.

[0010]

According to the present invention, a transformer, switching means for switching the power supplied to the primary winding of the transformer, and rectifying means for rectifying the output of the secondary winding of the transformer. And a smoothing means for smoothing the rectified output, wherein the rectifying means comprises a first insulated gate electric field in which channels are connected in parallel between the secondary windings of the transformer. A first insulated gate field effect transistor having a channel connected in series to the secondary winding and having a second insulated gate field effect transistor for setting the amplitudes of the gate drive voltages of the first and second transistors, respectively. Also, a switching power supply circuit is obtained which is provided with the second amplitude setting means.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals and are examples of a forward converter circuit using MOS transistors 5 and 9 for rectification.

Amplitude setting circuits 20 and 21 for determining the amplitude of the gate drive voltage are provided at the gate portions of the respective transistors 5 and 9.
(Dashed line portion), and the gate portion of the transistor 9 is further provided with a DC level setting circuit 22 (dashed line portion) for setting a DC component of the gate drive voltage.

The amplitude setting circuit 20 includes a capacitor 7 provided between one end of the secondary winding of the transformer 4 and the gate of the transistor 5, and a capacitor 6 provided between the gate and the source of the transistor 5. , And a resistor 8 provided in parallel with the capacitor 6. Capacitor 6
The divided voltage determined by the ratio of 7 and 7 is applied to the gate of the transistor 5.

The amplitude setting circuit 21 is provided between the capacitor 11 provided between the other end of the secondary winding of the transformer 4 and the gate of the transistor 9 and between the gate and the source of the transistor 9. It is composed of a capacitor 10 and a resistor 13 provided in parallel with the capacitor 10. A divided voltage determined by the ratio of the capacitors 10 and 11 is applied to the gate of the transistor 9.

The DC level setting circuit 22 includes a resistor 12 connected between the drain and the gate of the transistor 9,
It comprises a resistor 13 connected between the gate and the source, and a divided DC voltage determined by the ratio of the resistors 12 and 13 is applied to the gate of the transistor 9.

In such a configuration, the transistors 5 and 9
Since the capacitors 7 and 11 are connected to the gates of the transistors instead of the resistors, the secondary winding voltage of the transformer 4 is not directly applied between the gates and the sources of the transistors 5 and 9, but rather to the transistors. In 5, the voltage divided by the capacitors 7 and 6 is applied, and the transistor 9
Then, the voltage divided by the capacitors 11 and 10 is applied. That is, the voltage amplitude between the gate and the source of the transistors 5 and 9 can be adjusted by the capacitors 7 and 11, respectively.

The capacitors 6 and 10 can use the gate parasitic capacitances of the transistors 5 and 9, respectively.

Further, since the DC component of the secondary winding of the transformer 4 is blocked by the capacitors 7 and 11, respectively, a pure AC voltage is applied between the gate and source of the transistor 5 and between the gate and source of the transistor 9. Means that an AC voltage whose DC component is divided by the resistors 12 and 13 is applied. That is, the direct current component of the gate-source voltage of the transistor 9 can be adjusted by the resistor 12.

FIG. 2 shows the gate drive voltage waveform of the transistor 9 in the circuit of FIG. 1 in comparison with the conventional example.
FIG. 2D shows an ON / OFF waveform of the main switch element 2,
(A) is a gate drive voltage waveform of the transistor 9 of the conventional circuit of FIG. 4 at that time. In the waveform of (a), as described above, the gate drive voltage waveform is determined by the design of the converter main circuit, and the drive loss of the transistor 9 becomes large. Further, when the transistor 9 is off, the gate potential is substantially equal to the source potential, so that the transistor 9 cannot be sufficiently cut off, which causes a loss.

FIG. 2B is a circuit diagram of the circuit of FIG.
Is a waveform of the gate drive voltage of the transistor 9 in the case where is not connected. Since the amplitude can be optimally adjusted and set by the capacitor 11, the drive loss becomes small. Further, when the transistor 9 is off, the gate potential becomes lower than the source potential.
Can be sufficiently cut off.

FIG. 2C shows a resistor 12 in the circuit of FIG.
Is a waveform of the gate drive voltage of the transistor 9 in the case where is connected and the DC component is adjusted and set. In this way, the resistance 12
Since the direct current component can be set by the voltage division ratio between the transistors 13 and 13, the periods t1 to t2 "and t3" to t4 during which the so-called body diode of the transistor 9 conducts, the period t1 to t2 'when there is no direct current component in (b). , T3 'to t4, the conduction loss and the loss due to the recovery current can be reduced.

FIG. 3 is a circuit diagram of another embodiment of the present invention, in which the same parts as in FIG. 1 are designated by the same reference numerals. In this example, the resistor 12 for setting the gate DC component of the transistor 9 is used.
Is connected to the positive side of the converter output (the positive side of the capacitor 15), and it is clear that the same effect as the effect of FIG. 1 is produced.

Although the gate of the transistor 5 is not provided with a direct current level setting circuit, the gate drive voltage waveform of the transistor 5 is supplied as it is with a short waveform for turning on / off the main switch 2 and applied to the gate of the transistor 9. This is because the sine waveform as shown in FIG. 2 (see FIGS. 2B and 2C) is not generated, so that the problem of the conduction period of the body diode of the transistor does not occur.

The resistor 8 in the circuits of FIGS. 1 and 3 is for stabilizing the gate potential of the transistor 5, and is not essential for setting the amplitude of the gate drive voltage of the transistor 5.

Although the MOS transistor is used in the above embodiment, an insulated gate field effect element can be generally used.

[0027]

As described above, according to the present invention, since the circuit for setting the amplitude and DC level of the gate drive voltage of the rectifying transistor is provided, the drive voltage of the transistor can be optimized. Therefore, there is an effect that the loss of the transistor can be reduced and the efficiency is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

2A is an operation waveform diagram of a conventional circuit, and FIG. 2B is FIG.
2 is an operation waveform diagram when the DC level is not set in the circuit of FIG. 1, (c) is an operation waveform diagram of the circuit of FIG. 1, and (d) is an on / off waveform diagram of the main switch element 2.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a diagram showing an example of a conventional switching power supply circuit.

[Explanation of symbols]

 2 main switch element 4 transformer 5,9 rectifying MOS transistor 6,7,10,11 voltage dividing capacitor 8,12,13 resistor 14 choke coil 15 smoothing capacitor

Claims (4)

[Claims] 1. A transformer, switching means for switching electric power supplied to a primary winding of the transformer, rectifying means for rectifying an output of a secondary winding of the transformer, and smoothing for smoothing the rectified output. And a rectifying means, wherein the rectifying means comprises:
A first insulated gate field effect transistor having channels connected in parallel between the secondary windings of the transformer; and a second insulated gate field effect transistor having channels connected in series to the secondary winding. Having the first and second
The switching power supply circuit is provided with first and second amplitude setting means for respectively setting the amplitude of the gate drive voltage of the transistor. 2. The switching power supply circuit according to claim 1, further comprising direct current level setting means for setting a direct current component of the gate drive voltage of the first transistor. 3. The first and second amplitude setting means respectively divide the amplitude of the gate drive voltage to divide the amplitude of the first gate drive voltage.
3. The switching power supply circuit according to claim 1, further comprising a capacitor voltage dividing circuit applied to the second transistor. 4. The switching power supply circuit according to claim 1, wherein the DC level setting circuit is a resistance voltage dividing circuit that divides the gate drive voltage.