JPH06310610A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize semiconductor manufacturing equipment capable of having wiring layer-insulating films compliable with integration raising, and to raise the yield and reliability. CONSTITUTION:This manufacture includes processes of depositing at least one insulating film 103-105 on first metal wiring 102 thicker than the first metal wiring 102, of flattening the surface of the uppermost insulating layer 105, of forming opening 106 reaching the first metal wiring 102 from the flattened surface, of forming protective films 107 on the side walls of the openings 106, and of forming second metal wiring 108 in the openings 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, which is characterized by a method of forming an interlayer insulating film for multilayer wiring suitable for a semiconductor integrated circuit device, and a semiconductor device therefor.

[0002]

2. Description of the Related Art FIG. 3 shows a wiring forming method for obtaining a conventional multilayer wiring structure. Semiconductor substrate 301
The first-layer metal electrode 302 is formed on the surface of, and the first-layer metal wiring is arranged around the other part.

A first-layer insulating film 303 is formed on such a substrate 301 by a CVD method or the like, and an organic insulator 304 is applied to alleviate a step portion generated by the metal electrode 302 and the insulating film 303. Then etch back and CVD
The second interlayer insulating film 305 is deposited by the method or the like.

After that, the interlayer insulating films 303 and 305 are opened by patterning in a photolithography process, and a second wiring metal is deposited on the opening and the interlayer insulating film 305 by a sputtering method or the like. The desired second metal wiring 306 is formed again by patterning in the photolithography process.

Among the wirings thus obtained, the interlayer insulating films 303 and 3 on and around the first metal wiring 302.
In 05, a convex portion is formed.

[0006]

However, the above-mentioned formation of the convex portion is not preferable because it causes a great step. When a multi-layer wiring structure is adopted, a step difference in the second metal wiring may occur if the level difference is large, or the protective film on the second metal wiring may not cover the wiring, resulting in a decrease in yield, which may lead to a photoelectric conversion device. If you try to apply it, it will cause noise due to stray light.

If the second wiring metal is deposited in the opening while the organic insulating film used for reducing the step is exposed in the opening for wiring, the wiring metal is corroded by the components contained in the organic insulating film. , Significantly lowering the yield of semiconductor devices.

Further, when patterning at the time of opening the interlayer insulating film, if there is a large step, it is necessary to apply a thick photosensitizer, which makes it difficult to form an opening having a high aspect ratio.
In a highly integrated semiconductor device having a gate length of 0.8 μm or less, such a phenomenon causes the aspect ratio of the openings to be 1 or more, which further reduces the yield.

[Object of the Invention] The present invention has an object of improving the yield of semiconductor devices by forming an interlayer insulating film for wiring, which can cope with high integration, with respect to the above-mentioned technical problems.

[0010]

According to the present invention, as means for solving the above-mentioned problems, at least one insulating film is deposited on the first metal wiring in a thickness thicker than that of the first metal wiring layer. And a step of flattening the uppermost insulating film surface, a step of forming an opening from the flattened surface to the first metal wiring, and a protective film on the side wall of the opening. And a step of forming a second metal wiring in the opening, the method of manufacturing a semiconductor device is provided.

Another object of the present invention is, in a method of forming an interlayer insulating film on a first metal wiring, a step of depositing a first insulating layer thicker than a first metal wiring, and a step of depositing the first insulating film on the first insulating film. A step of forming a second insulating film on the first insulating film in order to mitigate the generated step, and a step of forming a second insulating film on the second insulating film.
A step of depositing an insulating film, a step of flattening the third insulating film, a step of forming holes in the first to third insulating films, and a step of forming a hole on the insulating film. This is accomplished by depositing a fourth insulating film, leaving the fourth insulating film only on the side wall of the opening, and forming a second metal wiring in the opening.

[0012]

According to the present invention, by thickening the first interlayer insulating film, the relief of the step portion by the second interlayer insulating film is significantly increased,
When the second wiring metal is protected by the one that facilitates the flattening of the third interlayer insulating film and the fourth insulating film that is left only on the sidewalls of the openings provided in the first to third interlayer insulating films. At the same time, the aspect ratio of the opening can be changed by changing the thickness of the fourth insulating film left on the side wall of the opening.

By forming the above-mentioned interlayer insulating film, the subsequent multilayer metal wiring can be easily formed.

[0014]

EXAMPLE 1 A preferred embodiment according to the present invention is to form an interlayer insulating film on a first wiring metal, flatten the uppermost insulating film, and then provide a first opening. Another insulating film is deposited on the upper part of the first opening so as to cover the entire first opening. After that, only the bottom surface of the first opening and the insulating film deposited on the first wiring metal are removed, and the second wiring metal is embedded in the opening to form the upper wiring.

FIG. 1 is a cross-sectional view of a process flow that best illustrates the features of the present invention. In the figure, 101 is a semiconductor substrate, 102 is a first layer wiring metal, 103 is a first interlayer insulating film, 104 is a second interlayer insulating film, and 105 is a third interlayer insulating film. 106 is an opening for the second wiring metal, 107
Is a fourth-layer insulating film, and 108 is a second wiring metal.

First, referring to FIG. 1-1, a semiconductor substrate 101 is provided.
A first wiring metal is deposited on the electrode and a first metal wiring 102 is formed on the substrate by a photolithography process.

The metal used at this time is Al, Al-
It is formed of Al and an Al alloy such as Si and Al-Si-Cu by a sputtering method, and has a film thickness of 4000 to 10000 angstrom. A barrier metal such as W or Ti may be used as the base.

Next, a first interlayer insulating film 103 is deposited on the first wiring metal 102. The insulating film type is N by the CVD method.
SG, PSG, PBSG, P-Si by P-CVD method
O, P-SiN, P-SiON, etc. are used and the film thickness is 400
It is 0-15000 angstroms (FIG. 1-2).

Further, a second interlayer insulating film 104 is applied.
The material is an organic insulating film such as SOG or polyimide with a film thickness of 10
It is from 00 to 5000 angstroms. After coating, heat treatment is performed at 400 to 500 ° C. in an N ₂ atmosphere, and then the third interlayer insulating film 105 is deposited to a film thickness of 2000 to 15000 Å. Here, NSG, PSG, PBSG by the CVD method and PS by the P-CVD method are used.
iO, P-SiN, P-SiON is used (Fig. 1-3,
4).

In the subsequent photolithography process, the third interlayer insulating film is etched by about 500 to 8000 angstrom by the etch back method to completely flatten the surface of the third interlayer insulating film 105 (FIG. 1-5).

Further, a second metal wiring groove 106 is formed on the interlayer insulating film by a photolithography process (see FIG. 1-).
6). A dry etching method or the like is used as a method of opening.

In the next step, the fourth interlayer insulating film 107 is deposited so as to cover the entire opening. It is desirable to increase or decrease the film thickness in accordance with the aspect ratio of the opening portion. When the aspect ratio is 1 or less, 500 to 3000 angstrom is preferable, and when it is 1 or more, 50 to 1000 angstrom is suitable. The insulating film deposited at this time is NSG, PSG, BPSG using the CVD method, or P using the P-CVD method.
-SiO, P-SiN, P-SiON (Fig. 1-
7).

In order to leave the fourth interlayer insulating film 107 only on the side wall of the opening 106 formed on the interlayer insulating film in the photolithography process again, an etch-back method or the like is used to form the first interlayer insulating film on the third interlayer insulating film. Fourth interlayer insulating film 10 deposited on wiring metal
Remove 7. At this time, the fourth interlayer insulating film 107 remaining on the side wall of the opening 106 must completely cover the organic insulator 104 which is the second interlayer insulating film (FIG. 1-).
8).

Finally, the second wiring metal 1 is passed through this opening.
08 is embedded. As a method of depositing the second wiring metal, Al,
A sputtering method or a selective Al deposition method is used for Al and an Al-based alloy such as Al-Si and Al-Si-Cu. The film thickness is 6000 to 12000 angstroms, and patterning is performed by a photolithography process after the deposition is completed.
Used as metal wiring (Fig. 1-9). [Embodiment 2] FIG. 2 is a sectional view of a process flow showing a second embodiment of the present invention. In the figure, 201 is a semiconductor substrate, 202 is a first layer wiring metal, 203 is a first interlayer insulating film, 204 is a second interlayer insulating film, 205 is a third interlayer insulating film, and 206 is a second layer metal. An opening for wiring, 207 is a fourth interlayer insulating film, 208 is a photosensitive layer, and 209 is a second wiring metal.

First, referring to FIG. 2A, a semiconductor substrate 201 is provided.
A first wiring metal is deposited thereon, and an electrode and a first metal wiring 202 are formed on the substrate by a photolithography process.
The metals used at this time are Al, Al-Si, Al-Si-C.
It is formed of Al and an Al alloy such as u by a sputtering method and has a film thickness of 4000 to 10000 angstrom. still,
In this case, it is also possible to use a barrier metal such as W or Ti as the base of the first wiring metal.

Next, a first interlayer insulating film 203 is deposited on the first wiring metal 202. As the insulating film species, NSG, PSG, BPSG using the CVD method, P-SiO, P-SiN, P-SiON using the P-CVD method, etc., and the film thickness is 6000 to 20000 angstrom (FIG. 2). −
2).

Further, a second interlayer insulating film 204 is applied.
The material is an organic insulating film such as SOG or polyimide, and the film thickness is 1
000 to 5000 angstroms so that the step of the first interlayer insulating film 203 is filled (FIG. 2-3).

After coating, heat treatment is applied at 400 to 500 ° C. in an N ₂ atmosphere, and then the third interlayer insulating film 205 is deposited. This film thickness is 2000 to 10000 angstrom, and the insulating film type is NSG, PS by the CVD method.
G, BPSG, P-SiO, P-S by P-CVD method
iN and P-SiON are used (FIG. 2-4).

Then, the entire third interlayer insulating film 205 is removed by a photolithography process, and the second interlayer insulating film 204 is removed.
Is partially removed and etched back so that the surface of the interlayer insulating film is completely flattened (FIG. 2-5).

In the photolithography process again, the second metal wiring groove 206 is opened on the interlayer insulating film (FIG.
6).

A dry etching method or the like is used as a method for forming holes.

As a next step, the fourth interlayer insulating film 207 is formed in the entire opening 206 and the exposed second interlayer insulating film 20.
4 is deposited so as to cover the entire surface (FIG. 2-7). It is desirable that the film thickness be increased or decreased according to the aspect ratio of the opening portion, and when the aspect ratio is 1 or less, 500 to 3000 angstrom is appropriate, and when it is 1 or more, 50 to 1000 angstrom is appropriate. In this case, the insulating film is made of NSG, PSG, BPSG by the CVD method, P-SiO, P-SiN, P-SiON by the P-CVD method.

Patterning is again performed in the photolithography process, and the photosensitive agent 208 is left on the portion other than the opening 206 (FIG. 2-8).

Dry etching or the like is performed using the photosensitizer 208 as a mask to remove the fourth interlayer insulating film 207 from the upper portion of the first wiring metal 202, leaving only the sidewall of the opening 206.
When the fourth interlayer insulating film 207 is completely removed from above the first wiring metal 202, the photosensitizer 208 used as a mask is also removed (FIG. 2-9).

Finally, the second wiring metal 209 is embedded through the opening 206. As a method of depositing the second wiring metal, Al, such as Al, Al-Si, and Al-Si-Cu, and Al
For the alloy, the sputtering method or the selective Al deposition method is used. The film thickness is 6000 to 12000 Å, and after the deposition is completed, patterning is performed by a photolithography process and used as a second metal wiring (FIG. 2-10).

[0036]

As described above, according to the present invention, by depositing the first interlayer insulating film thicker than the first metal wiring and using it in combination with the second interlayer insulating film for step relief, It is easy to flatten the upper third interlayer insulating film, and the opening of the second metal wiring groove can be formed with high precision.

Further, by forming the fourth insulating film on the side wall of the opening, the second wiring metal is protected from the second interlayer insulating film and, at the same time, the fourth insulating film thickness formed on the side wall of the opening is changed. As a result, the aspect ratio of the opening can be controlled, which facilitates the formation of metal wiring in a highly integrated circuit and has the effect of improving the yield of semiconductor devices.

[Brief description of drawings]

FIG. 1 is a process flow of a cross-sectional view of a method for forming an interlayer insulating film according to a first embodiment of the present invention.

FIG. 2 is a process flow of a cross-sectional view of a method for forming an interlayer insulating film according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of an interlayer insulating film according to a conventional technique.

[Explanation of symbols]

 In FIG. 1, 101 semiconductor substrate 102 first layer metal electrode 103 first interlayer insulating film 104 second interlayer insulating film 105 third interlayer insulating film 106 opening portion (through hole) 107 fourth interlayer insulating film 108 second layer metal electrode In FIG. 2, 201 semiconductor substrate 202 first layer metal electrode 203 first interlayer insulating film 204 second interlayer insulating film 205 third interlayer insulating film 206 opening part (through hole) 207 fourth interlayer insulating film 208 photosensitive agent 209 second Layer metal electrode In FIG. 3, 301 semiconductor substrate 302 first layer metal electrode 303 first interlayer insulating film 304 second interlayer insulating film 305 third interlayer insulating film 306 second layer metal electrode

Claims (8)

[Claims] 1. A step of depositing at least one layer of an insulating film on the first metal wiring so as to be thicker than the first metal wiring layer, a step of flattening a surface of the uppermost insulating film, Forming an opening from the flattened surface to the first metal wiring; forming a protective film on the side wall of the opening; forming a second metal wiring in the opening A method of manufacturing a semiconductor device, comprising: 2. A method of forming an interlayer insulating film on a first metal wiring of a semiconductor device, the first step of depositing a first insulating film thicker than the first metal wiring, and the first insulating film. Second step of forming a second insulating film on the first insulating film for alleviating a step generated in the first insulating film, and a third step of depositing a third insulating film on the second insulating film. A fourth step of flattening the third insulating film, a fifth step of opening the first to third insulating films, and a third insulating film including the opening portion. A method for manufacturing a semiconductor device, comprising: a sixth step of depositing a fourth insulating film on the upper surface; and a seventh step of leaving the fourth insulating film only on the side wall of the opening. . 3. The method of manufacturing a semiconductor device according to claim 2, wherein the thickness of the third insulating film is equal to the thickness of the first insulating film. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the surface of the third insulating film is completely planarized. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the fourth insulating film is formed only on a side wall of the opening. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the fourth insulating film covers the second insulating film. 7. The fourth insulating film is formed only on the side wall of the opening, and the aspect ratio of the opening is controlled by changing the fourth insulating film thickness. The method for manufacturing a semiconductor device according to claim 2, wherein 8. A semiconductor device having a metal multi-layer wiring using the interlayer insulating film according to claim 1. Description: