JPH06310461A - Semiconductor manufacturing device - Google Patents
Semiconductor manufacturing deviceInfo
- Publication number
- JPH06310461A JPH06310461A JP9639393A JP9639393A JPH06310461A JP H06310461 A JPH06310461 A JP H06310461A JP 9639393 A JP9639393 A JP 9639393A JP 9639393 A JP9639393 A JP 9639393A JP H06310461 A JPH06310461 A JP H06310461A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- electrode
- packing
- contact
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Measuring Leads Or Probes (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体ウェハの面にめ
っき加工を施す半導体製造装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus for plating the surface of a semiconductor wafer.
【０００２】[0002]
【従来の技術】周知の通り、半導体ウェハの主面に金め
っき加工を施す半導体製造装置では、半導体ウェハを保
持した複数の保持治具をラック内に吊持させてめっき槽
内に収納し、半導体ウェハに接触させた電極に所定時間
通電して所望する厚さの金めっき層を半導体ウェハの主
面に形成する。2. Description of the Related Art As is well known, in a semiconductor manufacturing apparatus for subjecting a main surface of a semiconductor wafer to gold plating, a plurality of holding jigs holding semiconductor wafers are suspended in a rack and stored in a plating tank. The electrodes in contact with the semiconductor wafer are energized for a predetermined time to form a gold plating layer having a desired thickness on the main surface of the semiconductor wafer.
【０００３】以下、このような装置の保持治具について
図４乃至図７を参照して説明する。図４は斜視図であ
り、図５は正面図であり、図６は断面図であり、図７は
電極針接触部分を示す部分拡大図である。A holding jig for such an apparatus will be described below with reference to FIGS. 4 to 7. FIG. 4 is a perspective view, FIG. 5 is a front view, FIG. 6 is a cross-sectional view, and FIG. 7 is a partially enlarged view showing an electrode needle contact portion.
【０００４】図４乃至図７において、保持治具１は治具
基板２と支持板３とがヒンジ部４によって下部が連結さ
れ、治具基板２と支持板３との間に半導体ウェハ５を挟
持するように構成されている。半導体ウェハ５は支持板
３に刻設された支持凹部６に装着されるようになってい
る。In FIGS. 4 to 7, the holding jig 1 has a jig substrate 2 and a supporting plate 3 whose lower portions are connected by a hinge portion 4, and a semiconductor wafer 5 is placed between the jig substrate 2 and the supporting plate 3. It is configured to be sandwiched. The semiconductor wafer 5 is mounted in a support recess 6 formed in the support plate 3.
【０００５】また、治具基板２には支持板３に支持され
た半導体ウェハ５の主面に対向する位置に半導体ウェハ
５の形状より小さ目の開口７が形成されている。そして
開口７の支持板３側の面の周囲には半導体ウェハ５の周
縁部分を押さえるパッキング８が設けられている。さら
に、治具基板２には上部に図示しないラックに吊持させ
るための吊持部９が設けられ、この吊持部９には集電板
１０が設けられている。An opening 7 smaller than the shape of the semiconductor wafer 5 is formed in the jig substrate 2 at a position facing the main surface of the semiconductor wafer 5 supported by the support plate 3. A packing 8 for pressing the peripheral edge of the semiconductor wafer 5 is provided around the surface of the opening 7 on the support plate 3 side. Further, the jig substrate 2 is provided with a hanging portion 9 for hanging it on a rack (not shown) on the upper portion thereof, and the hanging portion 9 is provided with a current collector plate 10.
【０００６】一方、１１は導電部材で形成されたコンタ
クトピンで、その中間軸部１２はふっ素樹脂コートが施
されており、先端部分は導電部が露出するようにして接
触電極針１３が形成されている。そしてコンタクトピン
１１は後端部で集電板１０に接続され、また後端部及び
中間部が治具基板２に設けられた支持部材１４，１５に
よって支持され、電極針１３が開口７に臨むようになっ
ている。On the other hand, 11 is a contact pin formed of a conductive member, the intermediate shaft portion 12 of which is coated with a fluororesin, and the contact electrode needle 13 is formed so that the conductive portion is exposed at the tip portion. ing. The contact pin 11 is connected to the collector plate 10 at the rear end, and the rear end and the intermediate part are supported by the supporting members 14 and 15 provided on the jig substrate 2, and the electrode needle 13 faces the opening 7. It is like this.
【０００７】そして金めっき加工を施すにあたって、上
記ように構成された保持治具１に半導体ウェハ５を支持
させるには、先ず主面に所定の感光性塗布材料膜１６が
設けられた半導体ウェハ５を主面を表側にして支持板３
の支持凹部６に装着する。続いて治具基板２を支持板３
側に回動させてパッキング８が支持凹部６に装着された
半導体ウェハ５の周縁部分に密着するようにする。そし
て両板２，３が開かないようにクリップ１７を嵌めるこ
とで半導体ウェハ５は保持治具に挟持される。In order to support the semiconductor wafer 5 on the holding jig 1 having the above-described structure in performing the gold plating process, first, the semiconductor wafer 5 having a predetermined photosensitive coating material film 16 provided on the main surface thereof. With the main surface as the front side, the support plate 3
It is mounted in the supporting recess 6 of. Subsequently, the jig substrate 2 is attached to the support plate 3
The packing 8 is rotated to the side so that the packing 8 comes into close contact with the peripheral edge portion of the semiconductor wafer 5 mounted in the support recess 6. Then, the semiconductor wafer 5 is clamped by the holding jig by fitting the clip 17 so that the plates 2 and 3 are not opened.
【０００８】なお、保持治具に挟持されることによって
半導体ウェハ５の主面には電極針１３の先端部位が、感
光性塗布材料膜１６を突き通すよう所定の接触圧を持っ
て接触し、集電板１０と半導体ウェハ５とがコンタクト
ピン１１を介して導通する。By being sandwiched by the holding jig, the tip portion of the electrode needle 13 comes into contact with the main surface of the semiconductor wafer 5 with a predetermined contact pressure so as to pierce the photosensitive coating material film 16 and collects. The electric plate 10 and the semiconductor wafer 5 are electrically connected via the contact pins 11.
【０００９】こうして半導体ウェハ５を挟持した保持治
具１は、集電板１０が図示しないラックの電極部に導通
するようにして吊持部９によってラック内に複数吊持さ
れる。そしてラックは同じく図示しない金めっき槽に収
納され、半導体ウェハ５の主面がめっき液中に浸るよう
にして所定時間保持して所望の金めっき層を主面に形成
する。A plurality of the holding jigs 1 holding the semiconductor wafers 5 in this way are suspended in the rack by the suspending portion 9 so that the current collector plate 10 is electrically connected to the electrode portion of the rack (not shown). The rack is also housed in a gold plating tank (not shown), and the main surface of the semiconductor wafer 5 is immersed in a plating solution and held for a predetermined time to form a desired gold plating layer on the main surface.
【００１０】しかしながら上記の従来技術においては、
コンタクトピン１１の電極針１３が半導体ウェハ５の主
面を押圧するように接触する。このため接触した箇所に
傷１８が付き、その部分のチップ１９は不良となってし
まう。まためき加工中、コンタクトピン１１の電極針１
３はめっき液中に導電部が露出した状態になるため、電
極針１３に金析出物２０が付着し、例えば１日１回は付
着した金析出物２０を約３時間かけて除去しなけらえば
ならず、めっき加工の処理能力を向上させることが難し
い状況にあると共に保守作業に時間を要するものとなっ
ていた。However, in the above prior art,
The electrode needle 13 of the contact pin 11 contacts the main surface of the semiconductor wafer 5 so as to press it. For this reason, a scratch 18 is attached to the contacted portion, and the chip 19 in that portion becomes defective. Also, during the plating process, the electrode needle 1 of the contact pin 11
In No. 3, since the conductive part is exposed in the plating solution, the gold deposit 20 adheres to the electrode needle 13, and the adhered gold deposit 20 must be removed once a day for about 3 hours. In addition, it is difficult to improve the processing capacity of the plating process, and it takes time for maintenance work.
【００１１】[0011]
【発明が解決しようとする課題】上記のようにコンタク
トピンの電極針が半導体ウェハの主面を傷付け歩留を低
下させると共に電極針への金析出物の付着によって処理
能力の向上や保守作業時間の短縮が難しいものとなって
いた。このような状況に鑑みて本発明はなされたもの
で、その目的とするところは歩留を向上させることがで
きると共にめっき加工の処理能力の向上や保守作業時間
の短縮が行えるようにした半導体製造装置を提供するこ
とにある。As described above, the electrode needle of the contact pin scratches the main surface of the semiconductor wafer to reduce the yield, and the deposition of gold deposits on the electrode needle improves the throughput and the maintenance work time. Was difficult to shorten. The present invention has been made in view of such a situation, and an object of the present invention is to improve the yield, and at the same time, to improve the processing capacity of the plating process and shorten the maintenance work time. To provide a device.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体製造装置
は、保持治具が半導体ウェハを周縁部にパッキングを圧
接するようにして挟持すると共に、半導体ウェハに電極
を接触させて該半導体ウェハの主面のチップ形成領域に
めっき加工を施すようにした半導体製造装置において、
電極が、パッキングを貫通して半導体ウェハのチップ形
成領域外の周縁部位に液密に接触するように設けられて
いることを特徴とするものである。In a semiconductor manufacturing apparatus of the present invention, a holding jig holds a semiconductor wafer so that packing is pressed against a peripheral portion of the semiconductor wafer, and an electrode is brought into contact with the semiconductor wafer to hold the semiconductor wafer. In the semiconductor manufacturing equipment that performs plating on the chip formation area of the main surface,
It is characterized in that the electrode is provided so as to penetrate the packing and come into liquid-tight contact with a peripheral portion of the semiconductor wafer outside the chip formation region.
【００１３】[0013]
【作用】上記のように構成された半導体製造装置は、保
持治具が挟持する半導体ウェハに、電極がパッキングを
貫通して半導体ウェハのチップ形成領域外の周縁部位で
液密に接触するように設けられている。このため半導体
ウェハの主面のチップ形成領域にめっき加工を施すにあ
たり保持治具で半導体ウェハを挟持すると、両者の間に
介在するパッキングは両方に密着する。それ故、パッキ
ング内を貫通して半導体ウェハに接触している電極及び
半導体ウェハの電極接触部位はめっき液に接触すること
がなく、めっき加工中に電極に析出物が付着することが
ない。また電極は半導体ウェハのチップ形成領域外の周
縁部位に接触しているので、チップ形成領域を傷付ける
ことがない。その結果、不良チップを発生することがな
く、また装置の保守が容易なものとなる。In the semiconductor manufacturing apparatus configured as described above, the electrodes penetrate the packing and come into liquid-tight contact with the semiconductor wafer held by the holding jig at the peripheral portion outside the chip formation region of the semiconductor wafer. It is provided. For this reason, when the semiconductor wafer is sandwiched by holding jigs in performing the plating process on the chip forming region of the main surface of the semiconductor wafer, the packing interposed between the two adheres to both. Therefore, the electrode penetrating the inside of the packing and in contact with the semiconductor wafer and the electrode contact portion of the semiconductor wafer do not come into contact with the plating solution, and deposits do not adhere to the electrodes during the plating process. Further, since the electrodes are in contact with the peripheral portion of the semiconductor wafer outside the chip forming region, the chip forming region is not damaged. As a result, no defective chip is generated, and the maintenance of the device becomes easy.
【００１４】[0014]
【実施例】以下、本発明の一実施例に係る保持治具を図
１及び図２を参照して説明する。図１は保持治具を示す
図であって、図１（ａ）は正面図で、図１（ｂ）は縦断
面図であり、図２は支持板が固定されていない時の図１
（ａ）におけるＡ−Ａ矢方向視の部分拡大断面図であ
り、図３は支持板が固定された時の図１（ａ）における
Ａ−Ａ矢方向視の部分拡大断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A holding jig according to an embodiment of the present invention will be described below with reference to FIGS. 1 is a view showing a holding jig, FIG. 1 (a) is a front view, FIG. 1 (b) is a longitudinal sectional view, and FIG. 2 is a view when a support plate is not fixed.
It is a partial expanded sectional view of the AA arrow direction in (a), and FIG. 3 is a partial expanded sectional view of the AA arrow direction in FIG. 1 (a) when a support plate is fixed.
【００１５】図１及び図３において、保持治具２１は硬
質ポリ塩化ビニールなどの絶縁材料、あるいはアルマイ
ト処理による絶縁表面を有するアルミニウムによって形
成された治具基板２２と支持板２３とが下部に設けられ
たヒンジ部２４によって連結され、治具基板２２と支持
板２３は矢印Ｂのように回動するように構成されてい
る。In FIGS. 1 and 3, a holding jig 21 is provided with a jig substrate 22 and a supporting plate 23, which are made of an insulating material such as hard polyvinyl chloride or aluminum having an insulating surface obtained by alumite treatment, and a supporting plate 23 in the lower portion. The jig substrate 22 and the support plate 23 are connected by the hinge portion 24 formed so as to rotate as indicated by an arrow B.
【００１６】支持板２３には、その治具基板２２に対面
する側の面に、主面が治具基板２２に対面するように半
導体ウェハ２５を装着可能とする略同形状の支持凹部２
６が刻設されている。そして、この支持凹部２６に半導
体ウェハ２５を装着した場合には、半導体ウェハ２５の
主面と支持板２３の表面とが略同一面を形成するように
なっている。On the surface of the support plate 23 facing the jig substrate 22, a supporting recess 2 of substantially the same shape can be mounted so that the semiconductor wafer 25 can be mounted so that the main surface faces the jig substrate 22.
6 is engraved. When the semiconductor wafer 25 is mounted in the support recess 26, the main surface of the semiconductor wafer 25 and the surface of the support plate 23 form substantially the same surface.
【００１７】また治具基板２２には、支持板２３に装着
された半導体ウェハ２５の主面に対向する位置に、半導
体ウェハ２５の外形形状より小さ目で半導体ウェハ２５
のチップ形成領域に対応する開口２７が形成されてい
る。そして開口２７の支持板２３に面する側の縁部に沿
った全周の面には、半導体ウェハ２５のチップ形成領域
外である周縁部分に密着し、この部分を押さえるシリコ
ンゴム等でなるパッキング２８が設けられている。On the jig substrate 22, a semiconductor wafer 25 smaller than the outer shape of the semiconductor wafer 25 is provided at a position facing the main surface of the semiconductor wafer 25 mounted on the support plate 23.
The opening 27 corresponding to the chip forming region is formed. Then, the surface of the entire circumference of the opening 27 along the edge facing the support plate 23 is in close contact with the peripheral portion of the semiconductor wafer 25 outside the chip formation region, and a packing made of silicon rubber or the like that presses this portion. 28 is provided.
【００１８】このため半導体ウェハ２５を装着し支持す
る支持板２３をヒンジ部２４で治具基板２２側に矢印Ｂ
のように回動させることによって半導体ウェハ２５は、
その周縁部分にパッキング２８が密着し開口２７からチ
ップ形成領域が覗くような状態で、治具基板２２と支持
板２３の間に挟持される。For this reason, the support plate 23 for mounting and supporting the semiconductor wafer 25 is moved to the jig substrate 22 side by the arrow B at the hinge portion 24.
The semiconductor wafer 25 is rotated by
The packing 28 is sandwiched between the jig substrate 22 and the support plate 23 in a state where the packing 28 is in close contact with the peripheral portion and the chip forming region is seen through the opening 27.
【００１９】さらに治具基板２２には上部に図示しない
ラックに吊持させるための吊持部２９が設けられ、この
吊持部２９には集電板３０が設けられている。そして集
電板３０には治具基板２２に刻設された溝内に、溝開口
をシール材で覆うわれるようにして液密に埋め込まれた
導電線３１の片端が接続されている。Further, the jig substrate 22 is provided with a suspending portion 29 for suspending it on a rack (not shown) on the upper portion thereof, and the suspending portion 29 is provided with a collector plate 30. Then, one end of a conductive wire 31 which is liquid-tightly embedded in the groove formed in the jig substrate 22 is connected to the current collector plate 30 so that the groove opening is covered with a sealing material.
【００２０】また３２は治具基板２２に設けられた電極
部で、これはそれぞれ導電部材で形成されたスリーブ３
３と、このスリーブ３３に内蔵されたスプリングによっ
て付勢されてスリーブ３３の一端側から電極尖端部３４
が延出するコンタクトピン３５と、スリーブ３３の他端
側に被せたステンレス等でなるキャップ３６を備えてい
る。Reference numeral 32 denotes an electrode portion provided on the jig substrate 22, which is a sleeve 3 formed of a conductive member.
3 and an electrode tip portion 34 from one end side of the sleeve 33 urged by a spring built in the sleeve 33.
And a cap 36 made of stainless steel or the like covering the other end of the sleeve 33.
【００２１】そして電極部３２は、治具基板２２の開口
２７の縁部に形成された段付孔３７と、この段付孔３７
に連通するようにパッキング２８に形成された貫通孔３
８に、コンタクトピン３５が進退可能となるような状態
で取着されている。なおコンタクトピン３５の電極尖端
部３４は、半導体ウェハ２５を挟持していない状態では
パッキング２８の面から外方に突出している。The electrode portion 32 has a stepped hole 37 formed at the edge of the opening 27 of the jig substrate 22, and the stepped hole 37.
Through hole 3 formed in packing 28 so as to communicate with
8, the contact pin 35 is attached so that it can be moved back and forth. The electrode tip 34 of the contact pin 35 projects outward from the surface of the packing 28 when the semiconductor wafer 25 is not held.
【００２２】一方、電極部３２のキャップ３６には導電
線３１の他端が接続されており、コンタクトピン３５の
電極尖端部３４と集電板３０とが導通するようになって
いる。そしてキャップ３６には、治具基板２２と同材料
で形成されたカバー３９がこれを覆うように取り付けら
れている。これによって電極部３２は電極尖端部３４が
パッキング２８の面で露出するのみで、他の部分は治具
基板２２等の中に密封される。On the other hand, the other end of the conductive wire 31 is connected to the cap 36 of the electrode portion 32 so that the electrode tip portion 34 of the contact pin 35 and the current collector plate 30 are electrically connected. A cover 39 made of the same material as the jig substrate 22 is attached to the cap 36 so as to cover the same. As a result, the electrode tip 32 has only the electrode tip 34 exposed on the surface of the packing 28, and the other portions are sealed in the jig substrate 22 and the like.
【００２３】さらに治具基板２２には長角孔４０が形成
されていて、この長角孔４０にはロック機構４１が設け
られており、これによって治具基板２２側に回動された
支持板２３が治具基板２２に密着するように固定され
る。例えばロック機構４１は取付けレバー４２と取外し
レバー４３、ロック爪４４を有するもので、取付けレバ
ー４２を操作することでロック爪４４が閉じ、支持板２
３が治具基板２２に密着した状態で固定される。そして
取外しレバー４３を操作しロック爪４４を開くことによ
って支持板２３の密着状態を解除することができる。Further, an oblong hole 40 is formed in the jig substrate 22, and a locking mechanism 41 is provided in the oblong hole 40, whereby the support plate rotated to the jig substrate 22 side. 23 is fixed so as to be in close contact with the jig substrate 22. For example, the lock mechanism 41 has a mounting lever 42, a removal lever 43, and a lock claw 44. By operating the mounting lever 42, the lock claw 44 is closed and the support plate 2
3 is fixed in a state of being in close contact with the jig substrate 22. The contact state of the support plate 23 can be released by operating the detaching lever 43 and opening the lock claw 44.
【００２４】そして半導体ウェハ２５に金めっき加工を
施すには、上記ように構成された保持治具２１に半導体
ウェハ２５を挟持させ、さらに図示しないラック内に複
数吊持し、このラックを同じく図示しない金めっき槽に
収納して行なわれる。In order to perform the gold plating on the semiconductor wafer 25, the semiconductor wafer 25 is clamped by the holding jig 21 having the above-mentioned structure, and a plurality of racks are suspended in a rack (not shown). Not performed in a gold plating tank.
【００２５】このため、先ず主面に所定の感光性塗布材
料膜４５が設けられた半導体ウェハ２５を主面を表側に
して支持板２３の支持凹部２６に装着する。続いて治具
基板２２を支持板２３側に回動させてパッキング２８が
支持凹部２６に装着された半導体ウェハ２５の周縁部分
に密着するようにする。そしてロック機構４１を操作す
ることで支持板２３を開かないように治具基板２２に固
定する。For this reason, first, the semiconductor wafer 25 having a predetermined photosensitive coating material film 45 provided on the main surface is mounted in the support recess 26 of the support plate 23 with the main surface facing the front side. Subsequently, the jig substrate 22 is rotated toward the support plate 23 so that the packing 28 is brought into close contact with the peripheral portion of the semiconductor wafer 25 mounted in the support recess 26. Then, by operating the lock mechanism 41, the support plate 23 is fixed to the jig substrate 22 so as not to open.
【００２６】こうすることで半導体ウェハ２５のチップ
形成領域が開口２７から除いた状態になり、パッキング
２８の面が半導体ウェハ２５の周縁面に圧接する。同時
に、パッキング２８の面から外方にスプリングによって
付勢され突出していたコンタクトピン３５の電極尖端部
３４が、半導体ウェハ２５の周縁部分、例えば外周から
２ｍｍ程度内側の部分に所定の押圧でもって接触する。
こうして電極尖端部３４が設けられているパッキング２
８の貫通孔３８が、半導体ウェハ２５の周縁面によって
閉塞された状態になり、電極部３２は全て治具基板２２
等の中に密封される。By doing so, the chip forming region of the semiconductor wafer 25 is removed from the opening 27, and the surface of the packing 28 is pressed against the peripheral surface of the semiconductor wafer 25. At the same time, the electrode tip 34 of the contact pin 35, which is urged outward by a spring from the surface of the packing 28, comes into contact with the peripheral portion of the semiconductor wafer 25, for example, a portion inside by about 2 mm from the outer periphery with a predetermined pressure. To do.
Packing 2 thus provided with electrode tips 34
The through holes 38 of No. 8 are closed by the peripheral surface of the semiconductor wafer 25, and all the electrode portions 32 are in the jig substrate 22.
Etc. sealed in.
【００２７】この後に、半導体ウェハ２５を挟持した保
持治具２１は、集電板３０が図示しないラックの電極部
に導通するようにして吊持部２９によってラック内に複
数吊持され、ラックを金めっき槽に収納される。そして
半導体ウェハ２５の主面がめっき液中に浸るようにす
る。そして所定時間保持して該主面に所望の金めっき層
を形成する。After that, the holding jigs 21 holding the semiconductor wafers 25 are suspended in the racks by the suspending portions 29 so that the collector plates 30 are electrically connected to the electrode portions of the racks (not shown). It is stored in a gold plating tank. Then, the main surface of the semiconductor wafer 25 is immersed in the plating solution. Then, it is held for a predetermined time to form a desired gold plating layer on the main surface.
【００２８】この際、パッキング２８が半導体ウェハ２
５の周縁面に圧接するため、段付孔３７と貫通孔３８の
内部が略液密状態に保持され、この内部に設けられた電
極部３２及び半導体ウェハ２５の電極尖端部３４の接触
部位がめっき液にほとんど接触することがない。このた
め電極尖端部３４は半導体ウェハ２５のチップ形成領域
には接触せずにめっき加工が行なえ、また電極尖端部３
４には金析出物が付着することがない。At this time, the packing 28 is the semiconductor wafer 2.
Since the inner surface of the stepped hole 37 and the through hole 38 is held in a substantially liquid-tight state due to the pressure contact with the peripheral surface of 5, the contact portion between the electrode portion 32 and the electrode tip portion 34 of the semiconductor wafer 25 provided inside the stepped hole 37 and the through hole 38 is Almost no contact with the plating solution. Therefore, the electrode tip portion 34 can be plated without coming into contact with the chip forming region of the semiconductor wafer 25, and the electrode tip portion 3
No gold deposits adhere to No. 4.
【００２９】そして、半導体ウェハ２５の主面に所望の
金めっき層を形成してから、保持治具２１は金めっき槽
から出されラックから外される。外された後保持治具２
１は、ロック機構４１の取外しレバー４３が操作される
ことでロック爪４４が開かれ治具基板２２と支持板２３
の密着状態が解除され、所望の金めっき層が形成された
半導体ウェハ２５が取り外される。Then, after forming a desired gold plating layer on the main surface of the semiconductor wafer 25, the holding jig 21 is taken out of the gold plating tank and removed from the rack. Holding jig 2 after removed
1 is that the lock claw 44 is opened by operating the removal lever 43 of the lock mechanism 41 and the jig substrate 22 and the support plate 23.
The close contact state is released, and the semiconductor wafer 25 on which the desired gold plating layer is formed is removed.
【００３０】以上説明したように本実施例は構成されて
いるので、コンタクトピン３５の電極尖端部３４は半導
体ウェハ２５の周縁部分に圧接して通電し、チップ形成
領域には接触しない。このためチップ形成領域に電極尖
端部３４による傷がつくことがなく、それによって不良
チップを生み出すことがなくなり、歩留が向上したもの
となる。Since the present embodiment is constructed as described above, the electrode tip portions 34 of the contact pins 35 are pressed against the peripheral portion of the semiconductor wafer 25 to conduct electricity and do not contact the chip formation region. For this reason, the chip forming region is not scratched by the electrode tip portion 34, so that a defective chip is not produced and the yield is improved.
【００３１】また、半導体ウェハ２５の電極尖端部３４
はめっき液にほとんど接触することがないことから、電
極尖端部３４には金析出物が付着することがない。この
ため、例えば付着した金析出物を約３時間かけて１日１
回除去していた保守作業がなくなり、２週間に１回の１
０〜２０分の電極部３２の点検を行なう程度の保守作業
でよいことになる。さらに保守作業による途中停止がな
いので装置としての稼動時間が増し、めっき加工の処理
能力を、例えば従来が２５０ロット／月であったもの
を、３００ロット／月と向上させることができる。The electrode tip 34 of the semiconductor wafer 25 is also used.
Since there is almost no contact with the plating solution, gold deposits do not adhere to the electrode tip 34. For this reason, for example, the deposited gold deposits can be taken daily for about 3 hours.
Maintenance work that had been removed once is lost, and once every two weeks
Maintenance work of only inspecting the electrode portion 32 for 0 to 20 minutes is sufficient. Further, since there is no intermediate stop due to maintenance work, the operating time of the apparatus is increased, and the processing capacity of the plating process can be improved from the conventional 250 lots / month to 300 lots / month.
【００３２】尚、本発明は上記の実施例のみに限定され
るものではなく、要旨を逸脱しない範囲内で適宜変更し
て実施し得るものである。The present invention is not limited to the above-described embodiments, but can be implemented with various modifications without departing from the scope of the invention.
【００３３】[0033]
【発明の効果】以上の説明から明らかなように本発明
は、保持治具が挟持する半導体ウェハに、電極がパッキ
ングを貫通して半導体ウェハのチップ形成領域外の周縁
部位で液密に接触する構成としたことにより、歩留を向
上させることができると共にめっき加工の処理能力の向
上や保守作業時間の短縮が行える等の効果を奏する。As is apparent from the above description, according to the present invention, the electrode is liquid-tightly contacted with the semiconductor wafer held by the holding jig at the peripheral portion of the semiconductor wafer outside the chip forming region through the packing. With the configuration, the yield can be improved, the processing capacity of the plating process can be improved, and the maintenance work time can be shortened.
【図１】本発明の一実施例に係る保持治具を示す図であ
って、図１（ａ）は正面図で、図１（ｂ）は縦断面図で
ある。FIG. 1 is a view showing a holding jig according to an embodiment of the present invention, FIG. 1 (a) is a front view, and FIG. 1 (b) is a vertical sectional view.
【図２】本発明の一実施例における支持板が固定されて
いない時の図１（ａ）のＡ−Ａ矢方向視の部分拡大断面
図である。FIG. 2 is a partially enlarged cross-sectional view taken along the line AA of FIG. 1A when the support plate is not fixed in the embodiment of the present invention.
【図３】本発明の一実施例における支持板が固定された
時の図１（ａ）のＡ−Ａ矢方向視の部分拡大断面図であ
る。FIG. 3 is a partial enlarged cross-sectional view taken along the line AA of FIG. 1A when the support plate is fixed in the embodiment of the present invention.
【図４】従来例に係る保持治具を示す斜視図である。FIG. 4 is a perspective view showing a holding jig according to a conventional example.
【図５】従来例の保持治具の正面図である。FIG. 5 is a front view of a conventional holding jig.
【図６】従来例の保持治具の断面図である。FIG. 6 is a cross-sectional view of a conventional holding jig.
【図７】従来例の保持治具の電極針接触部分を示す部分
拡大図である。FIG. 7 is a partially enlarged view showing an electrode needle contact portion of a conventional holding jig.
２１…保持治具 ２２…治具基板 ２３…支持基板 ２５…半導体ウェハ ２８…パッキング ３２…電極部 ３４…電極尖端部 ３５…コンタクトピン ３８…貫通孔 21 ... Holding jig 22 ... Jig substrate 23 ... Support substrate 25 ... Semiconductor wafer 28 ... Packing 32 ... Electrode portion 34 ... Electrode tip portion 35 ... Contact pin 38 ... Through hole
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/68 Ｎ 8418−4Ｍ Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 21/68 N 8418-4M
Claims (1)
キングを圧接するようにして挟持すると共に、前記半導
体ウェハに電極を接触させて該半導体ウェハの主面のチ
ップ形成領域にめっき加工を施すようにした半導体製造
装置において、前記電極が、前記パッキングを貫通して
前記半導体ウェハのチップ形成領域外の周縁部位に液密
に接触するように設けられていることを特徴とする半導
体製造装置。1. A holding jig sandwiches a semiconductor wafer so that a packing is pressed against a peripheral portion of the semiconductor wafer, and an electrode is brought into contact with the semiconductor wafer to perform plating on a chip formation region of a main surface of the semiconductor wafer. In the semiconductor manufacturing apparatus as described above, the electrode is provided so as to penetrate the packing and come into liquid-tight contact with a peripheral portion of the semiconductor wafer outside the chip formation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9639393A JPH06310461A (en) | 1993-04-23 | 1993-04-23 | Semiconductor manufacturing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9639393A JPH06310461A (en) | 1993-04-23 | 1993-04-23 | Semiconductor manufacturing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06310461A true JPH06310461A (en) | 1994-11-04 |
Family
ID=14163719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9639393A Pending JPH06310461A (en) | 1993-04-23 | 1993-04-23 | Semiconductor manufacturing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06310461A (en) |
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| US7833393B2 (en) | 1999-05-18 | 2010-11-16 | Ebara Corporation | Semiconductor wafer holder and electroplating system for plating a semiconductor wafer |
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| WO2000070128A1 (en) * | 1999-05-18 | 2000-11-23 | Ebara Corporation | Plating jig and device for semiconductor wafer |
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| EP1164209A2 (en) * | 2000-05-24 | 2001-12-19 | Yamamoto-Ms Co, Ltd. | Cathode cartridge of testing device for electroplating and testing device for electroplating |
| EP1164209A3 (en) * | 2000-05-24 | 2003-02-12 | Yamamoto-Ms Co, Ltd. | Cathode cartridge of testing device for electroplating and testing device for electroplating |
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