JPH06289840A - Flowable display control system - Google Patents

Abstract

PURPOSE:To provide the flowable display control system which scrolls an image freely in both longitudinal and lateral directions at a high speed. CONSTITUTION:The flowable display control system which scans and reads out data 11 arrayed in a matrix of bits, stores the data in a 1st storage means 12 in row-directional one-byte units, and scrolls and flowingly displays information on display screen 14 performs the row/column conversion of the information, stored in the storage means 12, as bit information in column-directional one-byte units of the data 11 to be displayed under software control and stores the converted data in a 2nd storage means 15, and then transfers them to a 2nd screen information storage means 16. Bits constituting respective bytes following a byte specified by read start address assignment are taken out under hardware control as serial data as a row-directional array of bits of the data 11 to be displayed and displayed on a display screen 14. Similarly, bits constituting respective bytes are taken out as serial data in a row-directional array of bits of the data 11 to be displayed and displayed on the display screen 14; and the above operation is repeated to scroll and display the information laterally on the display screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fluidized display control system for displaying informational characters or pictures by fluidizing them vertically (vertically) or horizontally (horizontally).

[0002]

2. Description of the Related Art In this type of flow display method, when displaying characters and pictures in a vertical direction, generally, FIG.
The method is as shown in. In the figure, the data to be displayed (characters, figures, pictures, etc.) 1 is 2 bytes x 2
If it consists of bytes (16 bits × 16 bits arranged in a matrix), it is 8 in the row direction.
As shown in the drawing, each bit is, for example, the first byte A1, the second byte A2, the third byte A3, and so on, and each of these 1-byte units of data is used as VRAM (Video Random) as screen information storage means. Access Memory) 2 to 1
Byte A1, second byte A2, third byte A3, ...
・ Storing by 1 byte unit.

When displaying this, VRAM is used.
Starting from 2, first byte A1 is used as a read start point, and data for each byte such as first byte A1, second byte A2, third byte A3, ... Output to 3. In the display unit 3, this serial data is allocated on the display screen 4 as shown in the drawing, whereby characters, figures, pictures, etc. are displayed.

Next, the third byte A3 is used as a read start address, and the third byte A3 and the fourth byte A4, 5 are set.
Bytes A5, ... Are read out and output as serial data to the display unit 3.
Display on top. In this manner, when the third byte A3 is used as the read start address and is displayed, the display content is such that the first byte A1 and the second byte A2 are missing. That is, one line of the character "A" in the upper horizontal direction is missing. Then, the fifth byte A5 is set as the read start address, and the seventh byte A7 is set as the read start address. Then, the display is sequentially performed, and "A" is displayed on the display screen 4. The character "" appears to flow (scroll) from bottom to top.

The above is the flow in the vertical direction (hereinafter referred to as vertical scroll). In the case of this vertical scroll, V
The first byte A1, the second byte A2, the third byte A3, ... Are read from the RAM 2 in this order and displayed in that order. That is, since the flow control method shown here is a method of laterally scanning and reading the horizontally arranged bits constituting the data 1 to be displayed, the horizontal control (row direction) is stored in the VRAM in units of 1 byte, and Of the contents, a predetermined address can be read as a starting point for reading and the contents can be read and displayed on the display screen, so that vertical scrolling can be easily performed. In other words, this method can be said to be hardware for vertical scrolling.

[0006]

However, in the above vertical scroll hardware, horizontal flow (hereinafter referred to as horizontal scroll) is displayed, that is, for example, the character "A" is changed from right to left. When flowing in the direction, the above vertical scroll hardware cannot be used as it is, and horizontal scroll hardware must be used.

Therefore, in such a fluidized display system, if the vertical scroll and the horizontal scroll are freely performed, it cannot be performed by any one of the hardware. In other words, the hardware does not have the degree of freedom to freely perform both vertical scrolling and horizontal scrolling, and there is no other way but to have dedicated hardware such as vertical scrolling hardware and horizontal scrolling hardware. There wasn't. Further, if it is attempted to do so by software, there is a speed problem with software having a slow processing speed, and smooth scrolling cannot be performed at high speed, which is far from practicality.

According to the present invention, by using the fluidized display control by dividing the function into hardware and software, it is possible to perform both vertical scrolling and horizontal scrolling freely and smoothly at high speed. The purpose is to realize the control method.

[0009]

FIG. 1 illustrates the principle of the present invention. In the figure, 11 indicates the structure of data that is displayed in a floating manner. Here, in order to make the description easy to understand, one character is 8 bits × 8 bits (1 byte × 1 byte) arranged in a matrix. It will be described as being configured. .., 8 in the horizontal arrangement direction (row direction) are attached to each bit, and numbers in the vertical arrangement direction (column direction) are a, b ,.
A code for 8 bits of h is added, and each bit is a
It is expressed as 1, a2, ... h8. In addition, every 8 bits in the horizontal arrangement direction (for example, a1, a2, ...
・ A8) is set to 1 byte, and X is set for each 1 byte.
The reference numerals 1, X2, X3, ... X8 are attached. Therefore, the first byte X1 is a1, a2, a3.
... a8, 2nd byte X2 is b1, b2, b3, ...
・ B8, 3rd byte X3 is c1, c2, c3, ... c
8, ..., 8th byte X8 is h1, h2, h3, ...
・ It consists of the bit h8.

When such data 11 to be displayed is vertically scrolled, the data 11 to be displayed is displayed from the first byte X1 and the bits a1, a2 and the bits constituting the data 11 are displayed.
... A8 is scanned laterally and read out, and the first storage means (hereinafter referred to as the first RAM) is read for each 1-byte unit.
Store in 12. Then, the contents of the first RAM 12 are transferred to the first screen information storage means (hereinafter referred to as the first VRAM) 13 by direct memory access. The content of this first VRAM 13 is also the first R
As with the contents of AM12, the read bit is 1
It is stored in bytes.

In order to display the contents of the first VRAM 13 on the display screen 14, first of all, the first VRAM 13 is displayed.
The first byte X1 of 13 is used as the read start address, the first byte X1, the second byte X2, and the third byte X
Bit data for 8 bytes is read out and output as serial data, such as the 8th byte X8, and this serial data is output to a predetermined position on the display screen 14 (in this case, 8 bits are set to 1 in the horizontal direction). By allocating (as lines), information consisting of 8 bytes is displayed. Next, the second byte is used as the read start address, the second byte and subsequent data are read in the same manner as above, such as the second byte X2, the third byte X3, the fourth byte X4, ... The eighth byte X8. Then, it is displayed on the display screen 14. In this case, the content displayed on the display screen 14 is the data in which the first byte X1 is missing.

As described above, by sequentially moving the read start addresses to the next read and displaying, the display screen 14 displays characters flowing from bottom to top. That is, vertical scrolling display is performed.

On the other hand, in this way, the data 11 to be displayed is
The bits (8 × 8 bits in this case) that make up 1 are made into 1 byte with 8 bits arranged horizontally, and are scanned and read out in the horizontal direction to display them on the display screen 14. In the display control method, when the display to make the characters to be displayed flow in the left-right direction, that is, the horizontal scroll display is performed as follows.

First, each bit a1, a2, ... A8 of the first byte X1 of the data 11 to be displayed, the second byte X
2 bits b1, b2, ... b8, 3rd byte X3
, C8, ..., Each of the bits h1, h2, ... h8 of the 8th byte X8 is the same as that described above from the first byte X1. The data is scanned and read in the direction (row direction) and stored in the first RAM 12 in units of 1 byte in the row direction. Then, row / column conversion is performed so that the information stored in the first RAM 12 in units of 1 byte in the row direction becomes information in units of 1 byte in the column direction of the data 11 to be displayed. The row / column converted and rearranged data is stored in the second RAM 15 as illustrated. By carrying out such bit expansion, the contents of the second RAM 15 are such that the arrangement of bits in the horizontal direction (row direction) is a1, b1, ... H in the first line.
The first and second rows are arranged in the vertical direction (column direction) such as a2, b2 ... h2. The bit expansion from horizontal arrangement to vertical arrangement of each bit is performed by software control.

Then, the contents of the second RAM 15 are transferred to the second VRAM 16 by direct memory access.
Transfer to. Also in this case, as in the case of the vertical scroll, each bit is read by the horizontal scan and stored in the second VRAM 16 in 1-byte units. Therefore, the content of the second VRAM 16 is the first byte Y1.
, A1, b1, ... h1, the content of the second byte Y2 is a2, b2, ... h2, the content of the third byte Y3 is a3, b3 ,. , 8th byte Y
The contents of 8 are a8, b8, ... H8.

To display this on the display screen 14,
First, the first byte Y1 of the second VRAM 16 is read as the read start address. In this case, first a1, then a2, and then a3, ..., b1,
b2, ..., h1, h2 ,.
The data is taken out in the column direction as serial data starting from the bit. Specifically, each bit (in this case, a1, b
1, ... h1) as a starting point, and the operation of extracting bits every 8 bits in the horizontal direction is repeated.
The serial data extracted in this way is displayed on the display screen 1
4 is displayed on the screen. When this first byte Y1 is used as the read start address, the display screen 14
Characters drawn with 8 bytes of bits are displayed above.

Then, the second byte Y2 is read as a read start address, and in this case as well, each bit (in this case, a2, b2, ... Starting from h2), the bits are taken out every 8 bits in the horizontal direction. Therefore, in this case, first a2, then a3, and then a4 ..., b2, b3 ,.
2, h3, ... Bits are taken out and output as serial data. The serial data extracted in this way is allocated and displayed on the display screen 14. When this second byte Y2 is used as the read start address, a2 to a8,
Characters drawn by bits b2 to b8, ... h2 to h8, that is, the vertical direction 1 at the left end of the data 11 to be displayed
Those in which the bits (a1, b1, c1, ... h1) in the column are missing are displayed.

As described above, the read start address is sequentially transferred from the second VRAM 16 to read the data, and each bit forming the byte that is the read start address is used as the starting point and once every eight bits in the horizontal direction. By repeating the operation of extracting bits in a divided manner, the characters are displayed on the display screen 14 in a flow display from the right to the left in the figure, that is, a horizontal scroll display. Display screen 1 from this second VRAM 16
The control of data transfer to 4 is performed by hardware control.

[0019]

In this way, the bits (8.times.8 bits in this case) forming the data 11 to be displayed are made into 1 byte with 8 bits arranged side by side, and this is scanned and read out in the horizontal direction to display the display screen. In the case of performing vertical scrolling in a fluidized display control system with a hardware configuration such as displaying on 14 screens, bit data for each byte is stored in the first RAM 12 and stored in the first VRAM 13 by direct memory access. By transferring and displaying the contents on the display screen 14 first from the first byte and then from the second byte, vertical scroll display is performed.

When performing horizontal scrolling, first,
The horizontally arranged bit data for each byte stored in the first RAM 12 is vertically and bit-expanded by software control and stored in the second RAM 15. Then, the contents of this second RAM 15 are transferred to the second VRAM 16 by direct memory access, and from this second VRAM 16, first, the data of the first byte is converted into each bit (in this case, the data) forming the byte. , A1, b
1, ... h1) as a starting point, a bit is taken out once every 8 bits in the horizontal direction and displayed on the display screen 14, then the read start address is moved and the data is read out. Similarly, each bit (in this case, a2
From b2, ... h2) as a starting point, a bit is taken out once every eight bits in the horizontal direction and is displayed on the display screen 14 by repeating the operation. The characters are displayed in a flow from right to left in the figure, that is, a horizontal scroll display. This second
Data transfer control from the VRAM 16 to the display screen 14 is performed by hardware control.

In this horizontal scroll display, the row / column conversion of the bits forming the data 11 to be displayed is performed before the data 11 to be displayed is displayed on the display screen 14, so Even if the row / column conversion is performed by software with a low processing speed, the smoothness or speed of scrolling is not affected.

Therefore, in the fluidized display control method in the hardware configuration in which each bit in the horizontal row forming the data 11 to be displayed is horizontally scanned and read to display it on the display screen 14, the original vertical display is adopted. Not only scroll display but also horizontal scroll display can be enabled.

[0023]

EXAMPLE An example of the present invention will be described below. 2 is a configuration diagram for explaining the embodiment, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2, reference numeral 21 denotes a CPU, and its address bus AB and data bus DB have a direct memory access controller (hereinafter referred to as DMAC) 22, the first RAM 12, the second RAM 15, and the second RAM 15 described in FIG. 1 VRAM 13, 2nd VRAM
16 are connected to each other, and a register 23 that holds a switching signal for switching between vertical scrolling and horizontal scrolling is also connected.

The contents of the first VRAM 13 are input to the latch circuit 24 and then to the shift register 25. Timings of reading data from the first VRAM 13 and inputting data to the latch circuit 24 and the shift register 25 are performed in synchronization with the count output from the display counter 26. Then, the shift register 25 outputs the parallel data from the first VRAM 13 as serial data, and the serial data is sent to the selector 27.

The contents of the second VRAM 16 are as follows.
1 / 8th selector 28 causes 1st bit, 9th bit, 1
One bit out of eight bits is sequentially read out, such as the seventh bit. This will be described below with reference to the example of FIG. That is, the second VRAM1
As shown in FIG. 1, the contents of 6 are a1 and b for the first byte Y1.
1, ... h1, second byte Y2 is a2, b2, ...
h2, ..., 8th byte Y8 is a8, b8, ... h
8 and, for example, assuming that the first byte Y1 is the read start address, each bit (a1, b1, ... h1 in this case) forming the byte that is the read start address is the starting point. Then, the bits are taken out every 8 bits in the horizontal direction. Therefore, in this case, by the 1/8 selector 28, first, a1, then a2, then a3 ... a8, and then b1, b2, ... b8 ,. ，
.., h8, and these are output as serial data.

The serial data from the 1/8 selector 28 is sent to the selector 27, and the register 23.
Switching between vertical scrolling and horizontal scrolling is performed by a switching signal from. Reference numeral 29 is a display unit.

The operation of the above arrangement will be described below. In order to make the description easier to understand, the description of this embodiment will be made assuming that one character is composed of 8 bits × 8 bits (1 byte × 1 byte) arranged in a matrix.

First, the case of performing vertical scroll display will be described with reference to FIGS. 2, 3, and 4.
In FIG. 3, reference numeral 11 shows the structure of data to be displayed, which has a structure of 8 bits × 8 bits. And
As mentioned above, each bit has a horizontal arrangement direction (row direction).
Are attached with numbers corresponding to 8 bits of 1, 2, ... 8 and in the vertical arrangement direction (column direction) are attached with symbols corresponding to 8 bits of a, b ,. A1, a2, ... h
It is expressed as 8. In addition, each 8 bits in the horizontal arrangement direction (for example, a1, a2, ... A8) is defined as 1 byte, and for ease of explanation, each 1 byte is
As shown in the figure, reference numerals X1, X2, X3, ... X8 are attached.

The data 11 to be displayed is CP
U21 stores the data in the first RAM 12 in 1-byte units. That is, the data 11 to be displayed is laterally scanned and read out, and each 1-byte data is written in the first RAM 12 as X1, X2, ... X8.
After being stored byte by byte, the contents of this first RAM 12 are transferred to the first VRAM 13 by the DMAC 22.

Of the contents of the first VRAM 13, first, with the first byte X1 as the start address, the first byte X1 is followed by X2.
It is read out as X3, ... X8. The content is latched by the latch circuit 24 and then input to the shift register 25.
Display unit 2 as serial data of 1, X2, ... X8
9 is output. In the display unit 29, the serial data is allocated to the bits on the display screen 14 as shown in FIG. 4 (a). In this case, on the display screen 14,
Since all the data of X1, X2, ... X8 are allocated, if the data is, for example, the character "A", the entire character "A" is displayed.

Next, from the first VRAM 13, the second byte X2 is used as a start address, and sequentially from the second byte X2, X3, X4 ,. Are stored in the first VRAM 13. Then, the content is latched by the latch circuit 24, then input to the shift register 25, and output from the shift register 25 as serial data of X2, X3, ... X9. Bits are assigned to the serial data on the display screen 14 as shown in FIG. Therefore, in this case, the portion formed by the byte X1 is displayed as a missing character. That is, if the data is, for example, the character "A", the upper end lateral direction of the character "A" is missing by one line.

Then, from the first VRAM 13,
With the third byte X3 as the start address, this 3
By performing the same operation as the above from the th byte X3 in order, the portion formed by the bytes X1 and X2 is displayed as a missing character. By repeating such an operation, the character displayed on the display screen 14 becomes
Looks like flowing from bottom to top.

Next, the operation for horizontal scroll display will be described with reference to FIGS. 2, 5 and 6. In the case of this horizontal scroll display, the contents stored in the first RAM 12 are converted from the vertical arrangement to the horizontal arrangement and stored in the second RAM 15. This processing is performed in advance by software control before the data 11 to be displayed is displayed on the display screen 14.

As a result, as shown in FIG. 5, the contents of the second RAM 15 are such that each 8 bits in the vertical arrangement direction stored in the first RAM 12 are sequentially stored as 8 bits in the horizontal arrangement from the top. It becomes a state. In other words, each of the 8 rows in the vertical arrangement direction stored in the first RAM 12
If the bits are eight bytes Y1 to Y8, the eight bytes Y1 to Y8 are stored in order from the top, and the first byte Y1 is a1, b1, c.
, ... h1 bits, and the second byte Y2 is composed of a2, b2, c2, ... h2 bits,
.. The eighth byte Y8 is composed of bits a8, b8, c8, ... h8.

The contents of the second RAM 15 are
It is transferred to the second VRAM 16 by the DMAC 22.
Therefore, the contents of the second VRAM 16 are such that each bit forming the data 11 to be displayed is vertically read and stored in 1-byte units. That is,
In this case, eight bytes Y1 to Y8 are stored in order from the top.

Next, the contents of the second VRAM 16 are initially designated by the count signal from the display counter 26 as the start address of the byte Y1.
The ⅛ selector 28 reads bits at a rate of once every 8 bits, such as a1 bits first, a2 bits next, and a3 bits next, and is output as serial data. That is, from the 1/8 selector 28, a1, a2, ... A8, b1, b2 ,.
Serial data such as 8, ..., H1, h2, ... H8 is output. This serial data is given to the selector 27 and sent to the display unit 29 by the switching signal from the register 23.

The display unit 29 allocates the sent serial data to a predetermined position on the display screen 14 and displays it. In this case, on the display screen 14, as shown in FIG. 6A, the first line is a1, a2, ...
1, b2, ... b8, ..., 8th line is h1, h2
.. is assigned such as h8, and characters such as these bits are displayed. If the data to be displayed is, for example, the character "A",
The entire "A" is displayed.

Then, the byte of Y2 is designated as the start address, and by the 1/8 selector 28, first a2 bits, next a3 bits, then a4 bits, once every 8 bits. The bits are read and output as serial data. In other words, this 1
From the / 8 selector 28, a2, a3, ...
2, b3, ... b9, ..., h2, h3, ... h
Serial data such as 9 is output.

The display unit 29 allocates the sent serial data to a predetermined position on the display screen 14 and displays it. In this case, on the display screen 14, as shown in FIG. 6B, the first line is a2, a3, ...
2, b3, ... b9, ..., 8th line is h2, h3
.. is assigned such as h9, and characters such as these bits are displayed. Therefore, in this case, one byte Y1 (a1 bit, b1 bit, ... h1 bit) for one column in the vertical direction at the left end in FIG. 6A is missing. As a result, if the displayed character is “A”, the left end of this “A” is displayed as being vertically missing by one line.

In this way, data is sequentially read from the second VRAM 16, and bits are formed at a rate of once every 8 bits by the ⅛ selector 28 starting from each bit constituting the byte which is the read start address. The character displayed on the display screen 14 by taking out and sending it as serial data to the display unit 29 is as follows.
It is displayed as if flowing from right to left.

As described above, according to this embodiment, the flow display in the hardware configuration in which the data to be displayed is horizontally scanned every 8 bits and read out to display on the display screen 14 is displayed. When horizontal scroll display is performed in the control method, the arrangement of each bit that constitutes the display data can be changed vertically / vertically by software control.
The data is laterally converted and stored in the VRAM, and the contents of the VRAM are sent to the display unit by hardware control.

As described above, the software process of rearranging the bits is not directly related to the quality of the fluidized display (such as the smoothness and speed of the fluidized flow), that is, it is performed before the display, and is directly related to the quality of the fluidized display. By performing the data transfer processing from the related VRAM to the display unit by hardware control, it is possible to minimize the hardware configuration and to perform high-quality vertical and horizontal flow display.

[0043]

According to the present invention, the data to be displayed is horizontally scanned every 8 bits and read out in the horizontal direction, so that the data is displayed on the display screen 14 in a fluidized manner. In the display control method, the horizontal scroll display as well as the vertical scroll display can be freely performed without affecting the quality of the flow display such as smoothness and speed of the flow display and without complicating the hardware configuration. Is possible.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of vertical scroll display in the embodiment.

FIG. 4 is a diagram showing an example of bit allocation on a display screen in vertical scroll display.

FIG. 5 is a diagram for explaining the operation of horizontal scroll display in the embodiment.

FIG. 6 is a diagram showing an example of bit allocation on a display screen in horizontal scroll display.

FIG. 7 is a diagram illustrating a conventional vertical scroll display method.

[Explanation of symbols]

 12 ... 1st RAM 13 ... 1st VRAM 14 ... Display screen 15 ... 2nd RAM 16 ... 2nd VRAM 28 ... 1/8 selector

Claims (4)

[Claims] 1. A data (11) to be displayed, which is arranged in a matrix of bits, is read by scanning in the row direction, and the read bits are first read in 1-byte units in the row direction.
In the first storage means (1)
The contents stored in 2) are stored in the first screen information storage means (13).
To the first screen information storage means (13) by designating a read start address set in advance.
The information on a 1-byte unit read from the beginning is read, and the information on each subsequent byte is sequentially read and displayed on the display screen (14).
After displaying the above, the read start address designation is moved to the next, and the information of the 1-byte unit designated by this is read first, and the information of each subsequent byte is read and displayed on the display screen (14). In the fluidized display control method in which information is fluidly displayed on the display screen (14) by repeating, the row direction 1 stored in the first storage means (12) is
The bit information for each byte unit is the data (1
The row / column conversion is performed so that each byte unit of 1) in the column direction is obtained, and the contents of the row / column conversion are stored in the second storage means (15).
After being stored in the second storage means (15), the contents stored in the second storage means (15) are transferred to the second screen information storage means (16) and set in advance from the second screen information storage means (16). The bits that form the bytes designated by the specified read start address are read out as the serial data of the row of bits of the data (11) to be displayed, and the serial data is extracted. After allocating to a predetermined position on the display screen (14) for display, the read start address designation is moved to the next designated line, and the designated byte is formed at the head to constitute each subsequent byte. The bits are taken out as serial data of a row of bits in the data (11) to be displayed, and the serial data is displayed on the display screen (14).
A flow display control method characterized in that it is possible to flow information in a horizontal direction on the display screen (14) by repeating the operation of allocating and displaying the predetermined position above. 2. The bit information of the first storage means (12) for storing the bits read by scanning the data to be displayed (11) in the row direction is displayed. As means for performing row / column conversion and rearrangement so that the data (11) should be arranged in 1-byte units in the column direction,
2. The fluidized display control method according to claim 1, wherein control by software is used. 3. A means for extracting bits constituting each byte after the byte designated by the read start address designation as serial data of a row of bits of data (11) to be displayed. Is
The flow display control method according to claim 1, wherein the flow display control method is performed using hardware control. 4. Hardware for taking out bits constituting each byte after the byte designated by the designation of the read start address as serial data of a row of bits of the data (11) to be displayed. As a means, the 1/8 selector is used, and the operation of extracting the bits once in eight bits is performed starting from each bit constituting the byte designated by the read start address designation. Flow display control method according to item 1