JPH0628293B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0628293B2 JPH0628293B2 JP61207111A JP20711186A JPH0628293B2 JP H0628293 B2 JPH0628293 B2 JP H0628293B2 JP 61207111 A JP61207111 A JP 61207111A JP 20711186 A JP20711186 A JP 20711186A JP H0628293 B2 JPH0628293 B2 JP H0628293B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- bipolar transistor
- oxide film
- emitter
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に、ＭＯＳ ＦＥＴとバ
イポーラトランジスタとを同一基板上に形成する半導体
装置の製造方法に関するものである。The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a MOS FET and a bipolar transistor are formed on the same substrate.
従来の横型ＮＰＮバイポーラトランジスタとＰチャンネ
ルＭＯＳ ＦＥＴとを同一基板上に形成した半導体装置
の構造の一例を第４図に示す。FIG. 4 shows an example of the structure of a conventional semiconductor device in which a lateral NPN bipolar transistor and a P-channel MOS FET are formed on the same substrate.
Ｐ型基板１の主表面にＰチャンネルＭＯＳ ＦＥＴ１３
とＮＰＮバイポーラトランジスタ１４とが形成されてい
る。これらの素子間には素子分離用の選択酸化膜２を有
している。ＰチャンネルＭＯＳ ＦＥＴ１３はＮウェル
３に形成されており、ソース・ドレイン領域７とゲート
電極４とを含み、バイポーラトランジスタ１４，Ｎウェ
ル３′に形成されており、ベース領域５とコレクタ電極
導出部８とエミッタ領域６′とエミッタ電極６とを含ん
でいる。A P channel MOS FET 13 is formed on the main surface of the P type substrate 1.
And an NPN bipolar transistor 14 are formed. A selective oxide film 2 for element isolation is provided between these elements. The P-channel MOS FET 13 is formed in the N well 3, includes the source / drain region 7 and the gate electrode 4, is formed in the bipolar transistor 14 and the N well 3 ′, and has the base region 5 and the collector electrode lead portion 8. It includes an emitter region 6'and an emitter electrode 6.
バイポーラトランジスタ１４のベース領域５は通常不純
物濃度１０17〜１０18／cm3で層抵抗は１〜３ＫΩ程度
の高抵抗になる。バイポーラトランジスタの高速化，高
性能化を図るにはこのベース抵抗を出来るだけ低減する
必要がある。一般にバイポーラトランジスタの高速化に
おいて重要なパラメータとして、エミッタ接地カット
オフ周波数Ｔ，ベース抵抗rbb′，接合容量（エ
ミッタ，ベース間容量ＣTE，ベースコレクタ間容量
Ｃcb，コレクタ−サブストレート間容量ＣCS）の３つを
挙げることができる。即ち、アナログ的に高周波特性を
評価する性能指数である最大発振周波数maxに対して
次の関係が成立する。The base region 5 of the bipolar transistor 14 usually has an impurity concentration of 10 17 to 10 18 / cm 3 and has a high layer resistance of about 1 to 3 KΩ. It is necessary to reduce this base resistance as much as possible in order to increase the speed and performance of the bipolar transistor. Generally, important parameters for increasing the speed of a bipolar transistor are grounded emitter cutoff frequency T , base resistance r bb ′, junction capacitance (emitter-base capacitance C TE , base-collector capacitance C cb , collector-substrate capacitance C). CS ) can be mentioned. That is, the following relationship is established with respect to the maximum oscillation frequency max , which is a performance index that evaluates high frequency characteristics in an analog manner.
(1)式から明らかなようにベース抵抗rbb′の低減により
最大発振周波数を改善することができる。またデジタル
回路での高速性の評価として遅延時間tpd が一般に使用
されているが、ベース抵抗rbb′の低減により、この遅
延時間tpd も小さくでき、高速化を図ることができる。
しかし、ベース抵抗を低くするため、エミッタ領域６′
直下のベース領域５の不純物濃度を必要以上に上げる
と、エミッタ注入効率の低下、ベース転送効率の低下、
ベース幅の増加、エミッタ・ベース接合容量の増加等多
くの不具合を生じる。 As is clear from Eq. (1), the maximum oscillation frequency can be improved by reducing the base resistance r bb ′. Further, the delay time t pd is generally used as an evaluation of high speed in a digital circuit, but the reduction of the base resistance r bb ′ also makes it possible to reduce the delay time t pd , thereby achieving higher speed.
However, in order to lower the base resistance, the emitter region 6 '
If the impurity concentration of the base region 5 immediately below is increased more than necessary, the emitter injection efficiency decreases, the base transfer efficiency decreases,
Many problems such as an increase in base width and an increase in emitter-base junction capacitance occur.
本発明は、ＭＯＳ ＦＥＴとバイポーラトランジスタと
が混在する半導体装置に於いて上記欠点を排し、ベース
抵抗を下げ、バイポーラトランジスタの高速化，高性能
化を図るためＭＯＳ ＦＥＴのソース・ドレイン領域と
バイポーラトランジスタのベース領域の一部の高濃度不
純物領域が同一工程で形成され、ＭＯＳ ＦＥＴのソー
ス・ドレイン領域の深さ、及び不純物濃度と上記バイポ
ーラトランジスタのベースの高濃度不純物領域の深さ及
び不純物濃度が略等しいという特徴を有する。The present invention eliminates the above-mentioned drawbacks in a semiconductor device in which a MOS FET and a bipolar transistor coexist, lowers the base resistance, and speeds up and improves the performance of the bipolar transistor. A part of the high-concentration impurity region of the base region of the transistor is formed in the same process, and the depth and impurity concentration of the source / drain region of the MOS FET and the depth and impurity concentration of the high-concentration impurity region of the base of the bipolar transistor Have the characteristic that they are substantially equal.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図に本発明の参考例となる半導体装置の断面構造を
示す。ＰチャンネルＭＯＳ ＦＥＴ１３と高不純物濃度
のベース電極導出部７′を有するＮＰＮバイポーラトラ
ンジスタ１４を同一基板上に形成したBi−CMOS構造の半
導体装置である。ＰチャンネルＭＯＳ ＦＥＴ１３のソ
ース，ドレイン領域７とバイポーラトランジスタ１４の
ベース電極導出部７′との深さ及び不純物濃度を略等し
くしている。他は第４図と同じ構造をしている。FIG. 1 shows a cross-sectional structure of a semiconductor device which is a reference example of the present invention. This is a Bi-CMOS structure semiconductor device in which a P-channel MOS FET 13 and an NPN bipolar transistor 14 having a high-impurity-concentration base electrode lead-out portion 7'are formed on the same substrate. The depth and the impurity concentration of the source / drain region 7 of the P-channel MOS FET 13 and the base electrode lead-out portion 7 ′ of the bipolar transistor 14 are made substantially equal. Others have the same structure as in FIG.
第２図に本発明の半導体装置の製造方法の参考例を示
す。第２図(a)はＰ型基板１内にＮウェル領域３，３′
を形成後、素子分離用の選択酸化膜２，ゲート４，コレ
クタ８を形成しバイポーラトランジスタのベース領域５
をホトレジスト膜１０をマスクにしてイオン注入法で形
成する工程を示している。ボロンイオン１１は３０〜１
０KeVのエネルギーで１×１０13〜１×１０14cm-2の量
を打込む。第２図(b)はエミッタ領域の窓を開けた後、
ヒ素を１０20〜１０21cm-3の濃度にドープした多結晶シ
リコンのエミッタ電極６，６′を形成する工程を示して
いる。第２図(c)はＰチャンネルＭＯＳ ＦＥＴのソー
ス・ドレイン領域７とバイポーラトランジスタのベース
電極導出部７′をホトレジスト膜１０をマスクとしてイ
オン打込み法で形成する工程を示している。ボロンイオ
ン１２は４０〜２０KeVのエネルギーで１×１０16〜１
×１０15cm-2の量を打込む。FIG. 2 shows a reference example of the method for manufacturing a semiconductor device of the present invention. FIG. 2 (a) shows the N well regions 3, 3'in the P type substrate 1.
After forming the element, a selective oxide film 2, a gate 4 and a collector 8 for element isolation are formed to form a base region 5 of a bipolar transistor.
Shows a step of forming the film by ion implantation using the photoresist film 10 as a mask. Boron ion 11 is 30 to 1
An amount of 1 × 10 13 to 1 × 10 14 cm -2 is implanted with an energy of 0 KeV. Fig. 2 (b) shows that after opening the window in the emitter area,
It shows a step of forming emitter electrodes 6, 6'of polycrystalline silicon doped with arsenic at a concentration of 10 20 to 10 21 cm -3 . FIG. 2 (c) shows a step of forming the source / drain regions 7 of the P-channel MOS FET and the base electrode lead-out portion 7'of the bipolar transistor by the ion implantation method using the photoresist film 10 as a mask. Boron ion 12 has an energy of 40 to 20 KeV and 1 × 10 16 to 1
Implant an amount of × 10 15 cm -2 .
第３図に本発明の半導体装置の製造方法の一実施例を示
す。第３図(a)はＰ型基板１内にＮウェル領域３，３′
を形成後、素子分離用の選択酸化膜２，ゲート４，コレ
クタ８，ベース５を形成し、エミッタ電極用のヒ素をド
ープした多結晶シリコン６とＣＶＤ酸化膜９を形成する
工程を示している。エミッタ電極用の多結晶シリコン６
にはヒ素が１０20〜１０21cm-3ドープされており、膜厚
は２０００〜４０００Åである。またＣＶＤ酸化膜９は
１０００〜３０００Åの膜厚に成長する。第３図(b)は
エミッタ電極６を形成する工程を示している。第３図は
ＰチャンネルＭＯＳ ＦＥＴのソース・ドレイン領域７
とバイポーラトランジスタのベース領域７′をホトレジ
スト膜１０をマスクとしてイオン打込み法で形成する工
程を示している。ボロンイオン１２は４０〜２０KeVの
エネルギーで１×１０16〜１×１０15cm-2の量を打込
む。この場合、エミッタ多結晶シリコン電極６上にはＣ
ＶＤ酸化膜９があるのでエミッタ電極に対して自己整合
にベース電極導出部７′を形成することができる。また
自己整合にベース電極導出部７′を形成してもＣＶＤ酸
化膜９がマスクとなり、ボロンイオンがエミッタ多結晶
シリコン電極６中に打込まれるのを防ぐので電極の抵抗
が増加することがない。FIG. 3 shows an embodiment of a method of manufacturing a semiconductor device of the present invention. FIG. 3 (a) shows the N well regions 3, 3'in the P type substrate 1.
After the formation, the selective oxide film 2, the gate 4, the collector 8 and the base 5 for element isolation are formed, and the arsenic-doped polycrystalline silicon 6 for the emitter electrode and the CVD oxide film 9 are formed. . Polycrystalline silicon 6 for emitter electrode
Is doped with arsenic in the range of 10 20 to 10 21 cm −3 and has a film thickness of 2000 to 4000 Å. Further, the CVD oxide film 9 grows to a film thickness of 1000 to 3000 Å. FIG. 3B shows a step of forming the emitter electrode 6. FIG. 3 shows the source / drain region 7 of the P-channel MOS FET.
And the step of forming the base region 7'of the bipolar transistor by the ion implantation method using the photoresist film 10 as a mask. Boron ions 12 implant an amount of 1 × 10 16 to 1 × 10 15 cm -2 with an energy of 40 to 20 KeV. In this case, C is formed on the emitter polycrystalline silicon electrode 6.
Since the VD oxide film 9 is provided, the base electrode lead-out portion 7'can be formed in self-alignment with the emitter electrode. Even if the base electrode lead-out portion 7'is formed in a self-aligned manner, the CVD oxide film 9 serves as a mask to prevent boron ions from being implanted into the emitter polycrystalline silicon electrode 6, so that the resistance of the electrode does not increase. .
以上説明したようにＭＯＳ ＦＥＴとバイポーラトラン
ジスタとが混在する半導体装置においてソース領域の一
部高濃度領域とＭＯＳ ＦＥＴのベース・ドレイン領域
を同一工程で形成することにより工程短縮及びベース抵
抗の低減により、バイポーラトランジスタの高速化，高
性能化を図ることができる。As described above, in the semiconductor device in which the MOS FET and the bipolar transistor coexist, by partially forming the high concentration region of the source region and the base / drain region of the MOS FET in the same process, the process is shortened and the base resistance is reduced. Higher speed and higher performance of bipolar transistors can be achieved.
第１図は本発明の参考例の構造を説明する断面図であ
る。第２図(a)〜(c)は本発明半導体装置の製造方法の参
考例を示す各工程での断面図、第３図(a)〜(c)は本発明
による製造方法の実施例を示す各工程での断面図、第４
図は従来構造を説明する断面図である。 １……Ｐ型基板、２……選択酸化膜、３，３′……Ｎウ
ェル領域、４……ゲート、５……ベース領域、６，６′
……エミッタ、７……ＰチャンネルＭＯＳ ＦＥＴのソ
ースドレイン、７′……ＮＰＮバイポーラトランジスタ
の高不純物濃度ベース電極導出部、８……コレクタ、９
……ＣＶＤ酸化膜、１０……ホトレジストマスク、１１
……ベースボロンイオン、１２……ソース・ドレインボ
ロンイオン、１３……ＰチャンネルＭＯＳ ＦＥＴ、１
４……ＮＰＮバイポーラトランジスタ。FIG. 1 is a sectional view illustrating the structure of a reference example of the present invention. 2 (a) to 2 (c) are cross-sectional views in each step showing a reference example of the method for manufacturing a semiconductor device of the present invention, and FIGS. 3 (a) to 3 (c) are examples of the manufacturing method according to the present invention. Sectional view in each step shown, 4th
The figure is a cross-sectional view illustrating a conventional structure. 1 ... P-type substrate, 2 ... Selective oxide film, 3, 3 '... N well region, 4 ... Gate, 5 ... Base region, 6, 6'
...... Emitter, 7 ...... Source and drain of P-channel MOS FET, 7 '... High impurity concentration base electrode lead-out portion of NPN bipolar transistor, 8 ...... Collector, 9
... CVD oxide film, 10 ... photoresist mask, 11
…… Base boron ion, 12 …… Source / drain boron ion, 13 …… P-channel MOS FET, 1
4 ... NPN bipolar transistor.
Claims (1)
とが混在する半導体装置の製造方法において、前記ＭＯ
Ｓ ＦＥＴのゲート電極を形成したのち、エミッタ不純
物がドープされた多結晶シリコン膜と酸化膜を順次形成
する工程と、前記多結晶シリコン膜と前記酸化膜をパタ
ーンニングして上面が前記酸化膜で覆われたエミッタ電
極を形成する工程と、前記ＭＯＳ ＦＥＴのソース・ド
レイン領域への不純物導入と同時に、前記エミッタ電極
を覆う前記酸化膜をマスクとして、前記バイポーラトラ
ンジスタのベース領域に不純物を導入し前記エミッタ電
極に対して自己整合的にベース電極導出部を形成する工
程とを有することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which a MOS FET and a bipolar transistor are mixed, wherein the MO
After forming the gate electrode of the SFET, a step of sequentially forming a polycrystalline silicon film doped with emitter impurities and an oxide film, and patterning the polycrystalline silicon film and the oxide film so that the upper surface is the oxide film. At the same time as forming the covered emitter electrode and introducing the impurity into the source / drain region of the MOS FET, the impurity is introduced into the base region of the bipolar transistor by using the oxide film covering the emitter electrode as a mask. And a step of forming a base electrode lead-out portion in a self-aligned manner with respect to the emitter electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61207111A JPH0628293B2 (en) | 1986-09-02 | 1986-09-02 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61207111A JPH0628293B2 (en) | 1986-09-02 | 1986-09-02 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6362263A JPS6362263A (en) | 1988-03-18 |
| JPH0628293B2 true JPH0628293B2 (en) | 1994-04-13 |
Family
ID=16534379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61207111A Expired - Fee Related JPH0628293B2 (en) | 1986-09-02 | 1986-09-02 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0628293B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3055781B2 (en) * | 1988-07-12 | 2000-06-26 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
| US5091760A (en) * | 1989-04-14 | 1992-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2787183B2 (en) * | 1993-03-10 | 1998-08-13 | 誠一 北林 | Injection head structure having an injection nozzle |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226850A (en) * | 1985-07-27 | 1987-02-04 | Nippon Gakki Seizo Kk | Manufacture of integrated circuit device |
-
1986
- 1986-09-02 JP JP61207111A patent/JPH0628293B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6362263A (en) | 1988-03-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |