JPH06273493A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid an abnormal rise in temperature of a product LSI by a cooling action with a simple cooling device by suppressing heat generation of a semiconductor chip itself during burn-in test. CONSTITUTION:A bi-polar VLSI has the main face 10 of its chip 1 divided into a plurality of blocks B11,... Bmn. Each block is provided with a burn-in control circuit to join/break power supply lines which connect an external power source and the inner circuit of each block, and the control circuit controls on/off of current to the inner circuit during burn-in test on the basis of temperature signal from a thermosensor provided in every block. This makes burn-in current break automatically during burn-in test before chip temperature rises abnormally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for screening a product LSI, and more particularly to a technique which is particularly effective when applied to an LSI in which a current larger than that in a normal operation is supplied and a burn-in test is performed. The present invention relates to a technique useful for use in electric power bipolar VLSI.

[0002]

2. Description of the Related Art As an aspect of a screening technique for removing defects contained in a product LSI, an LSI immediately after manufacturing is operated for a certain period of time under severe conditions of not less than a rating (operation under high temperature conditions, A burn-in test is known in which an LSI that may cause an initial operation failure is sieved and excluded in advance by applying a high bias). By the way, when the above burn-in test is actually performed, especially when the test is performed under a high bias condition, the LSI generates an abnormal heat, and if this is left as it is, the package may be unraveled or fired.

Therefore, conventionally, when performing a burn-in test on an LSI of high power consumption (several tens of watts) accompanied by high heat generation, a technique for suppressing abnormal heat generation by injecting a cooling gas to the LSI is known. It is proposed by Japanese Patent Application No. 63-295943.

[0004]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, the recent bipolar VL
SI consumes a large amount of power, and in a burn-in test in which a high bias is applied to the LSI, the supplied power is about 100 watts, so the chip temperature rises abnormally. In order to suppress the rise in the chip temperature to a predetermined value (for example, 180 ° C.) or less, it is necessary to cool the chip from the outside of the package by using a cooling device as in the above-mentioned conventional technique. Then,
This cooling requires a high cooling capacity, and therefore a large burn-in cooling device for circulating the cooling medium at high speed must be installed, which increases the cost required for maintenance and inspection of the burn-in device. However, there is a problem that the cost for the burn-in test becomes high, such as a large structure is required to house the device.

The present invention has been made in view of the above circumstances. It is possible to suppress heat generation of a semiconductor chip itself during a burn-in test and to sufficiently avoid abnormal heat generation during a burn-in test by a cooling operation by a simple cooling device. The main object of the present invention is to provide a semiconductor integrated circuit device capable of achieving the above. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the semiconductor integrated circuit device of the present invention,
The main surface of the semiconductor chip is divided into a plurality of blocks, and each block is provided with a power supply control circuit capable of connecting / disconnecting a power supply line for supplying a current from an external power supply to an internal circuit in each block. The power supply control circuit turns on / off the current to the internal circuit based on the temperature signal from the chip temperature detecting means provided for each block under a specific operation condition.

[0007]

In the semiconductor integrated circuit device having the above structure, when the chip temperature abnormally rises in any of the blocks under a specific operating condition such as a burn-in test in which a high bias is applied, the chip temperature detecting means detects it. The power supply control circuit that receives the detection signal shuts off the burn-in current to the internal circuit of the block, so that the chip temperature does not rise above a predetermined value under the specific operating condition, and the average temperature is maintained on the entire surface of the chip. An appropriate burn-in test can be performed with the temperature distribution.

[0008]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view schematically showing a bipolar VLSI chip having a burn-in function according to the present invention. As shown in this figure, in the LSI chip 1, the element region 10 in which the internal circuit is formed has N × M blocks (B ₁₁ , B ₁₂ , B _13, ..., B ₂₁ ,
B ₂₂ , ... Bmn). Further, signal lines L ₁₁ , L ₁₂ , L _13, ..., L ₂₁ , L ₂₂ , ... Lmn for controlling burn-in current on / off are provided for each block. As will be described later, this signal line is provided so as to connect / disconnect the internal circuit in each block and the constant voltage power source (VEE, GND). A control signal (high level signal) for communicating the internal circuit and the constant voltage power supply is constantly output, and a control signal for appropriately connecting / disconnecting the internal circuit and the constant voltage power supply according to the burn-in state during the burn-in test execution. (High level signal or low level signal) is output.

FIG. 2 is an enlarged view of the block shown in FIG. 1 (for example, block B ₁₁ ). As shown in the figure, the block B ₁₁ includes a burn-in control circuit 20 and
A signal line L ₁₁ connected to this is provided. The signal line L ₁₁ is provided independently for each block, and the branch wiring l laid in parallel in the block region at regular intervals.
_1, l ₁ ... and are composed of main lines l ₂ connecting the the branches wiring l _1, l ₁ ... and burn-in control circuit 20. Further, a temperature detector 12 for detecting the chip temperature in this block region is installed at substantially the center of the block B ₁₁ , and the detection signal from the detector 12 is transferred to the burn-in control circuit via the signal line l _3. It will be sent to 20. Then,
The burn-in control circuit 20 sends a command signal for controlling on / off of a current used for burn-in (hereinafter referred to as “burn-in current”) based on the temperature signal from the temperature detector 12 during a burn-in test. It flows through the internal circuit of the block via L ₁₁ . As the temperature detector, a known ring oscillator is formed on the chip and the temperature is detected by detecting the amount of change in the oscillation frequency which changes according to the temperature change of the oscillator, or the internal circuit. A voltage value at a predetermined position is detected, and the degree to which the voltage value changes according to the temperature change is used as a temperature signal. Further, as will be described later in detail, the burn-in control circuit 20 supplies a constant voltage power source (VEE, GN) to the internal circuit regardless of the chip temperature during normal operation.
D).

FIG. 3 is a block diagram showing the internal structure of the burn-in control circuit 20. As shown in this figure,
The burn-in control circuit 20 amplifies the temperature signal input from the temperature detector 12, and based on the temperature signal from the sense amplifier circuit unit 21, the trunk line l ₂ and branch line l of the signal line. _An on / off control circuit section 22 for sending a burn-in command signal to ₁ , l ₁ , ... The sense amplifier circuit section 21 has a register, and the value of this register is set to, for example, "1" during the burn-in test so that the signal from the temperature detector 12 is transmitted, while the normal operation is performed. At times, the value of the register is set to "0" so that the temperature signal from the detector 12 is cut off. Thus, during normal operation, a command signal for supplying a constant voltage power supply to the internal circuit is sent to the current supply / cutoff transistor provided in the internal circuit. The value of the register is switched by, for example, fixing a predetermined terminal provided on the chip to a level indicating a normal operation state.

FIG. 4 is a circuit diagram showing a configuration example of the on / off control circuit section 22 shown in FIG. 3 and an internal circuit of the block connected thereto. ON / OFF control circuit unit 22
Is a buffer unit 22A to which a signal obtained by amplifying the temperature signal from the temperature detector 12 is input, and whether the temperature signal sent via the buffer unit 22A represents a value larger than a predetermined value. Each internal circuit 13a, 1 of the block
An on / off signal generating section 2 for flowing an on / off control signal to the signals 3b ... 13i via a signal line L ₁₁ (l ₂ , l ₁ , l ₁ ...).
2B and. By the operation of the on / off control circuit unit 22 configured as described above, a burn-in current flows from the internal circuits 13a, 13b, ... 13i of the block to the negative constant voltage power supply VEE (not shown) during the burn-in test.
Then, when the temperature signal sent from the sense amplifier circuit section 21 indicates that the temperature exceeds the predetermined temperature, the burn-in current is cut off by the circuit section 22. The on / off control of the burn-in current according to the chip temperature is performed in each block (B ₁₁ , B ₁₂ , B ₁₃ ... Bmn).
Each time it is done independently.

FIG. 5 shows the on / off signal generator 22B.
2 is a circuit diagram showing an example of the configuration of FIG. 1 and an internal circuit of a block connected to it. As shown in this figure, when the temperature signal input to the input terminal IN ₁ of the ON / OFF signal generator 22B indicates a temperature equal to or lower than a predetermined temperature (in this case, IN
From ₁ a high-level signal is input from the constant voltage VEE), the transistor Tr ₁ is turned on, the transistor Tr ₂ is turned off, further transistor Tr ₄ is the voltage level of the output terminal OUT ₁ turned off is negative When the voltage becomes higher than the constant voltage VEE, the switching operation transistors Tr, Tr ... Provided in the internal circuit are turned on, and the logic circuit section 1 in the internal circuit is turned on.
A negative constant voltage VEE is applied to 7a, 17b .... on the other hand,
When the temperature signal indicates a predetermined temperature or higher (at this time, a low level signal equivalent to VEE is input from IN ₁ ), the transistor Tr ₁ is turned off, the transistor Tr ₂ is turned on, and the transistor Tr ₄ is turned on. Then, the voltage level of the output terminal OUT ₁ becomes substantially VEE, the switching operation transistors Tr, Tr ... Are turned off, and the application of the constant voltage VEE to the logic circuit portions 17a, 17b ... In the internal circuit is stopped. It

FIG. 6 shows the ON / OFF signal generator 22 of FIG.
FIG. 9 is a circuit diagram showing another configuration example of the on / off signal generating section 32B used in place of B and an internal circuit connected to it. The on / off signal generating section 32B comprises a transistor Tr ₁₀ and a resistor R ₁₀ , and when the temperature signal sent from the temperature detector 12 via the sense amplifier circuit section 21 indicates a predetermined temperature or lower. (At this time IN
High level signal is input from ₂ ), transistor T
When r ₁₀ is turned on, the voltage level of its output terminal OUT ₂ becomes higher than VEE, the switching operation transistors Tr, Tr ... Provided in the internal circuit are turned on, and the logic circuit parts 17a, 17b ... In the internal circuit are turned on. A negative constant voltage VEE is applied. On the other hand, when the temperature signal is equal to or higher than the predetermined value defined by the resistance value R ₀ (at this time, the low level signal is input from IN ₂ ), the transistor Tr ₁₀ is turned off and the switching operation transistors Tr and Tr are turned on. Are turned off, and the application of the constant voltage VEE to the logic circuit portions 17a, 17b in the internal circuit is stopped.

As described above, for each block B ₁₁ , ...
In the LSI chip 1 provided with the signal lines L ₁₁ , ... For turning on / off the power supply, an ON signal is output from the signal line at the start of the burn-in test performed immediately after manufacturing, which is a great problem. The burn-in current flows into the internal circuit of each block via the power supply lines (LGND, LVEE shown in FIGS. 5 and 6). When the chip temperature exceeds a predetermined temperature (for example, 175.degree. C.), the burn-in control circuit 20 acts to output an OFF signal through the signal line only to the block whose temperature has exceeded the cut-off of the burn-in current. It has become so.
As a result, the chip temperature does not rise above a predetermined temperature in any of the blocks, and the burn-in automatic temperature control is performed. During normal LSI operation other than the burn-in test, the sense amplifier circuit section 21 in the burn-in control circuit 20 shuts off the signal from the detector 12, and
A signal for forcibly turning off the transistor Tr _{1 or} Tr ₁₀ is output, and as a result, a constant voltage VEE smaller than that at the time of burn-in is supplied to the internal circuit on the chip regardless of the chip temperature. Will be applied.

As described above, when the abnormal temperature rise of the LSI is reduced during the burn-in test, even if the cooling device has a lower cooling capacity than the conventional LSI burn-in is performed, the L is reduced.
The SI chip can be maintained at the proper burn-in temperature, and an efficient burn-in test can be performed. As described above, by adjusting the amount of increase in the amount of current flowing in the internal circuit during burn-in with respect to the amount of current during normal operation in the circuit design, the acceleration of aging during burn-in test can be adjusted appropriately. You can Further, by setting the temperature condition (predetermined temperature) that determines the on / off of the burn-in current according to the amount of power consumption of each block during normal operation, regardless of the function of each part of the LSI, The burn-in test can be performed by making the rising temperature uniform. Further, by providing the LSI chip to be tested with the burn-in function having the above-mentioned configuration, the power consumption is 1 W to
A burn-in test of a plurality of types of LSI chips of about 200 W can be performed by a single burn-in device having a simple structure.

FIG. 7 shows a burn-in board 1 on which a packaged product LSI is mounted during the burn-in test.
It is a top view of 00. As shown in this figure, the burn-in board 100 includes a main body 10 on which a plurality of product LSIs are mounted.
1. A power supply terminal unit 1 having a plurality of terminals for supplying a burn-in current from an external power supply (VEE) to each LSI chip mounted on the LSI installation unit 101a of the main body unit 101
It has 02. In the power supply terminal unit 102, as many wirings as power supplies are provided independently in parallel so that the same amount of burn-in current is supplied to each LSI from an external power supply. There is. By the way, in the conventional product LSI, since a large amount of heat is generated during the burn-in test, it is not possible to burn-in a large number of LSIs at one time. However, the LSI of the present embodiment has a burn-in control circuit provided in a chip. Since the amount of heat generated can be suppressed to a predetermined value or less by the function, the burn-in test of a plurality of product LSIs can be performed at one time by using the burn-in substrate 100 having the above configuration.

FIG. 8 is a block diagram showing the structure of the burn-in test apparatus 200. As shown in the figure, the burn-in test apparatus 200 includes a power supply unit 20 for supplying power for burn-in to a burn-in board on which a product LSI is mounted.
1. From a rack unit 202 capable of stacking a plurality of burn-in boards at a time, a temperature adjusting unit 203 for uniformly controlling the atmosphere (temperature) in the rack unit 202, and an operation control unit 204 for controlling the operation of the entire test apparatus 200. Become. The operation control unit 204 is provided with an operation monitoring control function for displaying / recording a safety function of the device, an operation status during a burn-in test, and the like. The rack section 202 has a structure in which the burn-in boards 100 can be vertically stacked or arranged in the horizontal direction in order to improve mounting efficiency. Further, as the temperature adjusting device 203, a device having an appropriate circulation function (the refrigerant used is not particularly limited, and either a gas phase or a liquid phase may be used) is used.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. Similar to the first embodiment, the LSI chip 4 of the second embodiment is a bipolar VLSI, and as shown in FIG. 9, the element region 40 in which the internal circuit is formed is divided into several blocks in a matrix. Similar to the first embodiment, each block is provided with signal lines L ₂ , L ₂ ... Independently. Then, in the second embodiment, the plurality of blocks arranged in the matrix are further divided into groups. (In the illustrated example, a plurality of blocks arranged in a line in the vertical direction constitutes one group G ₁ , G ₂ , G ₃ ... Gm, respectively.) Then, one address is assigned to each group and the group belongs to that group. A signal distribution control block 43 (Bc ₁ , Bc ₂ , Bc ₃ , ...) For distributing a burn-in command signal for permitting execution of burn-in is provided in the burn-in control circuits 42, 42 ... Of each block.

This signal distribution control block 43 (for example, B
c ₁ ) distributes a command signal for permitting the burn-in operation to the burn-in control circuits 42, 42 ... Of each block belonging to the group (G ₁ ) over a predetermined time. The groups for which burn-in is permitted are switched every time a predetermined time elapses. By the operation of the control block 43, the burn-in current sequentially flows at predetermined intervals in each group during the burn-in test, so that the temperature of the chip does not rise temporarily.

FIG. 10 is a block diagram showing the internal structure of the signal distribution control block 43 (Bc) provided in the LSI chip 4 at a predetermined ratio. As shown in this figure, the signal distribution control block 43 includes a power supply current control unit 43.
A and a burn-in command signal generation circuit section 43B, and signal lines l ₄ and l ₄ extending from the burn-in command signal generation circuit section 43B are connected to the burn-in control circuit 42 of each block included in the group. ing. When the burn-in test is being performed, the signal distribution control block 43 functions to cause the burn-in control circuits 42 of the blocks belonging to each group to perform signal lines l ₄ , l ₄ ... A command signal allowing the burn-in current is sent. When the burn-in test is completed and the LSI enters the normal operation state, all distribution control blocks forcefully hold the command signal in the ON state so that the current necessary for the normal operation is supplied to each internal circuit. It has become. Also in the second embodiment, each block is provided with a temperature detector for detecting the temperature of the region, and the burn-in control circuit 42 of each block is based on the temperature signal from the detector. , Whether or not a burn-in current is passed through the internal circuit is determined. In this case, each burn-in control circuit has the same configuration as the circuit used in the first embodiment. When the LSI chip of the second embodiment is used, the temperature rise becomes slower than that of the method of the first embodiment in which a current for burn-in is temporarily applied to the entire chip, and the cooling device for burn-in is further simplified. Thus, the burn-in test can be easily performed. Further, since the burn-in is performed for each group, a large burn-in current can be made to flow with the same voltage value as compared with the method of performing burn-in on the entire surface of the chip, and the aging acceleration property is improved.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, this embodiment shows an example in which the main surface of the semiconductor chip is divided into a matrix, but the dividing method is not limited to this. Further, in the second embodiment, each block is divided into groups, and the burn-in current is simultaneously applied to all the blocks included in one group. However, the burn-in current may be applied to a plurality of blocks belonging to the same group. May be made to flow in order.

In the above description, the case where the invention made by the present inventor is mainly applied to a large-scale bipolar LSI which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be applied to general LSIs with high power consumption.

[0023]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. Heat generation of the LSI chip itself is suppressed during the burn-in test, and abnormal heat generation during the burn-in test can be sufficiently avoided by the cooling operation by the simple cooling device. Also, the power required for the burn-in test can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a bipolar VLSI chip having a burn-in function according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a block B ₁₁ shown in FIG. 1 in an enlarged manner.

FIG. 3 is a burn-in control circuit 2 provided in each block
It is a block diagram which shows the internal structure of 0.

FIG. 4 is a circuit diagram showing a configuration example of an on / off control circuit section 22 in a burn-in control circuit and an internal circuit of the block connected to the on / off control circuit section 22.

FIG. 5 is a circuit diagram showing a configuration example of an on / off signal generation section 22B in an on / off control circuit section and an internal circuit of a block connected thereto.

6 is a circuit diagram showing another configuration example of an on / off signal generation section 32B used in place of the on / off signal generation section 22B of FIG. 5 and an internal circuit connected thereto.

FIG. 7 is a plan view of a burn-in board 100 on which a packaged product LSI is mounted.

FIG. 8 is a block diagram showing a configuration of a burn-in test apparatus 200.

FIG. 9 is an ipolar VL according to the second embodiment in which a plurality of blocks on a chip are divided into groups and burned in.
It is a top view which shows the outline of a SI chip.

FIG. 10 is a block diagram showing an internal structure of a signal distribution control block 43 (Bc) provided in the LSI chip 4 at a predetermined ratio.

[Explanation of symbols]

1 Bipolar VLSI 10 device region 12 temperature detector 13a, 13b, ... internal circuit 17a, 17b, ... the internal logic circuit 20 burn control circuit 22 on / off control circuit unit 22B ON / OFF signal generator unit B _11, B _12, B ₁₃ , Bmn block L ₁₁ , L ₁₂ , L ₁₃ , Lmn signal line VEE, GND constant voltage power supply Tr switching transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/66 T 7630-4M 21/3205 27/04 T 8427-4M

Claims (3)

[Claims] 1. A power supply for dividing a main surface of a semiconductor chip into a plurality of blocks, and connecting / cutting off a power supply line for supplying a current from an external power supply to an internal circuit in each block for each block. A control circuit is provided, and the power supply control circuit turns on / off a current to the internal circuit based on a temperature signal from a chip temperature detection unit provided for each block under a specific operation condition. A characteristic semiconductor integrated circuit device. 2. The plurality of blocks are divided into two or more groups, and the semiconductor chip is provided with the power supply control circuit for each group under a specific operating condition every predetermined period. 2. The semiconductor integrated circuit device according to claim 1, further comprising a distribution control circuit for supplying a current from an external power supply to the internal circuits of the blocks belonging to the group. 3. The power supply control circuit comprises a transistor interposed on the power supply line, and an on / off control circuit section for controlling on / off of the transistor. Item 3. The semiconductor integrated circuit device according to Item 1 or 2.