JPH06259581A - Parallel computer - Google Patents

Abstract

PURPOSE:To accelerate an arithmetic operation by providing an internal register file consisting of plural registers and a pointer register to designate the register of the internal register file at each processor element(PE). CONSTITUTION:The internal register 35 provided at each of the PEs 4-11, 4-21 to 4-23 is constituted of the plural registers, and stores data for the arithmetic operation. The pointer register 30 is to designate the register of the internal register file 35, and the content of the pointer register 30 is designated by an instruction, and the content of memory and that of the instruction are stored in it. By employing such constitution, it is possible to change the content of the pointer register 30 even when the same instruction is issued. therefore, to make access the different addresses of the internal register file 35 and to maintain the degree of freedom of a program. Also, data with arbitrary address in the memory can be accessed by transferring the data from the memory of the PEs 4-11, 4-21 to 4-23 to the internal register file 35 simultaneously comprehensively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer.

[0002]

2. Description of the Related Art With the recent demand for high speed and large capacity computer systems, a large number of processors are provided in parallel,
There is a demand for a technology that realizes high processing capacity and reliability by operating the processing in a distributed manner. For this reason,
A so-called massively parallel computer is provided in which a large number of processor elements (hereinafter abbreviated as PE) having a simple configuration are connected.

In such a massively parallel computer, the PEs are different from the SIMD (single instruction multi data) type in which all PEs process the data given to each PE with the same instruction in the same program. There is a MIMD type (multi-instruction multi-data) that executes instructions.

In such a massively parallel computer, unless the individual computers are miniaturized, the execution time is delayed due to the propagation delay of the signal of the instruction or the data due to the distance between the computers or between the arithmetic circuit and the memory.

Therefore, it is important for realizing a massively parallel computer that each PE is formed on the same physical carrier so as to be close to each other and at the same time reduce the number of signal terminals. Here, the same physical carrier refers to, for example, the same semiconductor chip or wafer and the same printed wiring board.

Therefore, SI for executing the same instruction in each PE
In the case of the MD type, it is possible to reduce the number of signal terminals by making the signal line for supplying the command common, and it becomes relatively easy to mount them on the same physical carrier. However, since a large number of PEs are integrated, each PE needs to have a simple structure.

On the other hand, in the case of the SIMD type massively parallel computer, each PE is always supplied with the same instruction and must be completed within the same instruction cycle, so that the processing must be changed depending on the data. , A selection command is provided.

FIG. 5 is a block diagram of a conventional SIMD type massively parallel computer. In the figure, reference numeral 1 denotes a control processor, which supplies an instruction and an address of each memory commonly to a plurality of PEs provided in parallel to control the entire massively parallel computer.

Reference numeral 2 is an instruction broadcast signal line, which is a signal line through which the control processor 1 transmits an instruction and a memory address to each PE 4. 3 is a data collection signal line, and each PE
Is a signal line that outputs when responding to the control processor 1.

Reference numeral 4 denotes a PE, which performs arithmetic operations, logical operations, writing / reading with respect to the memory 6, and the like in accordance with an instruction broadcast from the control processor 1. The PE4 is constructed on a plurality of semiconductor wafers, and a massively parallel computer is constructed by using the plurality of semiconductor wafers. Usually, about 10,000 pieces are connected in parallel.

FIG. 6 is a block diagram of a conventional PE. The PE used here basically adopts a simple architecture but also has a function of a selection instruction. In the figure, PE4 is composed of a computing unit 5 and a memory 6.

Reference numeral 5 denotes an arithmetic unit, which includes a control unit 7 and an ALU8.
, A control flag 9, and an output control circuit 13. 6
Is a memory, which is designated by the control unit 7 by the first input address register 10, the second input address register 11, and the output address register 12 and is designated by the first input address register and the second input address register. It is a 3-port memory that reads the contents of the address to be written and writes the data to the address specified by the output address register.

A control unit 7 has first and second input address registers 10 and 11 and an output address register 12, and interprets an instruction from the control processor 1 to calculate an arithmetic logic unit (hereinafter abbreviated as ALU). ) 8, the control flag 9, and the output control circuit 13.

Reference numeral 8 denotes an ALU, which is used to perform a numerical operation and a logical operation on the contents of the first input and the contents of the second input, which are designated by an instruction. A control flag 9 is A
It is a flip-flop that is set or reset by the operation result of LU8 and the control unit 7.

Reference numerals 10 and 11 denote first and second input address registers for designating a read address of the memory 6. An output address register 12 designates a write address of the memory 6.

An output control circuit 13 sends the contents of the PE output to the data collection signal line 3 in response to a command from the control processor 1. An address decoder 14 decodes the outputs of the three address registers and supplies it to the memory, and is integrated with the memory 6.

The operation of the massively parallel computer having such a configuration will be described. The contents of the memory 6 of each PE 4 are written by the control processor 1 by a write circuit (not shown).

A command is given from the control processor 1 to each PE 4 by a command broadcasting signal line. Each PE4 sets the address part of the instruction in three address registers, and
Depending on the type of instruction, the contents of memory 6 and the operation result of ALU8 are set in three address registers and supplied to memory 6. Therefore, even if the instruction from the control processor 1 is the same, the address itself supplied to the actual memory 6 can be different.

As a result, the degree of freedom of the program can be increased and the processing target of the massively parallel computer can be expanded. However, in this method, each PE is connected to each memory 6
Therefore, it is necessary to transmit three addresses to each other, which requires a large number of address signal terminals and wiring. Since the number of processors that can be accommodated in one physical carrier is limited in order to cover the signal terminals and wiring, it has been an obstacle to the realization of a faster computer.

[0020]

In the conventional massively parallel computer, it is necessary to transmit an address from each PE to each memory, and an address signal terminal and wiring are required. Further, since each memory has a different address, decoding is performed separately.

In view of such a point, the present invention makes SI
An object of the present invention is to provide a means capable of reducing the number of address signal terminals and wiring of an MD type massively parallel computer, sharing a decoder of a memory, and not impairing the degree of freedom of programming.

[0022]

The above problems can be solved by a massively parallel computer configured as described below. Figure 1
FIG. 3 is a principle diagram of the present invention.

In a massively parallel computer composed of a plurality of processor elements 4 that perform arithmetic operations according to the same instruction, an internal register file 35 consisting of a plurality of registers for each processor element 4 and the registers of the internal register file 35. And a pointer register 30 for designating.

[0024]

[Function] The internal register file 35 provided for each processor element 4 is composed of a plurality of registers,
Stores data for calculation.

The pointer register 30 designates a register of the internal register file 35. The contents of the pointer register 30 are designated by an instruction, and the contents of the memory 6, the contents of the instruction and the like are stored.

By adopting this configuration, even if the instructions are the same, the contents of the pointer register 30 are changed, so that different addresses of the internal register file 35 can be accessed and the degree of freedom of the program can be maintained. .

Further, by simultaneously transferring data to the internal register file 35 from the memory 6 for each PE, the data at any address of the memory 6 can be accessed.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, by providing a register file inside each PE, it is possible to share an address signal designating a memory address of each PE, reduce address signal terminals and wiring, and share an address decoder. ,
Moreover, the configuration is such that the degree of freedom of the program is not impaired. It will be described below with reference to the drawings.

FIG. 2 is a block diagram of the PE of the embodiment of the present invention. In the figure, reference numeral 35 denotes an internal register file, which is composed of a plurality of registers and stores data for calculation, and uses a 3-port memory. Three
0 is a pointer register and is an internal register file
It specifies 35 registers. In the following, the pointer register 30 specifies the address of the internal register file 35.

Reference numeral 36 denotes an internal register selection circuit, which selects an internal register file by switching between the portion designating the internal register and the pointer register 30 in the instruction received by the control unit 7 of the arithmetic unit 5. Is. Details are shown in FIG. In addition, the same reference numerals as those in FIG. 5 are the same.

FIG. 3 is a block diagram of the internal register selection circuit. The internal register selection circuit 36 is composed of three multiplexers (hereinafter abbreviated as MPX) 37, 38 and 39. Each M
The PX switches the address of the three internal register files specified by the instruction and the contents of the pointer register 30. Three
The addresses of one internal register file are the first read address, the second read address, and the write address, which are distributed from the control processor 1 via the instruction broadcast signal line 2 as the address part of the inter-register operation instruction. Is. In addition, the same reference numerals as those in FIG. 6 are the same.

Here, the length of each address is determined so that the entire capacity of the internal register file can be accessed. If the number of registers is 64, the address length is 6
Bit needed.

The three outputs of the internal register selection circuit 36 are supplied to the internal register file 35. The internal register file 35 is composed of a 3-port memory, and the contents of two addresses can be read in parallel and written into one address. Therefore, two independent outputs can be obtained. These two outputs are 2 for ALU8
One input.

The ALU 8 performs a designated operation on the data of the internal register file 35 designated by the first read address and the data of the internal register file 35 designated by the second read address in accordance with a command from the control unit. It is written as the data of the internal register file 35 specified by the write address.

FIG. 4 is a block diagram of a massively parallel computer according to an embodiment of the present invention. In the figure, 21 is a PE chip,
It is a semiconductor chip equipped with multiple PE4. The command broadcast signal line 2, the data collection signal line 3 and the like are commonly provided for a plurality of PEs 4 to save terminals. Reference numeral 22 denotes a memory chip, which is a semiconductor chip having an address decoder 24 shared with a plurality of memories 6. The address broadcast signal line from the control processor 1 enters a shared address decoder 24 and its output is shared by each memory 6. Therefore, the memory chip 22 is a multi-bit memory such as 16 bits of 4 megabytes.

The operation of the massively parallel computer having such a configuration will be described. The contents of the memory 6 of each PE are written by the control processor 1 by a write circuit (not shown).

A block transfer command is given from the control processor 1 to each PE by a command broadcasting signal line. Each PE writes the data sent from the memory as the data of each internal register file 35.

Thereafter, each PE processes the data in the internal register file 35 in accordance with the instruction broadcast from the control processor 1. At this time, each PE decodes the instruction and sets the first read address, the second read address, and the write address in the three address registers that specify the position of the internal register file 35.

The first read address, the second read address, and the write address are switched to the contents of the pointer register 30 by an instruction. The contents of the internal register file 35 can be indirectly designated by changing the contents of the pointer register 30 according to the data stored in advance in the memory and the result of the processing.

For example, when normalizing the numerical data given to each PE, the contents of the pointer register 30 are set to the uppermost "
If the bit position is set to "1", the instruction broadcast from the control processor 1 is shifted from the position of the internal register file 35 designated by the pointer register 30 to simultaneously normalize the numerical data given to all PEs. Will be able to

As described above, even if the instruction from the control processor 1 is the same, the actual designated address of the internal register file 35 can be different. As a result, the degree of freedom of the program can be increased and the processing target of the massively parallel computer can be expanded.

Further, with such a structure, it is possible to reduce the number of address signal terminals and wirings and share the decoder of the memory. Therefore, a high-performance massively parallel computer can be configured by using the present invention to configure a plurality of PEs on one semiconductor substrate and providing a plurality of such semiconductor substrates.

[0043]

As is apparent from the above description, the present invention has the following remarkable industrial effects.

Since the instructions supplied to each processor are common, the number of terminals can be small and a high degree of integration can be realized. Since the data is stored in the internal register, the number of designated bits of the address is reduced, and inter-register operation instructions can be performed.

Since the calculation can be performed only inside, the wiring length can be shortened and the calculation speed can be improved. Since the operation is performed only by the internal register, when the PE is performing the operation, the operation of writing new data in the memory 6 can be executed in parallel, and the speed can be increased.

Since the internal register can be designated by the register pointer, the degree of freedom of the program is improved. The memory address decoder can be shared, which is advantageous for downsizing.

As a result of the above, it is possible to construct a massively parallel computer capable of high-speed computation.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a PE according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of an internal register selection circuit.

FIG. 4 is a configuration diagram of a massively parallel computer according to the embodiment of this invention.

FIG. 5 is a block diagram of a conventional SIMD type massively parallel computer.

FIG. 6 is a block diagram of a conventional PE

[Explanation of symbols]

1 Control Processor 2 Command Broadcast Signal Line 3 Data Collection Signal Line 4 PE 5 Arithmetic Unit 6 Memory 7 Control Unit 8 ALU 9 Control Flag 10 First Input Address Register 11 Second Input Address Register 12 Output Address Register 13 Output Control Circuit 14 Address Decoder 15 Address broadcast signal line 21 PE chip 22 Memory chip 24 Shared address decoder 30 Pointer register 35 Internal register file 36 Internal register selection circuit 37 to 39 MP
X

Claims (1)

[Claims] 1. A parallel computer comprising a plurality of processor elements (4) which perform arithmetic operations according to the same instruction, and an internal register file (35) comprising a plurality of registers for each processor element (4), Pointer register (30) for specifying the register of the internal register file (35)
A parallel computer characterized by having and.