JPH06252330A - Lead frame for wiring board - Google Patents
Lead frame for wiring boardInfo
- Publication number
- JPH06252330A JPH06252330A JP5032888A JP3288893A JPH06252330A JP H06252330 A JPH06252330 A JP H06252330A JP 5032888 A JP5032888 A JP 5032888A JP 3288893 A JP3288893 A JP 3288893A JP H06252330 A JPH06252330 A JP H06252330A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- wiring board
- leads
- lead
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、所定数の電子回路素子
を搭載した配線基板をリードフレームに取り付けた構造
のリードフレームに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame having a structure in which a wiring board on which a predetermined number of electronic circuit elements are mounted is attached to the lead frame.
【０００２】[0002]
【従来の技術】リードフレームは、ＩＣ、ＬＳＩ等の半
導体装置の内部に設けた各種の回路を形成した集積回路
本体を外部の電気回路に接続するために使用される部材
であり、半導体装置の集積度の高まりとともに、リード
フレームを構成する各リード間の間隔は小さくなってお
り、リードフレームには、極めて高い精度が要求されて
いる。2. Description of the Related Art A lead frame is a member used to connect an integrated circuit body, which has various circuits provided inside a semiconductor device such as an IC or LSI, to an external electric circuit. With the increase in the degree of integration, the intervals between the leads forming the lead frame have become smaller, and the lead frame is required to have extremely high accuracy.
【０００３】図５は、リードフレームの一例を示す図で
ある。リードフレーム１は、ＩＣ、ＬＳＩ等の半導体素
子を取付けるためのダイパッド２と、その周囲に配設さ
れたを行うためのインナーリード３と、インナーリード
と連続し外部回路との結線を行うためのアウターリード
４を備えている。FIG. 5 is a diagram showing an example of a lead frame. The lead frame 1 is a die pad 2 for mounting a semiconductor element such as an IC or an LSI, an inner lead 3 arranged around the die pad 2, and a lead pad 1 for connecting the inner lead to an external circuit. It has an outer lead 4.
【０００４】リードフレームは、通常コバール、４２合
金、銅系合金等の導電性に優れ、かつ強度が大きい金属
板をフォトエッチング法やスタンピング法等により、所
定の形状に加工することにより製造されるものである。The lead frame is usually manufactured by processing a metal plate such as Kovar, 42 alloy, copper alloy, etc., which has excellent conductivity and high strength, into a predetermined shape by a photo etching method, a stamping method or the like. It is a thing.
【０００５】リードフレームを用いた半導体装置を組み
立てる場合、図６に示すようにリードフレームのダイパ
ッド２に半導体素子５を取付けるとともに、半導体素子
５の接続端子部とインナーリード３とを金線等からなる
ボンディングワイヤ６により電気的に接続しており、イ
ンナーリードの接続部分には金や銀の貴金属のめっきを
施して、ワイヤボンディングが確実に行えるようされて
いる。When assembling a semiconductor device using a lead frame, the semiconductor element 5 is attached to the die pad 2 of the lead frame as shown in FIG. 6, and the connection terminal portion of the semiconductor element 5 and the inner lead 3 are made of gold wire or the like. Are electrically connected by a bonding wire 6, and the connection portion of the inner lead is plated with a noble metal such as gold or silver so that wire bonding can be reliably performed.
【０００６】一方、電子機器の小型化、高性能化、さら
には低価格化に向けて、さまざまなモノリシックＩＣが
開発されている。このようなモノリシックＩＣの代表例
として、ＢｉＣＭＯＳ型のＬＳＩが近年特に注目を浴び
ている。ＢｉＣＭＯＳはバイポーラの優れた高速性およ
び駆動能力と、ＣＭＯＳの低消費電力を結合したＡ−Ｄ
ＬＳＩ（アナログ−ディジタル混在ＬＳＩ）向きの魅力
ある特徴を備えている半導体素子であるが、従来から個
別に作られてきた半導体素子を、半導体素子製造プロセ
スでの複合化技術でモノリシックＩＣとして作りあげる
ことはきわめて難しい。また、モノリシックＩＣのため
の製造プロセスの開発にもモノシリックＩＣの開発と同
等の多くの時間と経費を要し、複合化することにより製
造費用が上昇するという大きな問題が生じる。On the other hand, various monolithic ICs have been developed in order to miniaturize electronic devices, improve their performance, and lower their prices. As a representative example of such a monolithic IC, a BiCMOS type LSI has been particularly attracting attention in recent years. BiCMOS is an AD that combines the high speed and driving capability of bipolar with the low power consumption of CMOS.
Although it is a semiconductor element that has attractive features for LSI (analog-digital mixed LSI), it is possible to fabricate individually manufactured semiconductor elements as a monolithic IC by the compounding technology in the semiconductor element manufacturing process. Is extremely difficult. In addition, the development of a manufacturing process for a monolithic IC requires a lot of time and cost equivalent to the development of a monolithic IC, and the compounding causes a big problem that the manufacturing cost increases.
【０００７】さらには、モノリシックＩＣ化が困難と考
えられる半導体素子の組み合わせもあり、必ずしもモノ
リシックＩＣはすべての場合に対応可能なものではなか
った。Further, there are some combinations of semiconductor elements which are considered to be difficult to be made into a monolithic IC, and the monolithic IC is not necessarily applicable to all cases.
【０００８】モノリシックＩＣ化が困難な半導体素子の
製造技術として、従来よりハイブリッドＩＣ（ＨＩＣ）
が用いられている。このハイブリッドＩＣ技術は、モノ
リシックＩＣでは対応することができない領域および製
造条件を克服するものであるが、集積規模の小さいハイ
ブリッドＩＣの製造は、製造価格面では有利ではないの
で部品点数の少ない電子機器でのハイブリッドＩＣ技術
の採用は適していない。A hybrid IC (HIC) has hitherto been used as a manufacturing technique of a semiconductor element which is difficult to be formed into a monolithic IC.
Is used. Although this hybrid IC technology overcomes a region and manufacturing conditions that cannot be handled by a monolithic IC, manufacturing a hybrid IC having a small integration scale is not advantageous in terms of manufacturing cost, and therefore an electronic device having a small number of parts is required. The adoption of hybrid IC technology in is not suitable.
【０００９】そこで、複数の半導体素子等の電子回路素
子をＩＣパッケージ内に搭載することにより、複合化モ
ノリシックＩＣ、あるいはハイブリッドＩＣ技術で実現
が難しい領域をカバーできるという、ＭＣＰ（Ｍｕｌｔ
ｉ Ｃｈｉｐ Ｐａｃｋａｇｅ）技術と呼ばれる新しい
集積化技術が開発されている。このＭＣＰ技術には種々
の方式のものが開発されている。Therefore, by mounting a plurality of electronic circuit elements such as semiconductor elements in an IC package, it is possible to cover an area which is difficult to realize with a composite monolithic IC or hybrid IC technology.
A new integration technology called i Chip Package technology has been developed. Various types of MCP technology have been developed.
【００１０】図７にその一例を示す。図７（Ａ）には平
面図を、図７（Ｂ）には図７（Ａ）のＡ−Ａ線における
断面図を示す。所定数の半導体素子５を配線基板７に搭
載し、その配線基板７をリードフレームのダイパッド２
上に接着している。またＭＣＰ技術の他の例として図８
（Ａ）には、平面図を示し、図８（Ｂ）には、図７
（Ａ）のＢ−Ｂ線で切断した断面図を示すように、リー
ドフレームに基板支持用リード８を設け、その上に半導
体素子５を搭載した配線基板７を接着する方式のもの
や、配線基板７の絶縁層に熱可塑性ポリイミドなどの接
着性のある材料を用い、この熱可塑性ポリイミドを接着
剤としてリードフレーム部材の基板支持用リード８と配
線基板６を接続する方法が提案されており、図３には、
配線基板を基板支持用リードフレームで接続したリード
フレームの一例を示す。リードフレーム１には、配線基
板７を接続する基板支持用リード８が設けられており、
基板支持用リード８は、インナーリード３およびアウタ
ーリード４と接続したダムバー９と一体に形成されてい
る。FIG. 7 shows an example thereof. 7A shows a plan view and FIG. 7B shows a cross-sectional view taken along the line AA of FIG. 7A. A predetermined number of semiconductor elements 5 are mounted on the wiring board 7, and the wiring board 7 is mounted on the die pad 2 of the lead frame.
Glued on top. As another example of MCP technology, FIG.
FIG. 8A shows a plan view and FIG. 8B shows FIG.
As shown in the sectional view taken along the line BB in (A), a lead frame is provided with a substrate supporting lead 8 and a wiring substrate 7 having a semiconductor element 5 mounted thereon is adhered, or a wiring A method has been proposed in which an adhesive material such as thermoplastic polyimide is used for the insulating layer of the substrate 7, and the substrate supporting leads 8 of the lead frame member and the wiring substrate 6 are connected using this thermoplastic polyimide as an adhesive, In Figure 3,
An example of a lead frame in which wiring boards are connected by a board supporting lead frame is shown. The lead frame 1 is provided with a board supporting lead 8 for connecting the wiring board 7,
The substrate supporting lead 8 is formed integrally with the dam bar 9 connected to the inner lead 3 and the outer lead 4.
【００１１】図４は、ＭＣＰによる半導体装置の製造方
法を示す断面図であるが、図４（Ａ）の組立工程におい
て、配線基板７の絶縁層である熱可塑性ポリイミド層１
０を接着剤として、基体が金属板１１の配線基板７を用
いると、図４（Ｂ）に示すようにワイヤボンディング工
程の加熱でリードフレーム部材の基板支持用リード８が
内側に熱膨張し、熱可塑性ポリイミド層１０の加熱によ
る弾性率と接着性の低下により基板支持用リード８の接
着位置にずれが生じ、そして、図４（Ｃ）に示すように
冷却時に接着剤である熱可塑性ポリイミド層の弾性率と
接着性が回復するため組立時の接着位置からずれた状態
で接続される。このため、リードフレーム部材が内側に
引っ張られ、リードフレーム本体にそりが生じ、樹脂封
止後のアウターリードの同一平面性（コプラナリティ）
が悪くなってしまうという問題があった。FIG. 4 is a sectional view showing a method of manufacturing a semiconductor device by MCP. In the assembly process of FIG. 4A, the thermoplastic polyimide layer 1 which is an insulating layer of the wiring board 7 is used.
When the wiring substrate 7 whose base is the metal plate 11 is used with 0 as an adhesive, the substrate supporting leads 8 of the lead frame member are thermally expanded inward by heating in the wire bonding step, as shown in FIG. 4B. Due to the decrease in elastic modulus and adhesiveness of the thermoplastic polyimide layer 10 due to heating, the bonding position of the substrate supporting lead 8 is displaced, and as shown in FIG. 4C, the thermoplastic polyimide layer which is an adhesive agent during cooling. Since the elastic modulus and the adhesiveness of the are restored, they are connected in a state of being displaced from the bonding position at the time of assembly. For this reason, the lead frame member is pulled inward, the lead frame body is warped, and the outer leads after resin sealing have the same planarity (coplanarity).
There was a problem that it got worse.
【００１２】[0012]
【発明が解決しようとする課題】本発明は、電子回路素
子を搭載した配線基板を有するリードフレームにおい
て、配線基板とのワイヤボンディング工程での熱的影響
によるリードフレームのそりを防止し、樹脂封止後のア
ウターリードの同一平面性が良好なリードフレームを得
ることを目的とし、組立が良好な電子回路素子搭載用リ
ードフレームを提供することにある。SUMMARY OF THE INVENTION In a lead frame having a wiring board on which an electronic circuit element is mounted, the present invention prevents warping of the lead frame due to thermal influence in the wire bonding process with the wiring board, and seals with a resin. It is an object of the present invention to provide a lead frame for mounting an electronic circuit element, which is easily assembled, for the purpose of obtaining a lead frame in which the outer leads have a good coplanarity.
【００１３】[0013]
【課題を解決するための手段】本発明は、少なくとも１
個の電子回路素子を搭載する配線基板を配線基板支持用
リードによって、電子回路素子を搭載した配線基板を接
続した配線基板用リードフレームにおいて、配線基板支
持用リードのうちの少なくとも１個はリードフレームと
は、一体に形成されていないリードフレームである。SUMMARY OF THE INVENTION The present invention comprises at least one
In a lead frame for a wiring board, in which a wiring board on which a plurality of electronic circuit elements are mounted is connected to a wiring board supporting leads on a wiring board, at least one of the leads for supporting the wiring board is a lead frame. Is a lead frame that is not integrally formed.
【００１４】本発明のリードフレームは、基板接続用の
ダイパッド部は有さず、配線基板をリードフレームと一
体に構成した配線基板支持用リードで接続しており、配
線基板の四隅を４本の基板支持用リードで支持する場合
には、そのうちの１本の基板支持用リードは、リードフ
レームとは切り離したもので、ワイヤーボンディング等
の熱影響を受けてもリードフレーム本体にソリが発生せ
ず、樹脂封止後のアウターリードの良好な同一平面性を
確保することができる。The lead frame of the present invention does not have a die pad portion for connecting the board, but the wiring board is connected by the wiring board supporting leads integrally formed with the lead frame. The four corners of the wiring board are connected to each other. When supporting with the substrate support leads, one of the substrate support leads is separated from the lead frame, so warping does not occur in the lead frame body even if it is affected by heat such as wire bonding. It is possible to secure good coplanarity of the outer leads after resin sealing.
【００１５】図面を参照して本発明を説明する。図１
は、本発明による配線基板用リードフレームの実施例を
示す平面図である。本発明のリードフレーム１は、銅系
合金、４２材、コバールなどの金属材料から構成されて
おり、インナーリード３とアウターリード４を有し、各
アウターリード４は、ダムバー９によって接合されてい
る。また、リードフレームは基板支持用リード８を有し
ており、リードフレームから切り離された基板支持用リ
ード１２は、リードフレームの金属部材に接合した絶縁
性部材である固定用テープ１３に接着されている。ま
た、各基板支持用リードには、電子回路素子搭載用の配
線基板６が接続されている。The present invention will be described with reference to the drawings. Figure 1
FIG. 3 is a plan view showing an embodiment of a lead frame for a wiring board according to the present invention. The lead frame 1 of the present invention is made of a metal material such as a copper alloy, 42 materials, and Kovar, and has an inner lead 3 and an outer lead 4, and each outer lead 4 is joined by a dam bar 9. . Further, the lead frame has a substrate supporting lead 8, and the substrate supporting lead 12 separated from the lead frame is adhered to a fixing tape 13 which is an insulating member joined to a metal member of the lead frame. There is. A wiring board 6 for mounting an electronic circuit element is connected to each board supporting lead.
【００１６】図２は、本発明による配線基板用リードフ
レームの製造工程を説明する図である。FIG. 2 is a diagram for explaining the manufacturing process of the lead frame for a wiring board according to the present invention.
【００１７】図２（ａ）のように、４本の基板支持用リ
ード８を有するダイパッドを有しないリードフレーム１
をフォトエッチング等の方法により形成し、インナーリ
ード３に銀めっき等を施す。次に図２（ｂ）のように、
インナーリード３および基板支持用リード８に固定用テ
ープ１３を熱圧着等により接合する。次に図２（ｃ）の
ように、電子回路素子を搭載し回路を形成した配線基板
を接続する。配線基板には、任意のものを使用すること
が可能であるが、とくに熱可塑性ポリイミド樹脂等の熱
的に接合可能な材料を絶縁層として、積層した銅箔等に
回路を形成したものが好ましい。回路を形成した電子回
路素子搭載用の配線基板６を基板支持用リード８の裏面
と配線基板６の回路パターン側に露出した絶縁層とを熱
圧着して接合する。次に図２（ｄ）のように、４本の基
板支持用リード８のうちの少なくとも１本をダムバー９
からスタンピング法等により打ち抜き、切り離された基
板支持用リード１３を形成する。As shown in FIG. 2A, a lead frame 1 having four substrate supporting leads 8 and having no die pad.
Are formed by a method such as photoetching, and the inner leads 3 are plated with silver or the like. Next, as shown in FIG.
The fixing tape 13 is bonded to the inner lead 3 and the substrate supporting lead 8 by thermocompression bonding or the like. Next, as shown in FIG. 2C, a wiring board on which an electronic circuit element is mounted and a circuit is formed is connected. As the wiring board, any material can be used, but it is particularly preferable that a circuit is formed on a laminated copper foil or the like by using a thermally bondable material such as thermoplastic polyimide resin as an insulating layer. . The wiring board 6 for mounting an electronic circuit element on which a circuit is formed is bonded by thermocompression bonding the back surface of the board supporting lead 8 and the insulating layer exposed on the circuit pattern side of the wiring board 6. Next, as shown in FIG. 2D, at least one of the four substrate supporting leads 8 is attached to the dam bar 9
Then, the substrate supporting leads 13 are punched out by a stamping method or the like to form the separated substrate supporting leads 13.
【００１８】このようにして得られた配線基板用リード
フレームでは、４隅がすべて基板支持用リードにより配
線基板に接続されていないため、ワイヤボンディング等
の熱影響を受けてもリードフレーム部材を内側に引っ張
る力が緩和され、リードフレーム本体にそりが発生せ
ず、樹脂封止後のアウターリードの同一平面性を良好に
保つことができる。In the lead frame for a wiring board thus obtained, since the four corners are not connected to the wiring board by the leads for supporting the board, even if the lead frame member is exposed to heat due to wire bonding, etc. The pulling force is relaxed, the warp does not occur in the lead frame body, and the outer flatness of the outer lead after resin sealing can be kept good.
【００１９】[0019]
【作用】少なくとも１個の電子回路素子を搭載する配線
基板を基板支持用リードを有するダイパッドを有しない
リードフレームに接続する配線基板用リードフレームに
おいて、配線基板を接続する４本の基板支持用リードの
うちの１本は、リードフレーム本体から切り離されてい
るので、ワイヤボンディング等の熱影響を受けてもリー
ドフレーム本体にそりが発生せず、樹脂封止後のアウタ
ーリードは同一平面性を保持しており、プリント配線基
板等への組立が良好である。In a lead frame for a wiring board, in which a wiring board having at least one electronic circuit element mounted thereon is connected to a lead frame having a board supporting lead and not having a die pad, four board supporting leads for connecting the wiring boards are provided. Since one of them is separated from the lead frame body, warpage does not occur in the lead frame body even when it is affected by heat such as wire bonding, and the outer lead after resin sealing maintains the same planarity. Therefore, it can be easily assembled on a printed wiring board or the like.
【００２０】[0020]
【実施例】実施例１ 厚さ０．１５ｍｍのニッケルを４２％含む鉄合金（４２
Ａ）板を通常のフォトエッチング法により４本の基板支
持用リードを有し、ダイパッドを有しないリードフレー
ムを製造した。このリードフレームのインナーリード部
に銀めっきを施し、ポリイミド樹脂の片面には、エポキ
シ系接着剤を塗布した固定用テープ（巴川製紙所 エレ
ファンＣＡＴ）を額縁状に切断し、インナーリードおよ
び基板支持用リードに熱圧着してインナーリードおよび
基板支持用リードを固定をした。Example 1 An iron alloy (42% containing 42% nickel having a thickness of 0.15 mm)
A) A lead frame having four substrate supporting leads and no die pad was manufactured from the plate by a normal photoetching method. The inner lead part of this lead frame is silver-plated, and one side of the polyimide resin is coated with epoxy adhesive and fixed tape (Elephan CAT, Tomoegawa Paper Mill) is cut into a frame shape to support the inner lead and substrate. The inner lead and the substrate supporting lead were fixed by thermocompression bonding to the lead.
【００２１】次に、銅箔（厚さ１８μｍ）／熱可塑性ポ
リイミド（厚さ２０μｍ）／熱硬化性ポリイミド（厚さ
５０μｍ）／熱可塑性ポリイミド（厚さ２０μｍ）／４
２Ａ（厚さ１５０μｍ）を積層した積層基板からなる電
子回路搭載用配線基板の銅箔面に回路を形成し、金めっ
きを施した。次いで、基板支持用リードの裏面と配線基
板の回路パターン側に露出した熱可塑性ポリイミドとを
熱圧着して接合した。Next, copper foil (thickness 18 μm) / thermoplastic polyimide (thickness 20 μm) / thermosetting polyimide (thickness 50 μm) / thermoplastic polyimide (thickness 20 μm) / 4
A circuit was formed on a copper foil surface of a wiring board for mounting an electronic circuit, which was composed of a laminated board in which 2 A (thickness: 150 μm) was laminated, and gold plating was applied. Next, the back surface of the board supporting lead and the thermoplastic polyimide exposed on the circuit pattern side of the wiring board were bonded by thermocompression bonding.
【００２２】次に、４本の基板支持用リードのうちの一
本を金型を用いてスタンピング法によりダムバー付近よ
り打ち抜き、リードフレーム本体から切り離した。この
時、リードフレーム本体から切り離した基板支持用リー
ドは固定テープによって固定されているため位置ずれを
生じることはない。Next, one of the four substrate supporting leads was punched from near the dam bar by a stamping method using a mold and separated from the lead frame body. At this time, since the substrate supporting leads separated from the lead frame body are fixed by the fixing tape, no positional deviation occurs.
【００２３】次いで、リードフレームと配線基板を金線
を使用してワイヤボンディングを行ったところ、基板の
温度は２７０℃に達した。冷却した後のリードフレーム
の形状をワイヤボンディングの前後で比較したところ、
形状の変化はみられなかった。Next, when the lead frame and the wiring board were wire-bonded using a gold wire, the temperature of the board reached 270 ° C. After comparing the shape of the lead frame after cooling before and after wire bonding,
No change in shape was observed.
【００２４】比較例１ ４本の基板支持用リードのうちの１本をリードフレーム
の本体から切断しなかった点を除いて実施例１と同様に
配線基板を接続し、ワイヤボンディングを行ったとこ
ろ、ワイヤボンディングの前後でのアウターリードには
０．６ｍｍのそりが生じた。Comparative Example 1 A wiring board was connected and wire bonded in the same manner as in Example 1 except that one of the four substrate supporting leads was not cut from the main body of the lead frame. A warp of 0.6 mm occurred on the outer leads before and after wire bonding.
【００２５】[0025]
【発明の効果】本発明による半導体素子搭載用の配線基
板を接続したリードフレームによれば、ワイヤボンディ
ング等の熱影響を受けてもリードフレーム本体にそりが
発生せず、樹脂封止後のアウターリードの同一平面性を
確保で、良好なアッセンブリが可能となる。According to the lead frame to which the wiring board for mounting a semiconductor element according to the present invention is connected, warpage does not occur in the lead frame body even when it is affected by heat such as wire bonding, and the outer after resin encapsulation is performed. By ensuring the coplanarity of the leads, good assembly is possible.
【図１】本発明の配線基板用リードフレームの１実施例
の平面図。FIG. 1 is a plan view of an embodiment of a lead frame for a wiring board of the present invention.
【図２】本発明の配線基板用リードフレームの製造工程
を説明する図。FIG. 2 is a diagram illustrating a manufacturing process of a lead frame for a wiring board of the present invention.
【図３】従来の配線基板用のリードフレームを説明する
図。FIG. 3 is a diagram illustrating a conventional lead frame for a wiring board.
【図４】従来の配線基板用リードフレームのそりの発生
を説明する図。FIG. 4 is a diagram illustrating the occurrence of warpage in a conventional lead frame for a wiring board.
【図５】従来のリードフレームの平面図。FIG. 5 is a plan view of a conventional lead frame.
【図６】従来のリードフレームを用いて製造した半導体
装置の要部を示す概略説明図。FIG. 6 is a schematic explanatory view showing a main part of a semiconductor device manufactured using a conventional lead frame.
【図７】ダイパッドを用いたＭＣＰ技術による従来の方
法を示す平面図及び断面図。7A and 7B are a plan view and a cross-sectional view showing a conventional method by the MCP technique using a die pad.
【図８】基板支持用リードを用いたＭＣＰ技術による従
来の方法を示す平面図及び断面図。8A and 8B are a plan view and a cross-sectional view showing a conventional method by an MCP technique using a substrate supporting lead.
１…リードフレーム、２…ダイパッド、３…インナーリ
ード、４…アウターリード、５…半導体素子、６…ボン
ディングワイヤ、７…配線基板、８…基板支持用リー
ド、９…ダムバー、１０…熱可塑性ポリイミド層、１１
…金属板、１２…リードフレームから切り離された基板
支持用リード、１３…固定用テープDESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... Die pad, 3 ... Inner lead, 4 ... Outer lead, 5 ... Semiconductor element, 6 ... Bonding wire, 7 ... Wiring board, 8 ... Board supporting lead, 9 ... Dam bar, 10 ... Thermoplastic polyimide Layer, 11
... Metal plate, 12 ... Substrate supporting leads separated from lead frame, 13 ... Fixing tape
Claims (1)
る配線基板を配線基板支持用リードによって取り付けた
配線基板用リードフレームにおいて、配線基板を支持す
る基板支持用リードのうちの少なくとも１個は、リード
フレームの金属部材に接合した絶縁性部材によって保持
されていることを特徴とする配線基板用リードフレー
ム。1. In a lead frame for a wiring board, in which a wiring board on which at least one electronic circuit element is mounted is attached by a wiring board supporting lead, at least one of the board supporting leads for supporting the wiring board comprises: A lead frame for a wiring board, which is held by an insulating member joined to a metal member of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5032888A JPH06252330A (en) | 1993-02-23 | 1993-02-23 | Lead frame for wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5032888A JPH06252330A (en) | 1993-02-23 | 1993-02-23 | Lead frame for wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06252330A true JPH06252330A (en) | 1994-09-09 |
Family
ID=12371426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5032888A Pending JPH06252330A (en) | 1993-02-23 | 1993-02-23 | Lead frame for wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06252330A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0735582A1 (en) * | 1995-03-31 | 1996-10-02 | STMicroelectronics S.A. | Package for mounting an IC-chip |
| JP2008141222A (en) * | 2008-02-04 | 2008-06-19 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using the same and method of manufacturing the same |
| CN107993942A (en) * | 2017-11-24 | 2018-05-04 | 中山复盛机电有限公司 | The manufacturing process of lead frame |
-
1993
- 1993-02-23 JP JP5032888A patent/JPH06252330A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0735582A1 (en) * | 1995-03-31 | 1996-10-02 | STMicroelectronics S.A. | Package for mounting an IC-chip |
| FR2732509A1 (en) * | 1995-03-31 | 1996-10-04 | Sgs Thomson Microelectronics | BOX FOR MOUNTING AN INTEGRATED CIRCUIT CHIP |
| US6049971A (en) * | 1995-03-31 | 2000-04-18 | Sgs-Thomson Microelectronics S.A. | Casing for integrated circuit chips and method of fabrication |
| JP2008141222A (en) * | 2008-02-04 | 2008-06-19 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using the same and method of manufacturing the same |
| CN107993942A (en) * | 2017-11-24 | 2018-05-04 | 中山复盛机电有限公司 | The manufacturing process of lead frame |
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