JPH06224691A - Resistance circuit and filter circuit using the same - Google Patents

Abstract

PURPOSE:To vary the resistance value on an integrated circuit by a voltage and to use it to automatically vary the time constant of a filter circuit. CONSTITUTION:This resistance circuit is provided with a constant current source Ix controlled by a voltage, a voltage generating circuit which generates a voltage proportional to the current of the constant current circuit by first and second terminals of a three-terminal element, a three-terminal element operated as a MOS diode, and a circuit where three-terminal elements operated in a constant current are connected in series, and the voltage of the voltage generating circuit is supplied to the series connection circuit to vary the impedance at both ends of the series connection circuit. Thus, a large resistance value is obtained in a small element area.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to circuits for generating internal clock signals for integrated circuits.

[0002]

2. Description of the Related Art In recent years, the speed of integrated circuits has increased, and the frequency of the clock signal that is the basis of the operation of the integrated circuits has been increasing year by year. The operating speed of a microprocessor, which is well known as a representative of digital integrated circuits, is 1.
It has been increasing at a rate of 3 to 1.4 times, and it is considered that this trend will continue in the future even if this growth rate slows down a little. At present, what is known as a high-speed microprocessor supplies a clock signal of 12 MHz from the outside, and if the operating speed is improved at the above-mentioned annual rate, the required clock frequency will be 44 MHz after 5 years. ~ 64 MH
The frequency becomes extremely high as z. That is, in order to further speed up the integrated circuit in the future, it is necessary to generate a clock signal having a very high frequency as described above.

[0003]

When such a high-frequency signal is generated in an internal oscillator circuit using a crystal oscillator as in the conventional case, the ability to drive a large stray capacitance or the like of an external pin at high speed is required. There is difficulty in configuring the oscillator circuit that it has. Similarly, when the clock signal generated by an external circuit is supplied to the integrated circuit, the capacitance of the external pin and the stray capacitance of the wiring must be driven at high speed. Especially in applications where a large number of integrated circuits are used,
1 clock generator circuit for low cost system
It is desirable to supply a clock signal to each integrated circuit as one, and when operating each integrated circuit in synchronization,
The number of clock generation circuits is limited to one. Like this one
When supplying clock signals from one clock generation circuit to many integrated circuits, the stray capacitance of the external pins of each integrated circuit and the stray capacitance of the wiring become very large, and a stable high-frequency clock signal is supplied. Difficult to do.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems by applying an integrated circuit to which an external clock signal is applied at a low frequency while keeping an internal clock signal of a high frequency synchronized with this signal. It provides a circuit that can be generated.

The frequency of the clock signal supplied from the outside is not always constant, and various frequencies may be added depending on the application. The present invention provides a circuit adaptable to such a case. To do.

[0006]

According to the present invention, the internal clock circuit of the integrated circuit has a phase-locked loop circuit (hereinafter abbreviated as "PLL circuit") so that a high-frequency internal clock signal synchronized with an externally supplied clock signal can be generated. It is possible to generate. Further, by varying the specific number of filters in the PLL circuit according to external clock signals of various frequencies, it is possible to operate in a wide range of external clock frequencies.

[0007]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1A shows a frequency doubler circuit A (12).
It is a figure showing the composition of integrated circuit 11 which has inside.
FIG. 1B is a conceptual diagram showing the waveform of the signal in FIG. In FIG. 1A, the integrated circuit 11 is
It has a frequency doubler circuit 12 and a circuit 14 which operates by an internal clock signal S obtained by this frequency doubler circuit. A reference clock signal R is externally supplied to the frequency doubler circuit A.
(Frequency f _R ) is added or integrated circuit 1
The reference clock signal R '(frequency f _R ) obtained by the oscillator circuit OSC (13) in 1 is added. The frequency doubler circuit A receives these signals and generates a high frequency signal S (frequency nf _R : n is an integer) synchronized with these signals. Further, the input of the frequency doubler circuit A and N are external inputs for setting the frequency doubler n. With this type of circuit,
Even if the frequency of the internal clock signal required in the internal circuit B is high, the frequency of the signal applied to the external pin of the integrated circuit can be lowered, and it will be easy to improve the operating speed of the integrated circuit in the future. It has the advantage of being adaptable.

The embodiment shown in FIG. 2 is a frequency divider circuit A shown in FIG.
2 shows a circuit system for realizing the above. This circuit system has a circuit configuration well known as a PLL circuit. In FIG. 2, 21 is a frequency divider circuit (CNTR1), 22 is a phase comparison circuit (PC), 23 is a charge pump circuit (CP), and 2
Reference numeral 4 is a low pass filter (LPF), 25 is a voltage controlled oscillator (VCO), and 26 is a frequency divider (CNTR2). The signals M and N input to the frequency dividing circuit are signals for setting the frequency dividing number. In addition, the frequency divider circuit CNTR1
Sets the number of stages according to the application, but it may not be necessary.

In the circuit of this embodiment, in the stable state,
1 / M of external reference clock signal R (frequency f _R )
Signal of frequency R _M and output signal S of VCO (frequency f _S )
The signals S _N having a frequency of 1 / N are equal, and the phases are also synchronized. Therefore,

[0011]

[Equation 1]

A VCO output signal S having a frequency of is obtained. Here, by setting the values of M and N that satisfy the relationship of N / M> 1, the frequency of the output signal of the VCO can be made higher than the frequency of the reference clock signal.
Similarly, a signal S'taken out from the middle of the frequency dividing circuit CNTR2.
(Frequency f _S / N ') can also be higher in frequency than the reference clock signal. By using these signals S and S'as internal clock signals, the frequency doubler circuit shown in FIG. 1 can be realized.

The features of the case where the PLL circuit of this embodiment is used as the frequency dividing circuit will be described below.

First, the degree of freedom in setting the frequency proportionality between the external reference clock signal and the internal clock signal is large. This means that the high frequency of the internal clock of the integrated circuit can be dealt with by only changing the setting of the frequency division number N of the frequency division circuit CNTR2 without changing the reference clock frequency from the outside. I mean.

The second point is that when a PLL circuit is used,
The phase of the external reference clock signal and the internal clock signal can be easily synchronized. As a frequency divider circuit, P
Circuits other than the LL circuit are possible, but it is not easy to synchronize the phases.

The features of the embodiment shown in FIG. 2 as a frequency doubler circuit have been described above, but they also have problems. If the frequency of the reference clock signal is determined, it is L
It is possible to determine the time constant of the PF, but it is impossible to uniquely determine the time constant of the LPF in the case where the reference clock signal is to be operated using a wide range of frequencies. In other words, the time constant of LPF is
Since it is a factor that determines the damping factor, lock-up time, etc. of the entire PLL circuit, it is necessary to select an optimum value according to the frequency entering the phase comparison circuit. Therefore, when the frequency of the reference clock signal is changed over a wide range, it is necessary to change the time constant of the LPF accordingly. From the standpoint of manufacturing an integrated circuit, there is often a demand for setting the frequency of the reference clock signal in a wide range from the standpoint of manufacturing the integrated circuit so that the function check is performed at a reduced speed during the test of the integrated circuit. Also, from the standpoint of using an integrated circuit, it is often the case that a test is performed at a low speed for checking software such as a micro program in the integrated circuit. Further, due to the convenience of the system, it is often the case that a reference clock signal of an arbitrary frequency cannot be generated and the reference clock signal of low frequency is used.

Even in the case of the embodiment shown in FIG. 2, it is partially applicable to such various uses.

First, by increasing the number of frequency dividing stages of the first reference clock signal frequency dividing circuit CNTR1 and changing the setting of the frequency dividing number M for a wide range of reference clock signals,
There is a method of keeping the frequency entering the phase comparison circuit PC constant. However, in this case, since the input signal frequency of the phase comparison circuit must be set to a low frequency in advance, the time constant of the LPF must be set to a large value. As is well known, in an integrated circuit, obtaining a large time constant causes an increase in device area and is difficult. Further, increasing the number of stages of the frequency dividing circuit for the reference clock signal also increases the circuit area, which is not preferable.

As another method, an element for determining the time constant of the LPF is externally attached and the element is exchanged according to the operating frequency, or the LPF is externally controlled by using a voltage (current) control variable time constant circuit. It is also possible to set the time constant from. However, in this case, the number of pins of the integrated circuit increases because an element is externally attached or an external pin must be prepared for a control terminal.

As described above, the above method has a restriction that the setting must be changed for each used frequency.

FIG. 3 shows an embodiment showing a circuit system which can solve the above problems. In FIG. 3, 31 is a frequency divider circuit (CNTR1), 32 is a phase comparison circuit (PC), 33
Is a charge pump circuit (CP), 34 is a low-pass filter (LPF), 35 is a voltage controlled oscillator (VCO), 3
Reference numeral 6 is a frequency dividing circuit (CNTR2), and 37 is a frequency-voltage conversion circuit (FVC). 31-36 in this circuit system
Is the same circuit block as the embodiment shown in FIG.

In this embodiment, in order to solve the problems described in the embodiment of FIG. 2, a frequency-voltage conversion circuit is provided, and L
The PF is composed of a voltage (current) control variable time constant circuit. In the operation of this embodiment, the reference clock signal is input to the frequency-voltage conversion circuit, the signal voltage Vc obtained by converting the frequency into a voltage is obtained, and this is applied to the voltage control input of the LPF. As a result, it becomes possible to automatically control the time constant of the LPF to an optimum value according to the frequency of the reference clock signal.

The features of the above embodiment will be described below. Since this embodiment has all the constituent requirements of the embodiment shown in FIG. 2, the features described in the embodiment of FIG. 2 become the features of this embodiment as they are. Furthermore, the problems described in the embodiment of FIG. 2 can be solved, and external parts are unnecessary. An external pin for setting the frequency division number of the reference clock signal or an external pin for controlling the time constant of the LPF is also unnecessary. It has a great advantage that it can be automatically adapted to various reference clock signals. From the above, if the circuit system of this embodiment is used, the operation speed is reduced during the test of the integrated circuit to perform the function check,
It can be easily applied to applications such as a micro program in an integrated circuit that is used at a slow speed when checking lift wear, or applications where a high-frequency reference signal cannot be obtained due to system limitations. Has the advantage that

FIG. 4A is a diagram showing an embodiment of a concrete circuit for realizing the VCO circuit in the embodiment shown in FIGS. 2 and 3. FIG. 4B is an example of a ring oscillator using a conventional CMOS inverter.

In FIG. 4A, reference numeral 41 is a voltage / current conversion circuit for receiving the output voltage from the LPF and converting it into a current.
Q ₄₁ , Q ₄₂ , and Q _{43 form} a current mirror circuit. Q _44, Q ₄₇ receives the potential from the current mirror circuit, a transistor for controlling the charging and discharging current flowing through the CMOS inverter formed by Q _45, Q _46. The oscillating circuit consists of an inverter of Q ₄₅ , Q ₄₆ and Q ₄₄ , Q
It is composed of a ring oscillator in which circuits of ₄₇ transistors are connected in odd stages. The output signal S (frequency f _S ) is taken out via the 42 output buffer.

In the VCO circuit of this embodiment, the voltage / current circuit receives the input voltage and converts it into a current, and the current proportional to this current controls the oscillation frequency of the ring oscillator circuit by the inverter. Hereinafter, the operation of the oscillator circuit portion of this embodiment will be described in comparison with the conventional example.

FIG. 4B shows a conventional VCO circuit using a ring oscillator with a CMOS inverter.
In FIG. 4B, the delay time τ per inverter stage
Is

[0028]

(2) τ = CV / _ID ... (2) Where C is the capacitance value at the output end of the inverter,
V is a control voltage, which supplies the power supply voltage of the inverter. I
_D is the drain current when the transistor is on. This _ID is proportional to the square of the gate voltage, and the gate voltage is CM
Since OS swings from the ground potential to the power supply voltage V, I _D
Is eventually proportional to the square of the power supply voltage V. Therefore, in the delay time,

[0029]

[Equation 3] τ∝C / V (3) In the ring oscillator in which the inverters are connected in n stages (odd number), the oscillation frequency f _S is

[0030]

[Equation 4]

It becomes As described above, in the circuit of FIG. 4B, the oscillation frequency f _S is changed to V by changing the control voltage V.
Can be changed in proportion to.

However, in the conventional example as shown in FIG. 4B, the change of the control voltage V directly changes the theoretical amplitude of the ring oscillator circuit, and the output is taken out from the ring oscillator circuit. It becomes difficult to drive the circuit.

On the other hand, the circuit of the embodiment of the present invention shown in FIG. 4A is characterized in that the maximum logical amplitude can be obtained without changing the logical amplitude even if the oscillation frequency is changed. .

Since the inverter of the oscillation circuit section of this embodiment has current control transistors on the power supply side and the ground side, the charge / discharge amount of the output terminal capacitance is determined by this current value I ₀ .
The delay time τ per inverter in the circuit of this embodiment is

[0035]

[Equation 5]

It becomes Here, V _CC is the power supply voltage.
Therefore, the oscillation frequency f _S of the ring oscillator in which this inverter is connected in n stages (odd number) is

[0037]

[Equation 6]

[0038] In this way, the circuit of this embodiment is
The oscillation frequency f _S can be changed in proportion to the control current I ₀ . Further, in the circuit of the present embodiment, since the power supply voltage of the inverter is not changed, the logic amplitude is constant and the maximum amplitude from the ground potential to the power supply voltage V _CC is always obtained.

In addition to the above description, as the VCO circuit of FIGS. 2 and 3, a sawtooth wave oscillation circuit, an integrated emitter oscillation circuit (source coupled oscillation circuit in the case of MOS), various oscillation circuits by an IIL circuit, etc. are used. It goes without saying that you can do it.

Next, FIG. 5 shows an embodiment of a concrete circuit for realizing the LPF in the embodiments shown in FIGS. Figure 5
Is an example of an LPF using a passive element (resistor R and capacitor C) that is well known in the past. Since it is of course possible to realize an LPF using such a passive element in an integrated circuit, it can be used as the LPF of the embodiments shown in FIGS.

However, when an LPF having a large time constant is to be realized in an integrated circuit, its element value,
The device area becomes large and it is difficult to realize. In addition, as shown in FIGS. 2 and 3, it cannot be used for applications in which the time constant of the LPF must be variable by the control voltage V _C.

The circuit shown in FIG. 6 (a) is an embodiment of a voltage controlled variable resistance circuit which solves the problems of the conventional circuit and enables the construction of an LPF having a variable time constant.

In FIG. 6A, the variable resistor is composed of a series circuit of transistors Q ₆₁ and Q _{62, and} a circuit for controlling the resistance value is a transistor Q _{X having a} polarity opposite to that of Q ₆₁ and Q _62.
And a voltage-controlled constant current source I _X. V _C is an input voltage for controlling the voltage controlled constant current source I _X.

The operation of this embodiment will be described below.

First, in the circuit of FIG. 6A, it is assumed that the potential V _{A at} point _A is higher than the potential V B at point _B.

When the input voltage V _C is applied and the control current I _X is determined, a current flows through the transistor Q _X, and the source of Q _X
The voltage V _X between the gates is determined. The source and gate of the transistor Q _X are connected to the gates of the transistors Q ₆₁ and Q ₆₂ and the drain of Q ₆₁ (source of Q ₆₂ ), respectively. Therefore, the drain-gate voltage of the transistor Q ₆₁ and the gate-source voltage of the transistor Q ₆₂ are equal to the voltage V _X.
Will be fixed to.

Therefore, the transistor Q ₆₁ operates as a MOS diode whose gate voltage is always higher than the drain voltage by the voltage V _X. Since the voltage between the gate and the source is fixed to V _X , the transistor Q ₆₂ operates like a constant current source in which a current limited by this voltage flows. As a result, the drain-source impedance of the transistor Q ₆₁ is low and that of the Q ₆₂ is high, and the current I flowing through Q ₆₁ and Q ₆₂ is determined by the drain-source current of the transistor Q ₆₂ . After all, the current from the point A to the point B in this circuit can be made variable by the voltage V _X. Voltage V _X is controlled by the current I _X, I _X can be controlled by the control voltage V _C.

As can be seen from the above description, in the circuit of this embodiment, the characteristics of the respective transistors are made uniform so that the control current I _X and the current I flowing through Q ₆₁ and Q ₆₂ can be proportionally controlled. It is possible.

Moreover, since the circuit of this embodiment constitutes the resistance by using the transistor, there is an advantage that a large resistance value can be easily realized by changing the bias voltage thereof even with a small element area.

In the above description, the potential V _{A at the} point _A is higher than the point _B. However, even when the potential V _{B at the} point _B is higher than the point A, the transistors Q ₆₁ and Q ₆₂ are connected symmetrically. Therefore, a similar current flows from point B to point A. After all, the circuit of this embodiment exhibits the current-voltage characteristic as shown in FIG. In FIG. 6B, the vertical axis I is the current flowing through the transistors Q ₆₁ and Q ₆₂ (the direction of the current flowing from point A to point B is positive), and the horizontal axis is the potential V _{A at} points A and B. , V _{B is} the difference V. Further, FIG. 6B shows the characteristics in three cases when the control voltage V _C is changed.

Like the resistance of the passive element, the voltage controlled variable resistance circuit shown in this embodiment shows symmetrical characteristics regardless of whether the voltage between both terminals used as the resistance is positive or negative. It can be applied.

In the above embodiments, the polarities of the transistors are limited for convenience of explanation, but it goes without saying that the present invention also includes the case in which the polarities of the transistors are reversed.

FIG. 6C shows an example in which an LPF is constructed by using the circuit of this embodiment shown in FIG. 6A. As can be seen by comparing FIG. 6C with FIG. 5, in the present embodiment, the transistors R ₁ and Q ₂ are used in place of the resistor R of FIG.
Makes up F.

In addition to this, the voltage control variable resistor shown in this embodiment can be replaced with a resistor which is a conventional passive element.

FIG. 7A shows an example in which a conventional lag-advance LPF is composed of passive elements, and FIG. 7B shows the voltage control of this embodiment instead of the resistors R ₁ and R ₂ of the circuit of FIG. An example using a variable resistance circuit is shown.

In FIG. 7, Q ₇₁ and Q ₇₂ act as a resistor R ₁ , and Q ₇₃ and Q ₇₄ act as a resistor R ₂ . Each resistance value can be controlled by the current of I _x1 and I _x2 . Further, not only the LPS but also a high pass filter (HPF) can be easily used.

Further, in applications using an amplifier, the gain of the amplifier is often electronically controlled. This type of electronic gain control is particularly useful for improving the signal processing capability or dynamic range of amplifiers,
Amplifier gain is often controlled with an automatic gain control (AGC) loop. Even in such a case, the voltage controlled variable resistance circuit of this embodiment is optimal.

The LPF of the embodiment shown in FIGS.
It goes without saying that another circuit may be used as the voltage controlled variable resistance circuit in FIG.

Next, FIG. 8 shows an embodiment of a concrete circuit for realizing the frequency-voltage conversion circuit (FVC) in the embodiment shown in FIG.

The circuit of FIG. 8A is roughly divided into
(1) Circuit blocks (81 to 8) that divide a reference clock signal to obtain a signal for controlling a circuit that performs charge integration
9), (2) A circuit (90 to 92, C ₁ ) that receives the above signal and performs charge integration for a certain period, (3) A circuit (9) that samples and holds the voltage obtained as a result of charge integration.
3, C ₂ ) and (4) a buffer circuit (94) for outputting the sampled and held voltage (or the voltage is converted into a current).

In FIG. 8A, 81 is a circuit for dividing the reference clock, 82 and 85 are logic circuits for synthesizing a start signal of charge integration from the divided signal, and 83 and 86 are for dividing the end signal of charge integration. Logic circuits matched from the frequency signals, 84, 87
Is a logic circuit for synthesizing a sample Hall signal necessary for taking in a voltage resulting from charge integration from a frequency-divided signal. 8
Reference numerals 8 and 89 denote flip-flop circuits for opening and closing the gate of the integration circuit in response to the charge integration start signal and the end signal.
90 a constant current circuit for determining the slope of the voltage rise with respect to time of the charge integration, 91 and 92 gates for opening and closing the current path during the dormant period charge integration period, C ₁ is the capacitance for storing charge Is. Reference numerals 93 and C ₂ respectively denote a gate for taking in the voltage of C ₂ and a capacitor for holding the voltage.

Below, the operation of the circuit of FIG.
This will be described with reference to the signal timing chart of (b).

The reference clock signal R (frequency f _R ) is received, and frequency division is performed by a frequency dividing circuit of n stages (n is an arbitrary value: four stages here for convenience of explanation), and A, B, C,
Four types of signals, D and D, are obtained. The relationship between these signals is shown in FIG.
It is shown in (b). These reference clock signals R and A,
B, C, and D signals are input to the logic circuits 82, 83, and 84 in FIG. 8A to obtain E, F, and G signals.

Here, the E signal is a signal for giving the start of charge integration, and in the logical expression,

[0065]

[Equation 7]

It becomes

The F signal is a signal that gives the end of charge integration.
In the formula,

[0068]

[Equation 8]

It becomes

The G signal is a signal for sampling and holding the voltage of the charge integration result.

[0071]

[Equation 9]

It becomes

When this charge integration start signal F is input to the flip-flop composed of 88 and 89, the output H of the flip-flop becomes Low level, and the transistor 9
1 is on and 92 is off. Therefore, the constant current source 9
The current I ₀ starts flowing from 0, and the charging of the capacitor C ₁ is started.
The voltage value V _A of the capacitor C ₁ rises linearly with a certain slope over time. In the process of this voltage rise
A hold signal is input, the gate 93 is opened to take in the voltage to the capacitor C ₂ , and then the gate 93 is closed to keep the voltage of the capacitor C ₂ .

Next, upon receiving the charge integration end signal F, the flip-flop is inverted to turn off 91 and turn on 92. At this time, since 92 is turned on, the electric charge of the capacitor C ₁ is discharged through C ₁ and the voltage V _A becomes 0. This state is maintained until the next charge integration start signal arrives.

In this embodiment, the time position where the voltage V _A of the capacitor C ₁ is sampled and held changes in inverse proportion to the frequency, so that frequency / voltage conversion is possible. If the frequency of the reference clock signal is f _R and the time at the start of integration is 0, then the time T at which sample and hold is performed is

[0076]

[Equation 10]

It becomes Here, n is the number of stages of the frequency dividing circuit, and in the example of FIG. 8, n = 4.

On the other hand, the voltage V _A of the charge integration circuit is

[0079]

[Equation 11]

Therefore, the voltage V _A at time T is

[0081]

[Equation 12]

It becomes Since this voltage value V _A | _t = _T is sample-held, the voltage value to be sampled and held is inversely proportional to the frequency f _R of the reference clock signal R.

In this way, the circuit of this embodiment can perform frequency / voltage conversion. By adding the converted voltage to the variable time constant LPF, it is possible to automatically change the time constant of the LPF according to the frequency of the reference clock signal.

In the above description, no reference was made to the phase comparison circuit, charge pump circuit and frequency divider circuit of the embodiments shown in FIGS. 2 and 3, but these circuits are well known in the prior art. It goes without saying that it can be configured by using a circuit that has

[0085]

As described above, according to the present invention, the frequency of the internal clock signal is increased (for example, at most about 10 MHz) without increasing the frequency of the reference clock signal externally given to the integrated circuit. Therefore, there is a great effect that (for example, several tens of MHz to 100 MHz), it becomes easy to adapt to future high speed integrated circuits. Further, this has a great economical advantage that the side using the integrated circuit does not need to handle a high frequency signal, so that the cost of various parts used together with the integrated circuit can be reduced.

Further, according to the present invention, the frequency of the external reference clock signal having various frequencies different from the frequency of the internal clock signal can be selected simply by changing the setting of the frequency division number of the internal frequency dividing circuit. Since it can be done, it has an advantage that it can be easily applied to various systems by a system designer.

In addition to the above, according to the present invention, a signal synchronized with an external reference clock signal can be obtained as an internal clock signal of the integrated circuit. It has an advantage that the signal transmission can be easily synchronized.

Further, according to the present invention, there is an advantage that even if the frequency of the reference clock signal given from the outside is arbitrarily changed, the time constant required for the internal frequency doubler circuit can be automatically changed and adapted. Have Moreover, this time constant circuit
Since it can be easily configured on-chip in an integrated circuit, it has a great effect in reducing the number of external pins or the number of external parts. The ability to automatically change the time constant inside an integrated circuit means that it can be used at a slower speed when testing the integrated circuit, or at a slower speed when checking software such as micro programs in the integrated circuit. It has a great effect that it can be used without making any changes to the system for applications such as the above, or applications in which a high-frequency reference clock signal cannot be obtained and the operating speed is inevitably reduced. .

[Brief description of drawings]

FIG. 1 is an embodiment for giving a general description of the present invention.

FIG. 2 is a block diagram of a circuit according to the first embodiment.

FIG. 3 is a circuit block diagram of a second embodiment.

FIG. 4 is an example of partial circuits of the first and second examples.

FIG. 5 shows a conventional example.

FIG. 6 is an example of a partial circuit of the first and second examples.

FIG. 7A is a partial circuit diagram of a conventional example, and FIG. 7B is a partial circuit diagram of the first and second embodiments.

FIG. 8 is a partial circuit diagram of first and second embodiments.

[Explanation of symbols]

11 ... Integrated circuit, 12 ... Double frequency circuit, 13 ... Oscillation circuit, 1
5 ... Crystal oscillator, 16 ... Capacitance, 21, 26 ... Dividing circuit,
22 ... Phase comparison circuit, 23 ... Charge pump circuit, 24
... LPF, 25 ... VCO, 31, 36 ... Dividing circuit, 32
... Phase comparison circuit, 33 ... Charge pump circuit, 34 ... L
PF, 35 ... VCO, 37 ... Frequency / voltage conversion circuit, 4
1 ... Voltage / current conversion circuit, 42 ... Output buffer, Q ₄₁ ,
Q ₄₂ , Q ₄₄ , Q ₄₅ , Q ₄₈ ... PMOS transistor,
Q ₄₃ , Q ₄₆ , Q ₄₇ , Q ₄₈ ... NMOS transistor, R ...
Resistance, C ... capacitance, I _X ... constant current source, Q _X ... PMOS Ratonjisuta, Q _61, Q ₆₂ ... NMOS Tonjisuta, R _1, R ₂ ...
Resistors, I _X1 , I _X2 ... Constant current source, Q _X1 , Q _X2 ... PMOS transistors, Q _{71 to} Q ₇₄ ... NMOS transistors, 81
... Frequency divider circuit, 82-87 ... Logic gate, 88, 89 ... Flip-flop circuit, 90 ... Constant current source, 91 ... PMO
S transistor, 92 ... NMOS transistor, 93 ...
Transfer gate, 94 ... Buffer circuit, C ₁ , C ₂ ...
capacity.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshimune Hagiwara 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (3)

[Claims] 1. A constant current source controlled by voltage, a voltage generation circuit for generating a voltage proportional to the current of the constant current circuit at the first and second terminals of a three-terminal element, and operating as a MOS diode. By supplying the voltage of the voltage generation circuit to the series connection circuit, the impedance can be varied at both ends of the series connection circuit by connecting the 3-terminal element and a circuit in which the constant current operation is performed in series. Resistance circuit characterized by. 2. The resistance circuit according to claim 1, wherein, as the series connection circuit, the gates of the first conductivity type MOS transistors Q ₁ and Q ₂ are connected, and the drain of Q ₁ and the source of Q ₂ are connected. , The source of Q ₁ and the drain of Q ₂ are two terminals of the resistor, and the gates of Q ₁ and Q ₂ are of the second conductivity type MOS transistor Q ₃
Connect the source, the connection point of the source of the drain, Q ₂ of the Q ₁ is connected to the gate of Q ₃ are the voltage generating circuit, and the ground drain of the Q _3, the source of the Q ₃ are A resistance circuit in which the impedances of the resistor transistors Q ₁ and Q ₂ are made variable by connecting the constant current source and applying a control voltage to the constant power source. 3. The resistance circuit according to claim 1, wherein:
A filter circuit formed by connecting a capacitor to one end of the series connection circuit.