JPH0621999B2 - Cache memory access device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a cache memory access device for accessing a cache memory by a direct mapping and store-through method, and particularly, to improve its control method. It is a thing.

<Prior Art> FIG. 2 shows an example of a conventional device for accessing a cache memory by a direct mapping and store-through method.

In this figure, 1 is a central processing unit CP for controlling the whole.
U, 2 are a cache control unit for controlling the cache memory, 3 is a tag valid unit TV for storing the validity / invalidity of the tag unit of the address A with respect to the cache memory output from the CPU 1, and 4 is the previously accessed address A. The tag part that holds the tag of 5 is the address A given this time.
Of the tag valid unit TV3 and the output of the comparator 5 are input to the AND gate circuit G. A cache memory hit occurs when the tag valid bit TV is valid and the previous tag and the current tag are equal.

Further, for the CPU 1, when the width of the data bus DB is 32 bits, the access unit is 8 bits (byte), 16 bits (word), 24 bits, 32 bits (long word).・ Bid TV
In addition, data valid portions (DV0, DV1, DV2, DV3) indicating valid / invalid for each of the four byte data constituting 32-bit data 6, 7, 8,
9 is provided.

On the other hand, the cache control unit 2 is provided with a read / write signal R / W and a data size signal S to be accessed from the CPU 1, and the data size instruction signals M0, M1, M2, M3.
Is output. However, in this figure, each signal M0,
M1, M2 and M3 are active "L". The respective magnitude signals M0, M1, M2, M3 are given to the OR gate circuits g1, g2, g3, g4 together with the data valid signals DV0, DV1, DV2, DV3, respectively, and the OR gate circuits g1, g2, g3. , G4 are input to the AND gate circuit G.

It is to be noted that reference numerals 10, 11, 12, and 13 are data portions in which 32-bit data to be accessed is stored in units of 8 bits (1 byte).

Such a cache memory access device is effective for the tag valid bit TV, and the OR gate circuits g1, g2, g3 and g4 which determine the size of the data to be accessed by checking the previous tag match with the current tag match. The hit / miss to the cache memory is judged by the output of the AND gate circuit G to which the output value is given. And CP
U1 reads / writes the data stored in the data registers 10, 11, 12, and 13.

<Problems to be Solved by the Invention> The conventional cache memory access device described above is
Since the data valid bit is set for each byte of data to be accessed, the number of valid bids increases, the number of memory elements increases correspondingly, and the control circuit for this becomes complicated, and the data access control becomes complicated. There was a drawback that

The present invention solves this drawback, and an object of the present invention is to realize a cache memory access device with a simple configuration and high access efficiency.

<Means for Solving the Problems> The present invention uses the direct mapping and store-through method to determine the validity / invalidity of the tag portion given this time and the tag portion of the read address accessed last time and the present invention. In a cache memory access device for determining hit / miss to a cache memory by comparing with a tag part, a read / write signal from a central processing unit, a data size signal to be accessed and the hit / miss information are input. , Outputs a control signal for accessing the cache memory according to the full data width when reading data, and outputs a write instruction signal only to the main memory when the data to be written is smaller than the full data width when writing data Cache memory access device comprising an access control unit Is.

<Operation> In the cache memory access device of the present invention, when the central processing unit reads the data or program, when the data is hit, the full data width is read and only the necessary data width is read out, and when the data is missed, the miss is made. The data is read from the main memory with the full data width and written to the cache memory, and the valid bit of the tag section is validated. When the central processing unit writes data, it writes to the cache memory and the main memory with the width indicated by the central processing unit when there is a hit, and the cache memory and the main memory when the central processing unit writes with the full data width when there is a miss When writing with this width, and writing with a width smaller than the total data width, write only in the main memory.

<Embodiment> FIG. 1 is a block diagram showing a cache memory access device embodying the present invention.

In this figure, the same reference numerals as those of the conventional device shown in FIG. 2 have the same functions.

The device of the present invention is characterized in that the data valid portion provided in byte units and the OR gate circuit for determining the data size are eliminated, and the read / write signal R / W, the data size signal S and the AND gate from the CPU 1 are eliminated. Input the hit / miss signal from the circuit G and newly read / write signal R /
The access control unit 14 that outputs W and the data size signal S'is provided.

When a data read signal is given from the CPU 1, the access control section 14 outputs an access signal of the entire data width (4 bytes) regardless of the data size designated at this time, and is given a data write signal. If the data size is smaller than the total data width, the data write signal is output only to the main memory.

The device of the present invention having such an access control unit 14 operates as follows.

(A) At the time of reading data and program The CPU 1 outputs the address A, the data or program read signal R / W and the data size signal S.

When the output of the tag valid unit 3 is valid and the output of the comparator 5 is coincident (hit), the access control unit 14 determines that the CPU 1
Value of the data size signal S from 1 byte, 2 bytes, 3
(4 bytes, 4 bytes), the 4-byte access signal S'is output and main memory is not accessed, and 4-byte data or program is read from the data section 10, 11, 12, 13. CPU1 read 4
All that is necessary is to read the required amount of data in the byte data.

When the output of the tag valid unit 3 is invalid or the outputs of the comparator 5 do not match (miss), the CPU 1 determines that the access control unit 1
4 bytes of data are read from the main memory regardless of the size of the data to be accessed by 4
Write to 0, 11, 12, 13. After that, the CPU 1 validates the tag valid bit, and reads the data or program with the required data width.

In this way, when reading data or programs from the data section 10, 11, 12, 13, the access control section 1
4 always outputs the full data width signal (4 bytes) S'to assist the data read operation, and the CPU 1 reads 4
Read the required number of data bytes out of the byte data.

(B) At the time of writing data and program At the time of hit, the access control unit 14 does not function, and the read / write signal R / W and the data size signal S from the CPU 1 are output as they are, and the size of the data to be written is 4 bytes. In the case of 4 bytes, in the case of 3 bytes, it is 3 bytes, in the case of 2 bytes, it is 2 bytes, and in the case of 1 byte, it is 1 byte, and the CPU 1 writes the data in the data storage section of the main memory and the cache memory.

At the time of a miss, if the CPU 1 has a 4-byte access, the 4-byte data is written in the data storage units of the main memory and the cache memory. The size of the data to write is 1 byte,
In the case of 2 bytes and 3 bytes, the byte values other than the data to be written are undefined, so the data part 10, 11, 12, 13
Data is not written to the main memory but data is written only to the main memory according to this data size.

In this way, when reading data or programs from the cache memory, regardless of the hit / miss or the size of the data to be accessed, the data of the entire data width (4 bytes) is always accessed by the output of the access control unit. The cache memory access device can be configured with a simple configuration without providing a data valid determination unit for each byte.

<Effects of the Invention> As described above, the cache memory access device of the present invention enables / disables data that is conventionally provided for each byte.
Since valid bits that indicate invalidity are unnecessary, the number of valid bits can be increased, the number of memory elements can be reduced accordingly, and the cache memory access device can be easily configured without complicating the control circuit. Can
Access efficiency is also good.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache memory access device embodying the present invention, and FIG. 2 is a conventional cache memory access device.
It is a block diagram of an access device. 1 ... Central processing unit CPU, 2 ... Cache control unit, 3 ... Tag valid unit, 4 ... Tag unit, 5 ... Comparator, 6,7,8,9 ... Data valid unit, 10 , 11, 12, 13 ... Data section, G ... AND gate circuit, g1, g2, g3, g4 ... OR gate circuit, DB ... Data bus.

Claims (1)

[Claims] 1. A direct mapping, store-through method,
A cache memory access device that determines the validity / invalidity of the tag unit given this time and determines the hit / miss to the cache memory by comparing the tag unit of the read address accessed last time with the tag unit given this time In, a read / write signal from the central processing unit, a data size signal to be accessed and the hit / miss information are input, and a control signal for accessing the cache memory by the entire data width is output. However, the cache memory access device is provided with an access control unit that outputs a write instruction signal only to the main memory when the data to be written when writing data is smaller than the full data width.