JPH06209109A - Soi-structure mos field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a SOI structure MOSFET hardly bringing about the short channel effect having excellent controllability of channel length and capable of sufficiently coping with the further miniaturization of the MOS device. CONSTITUTION:This SOI structured MOSFET is composed of a pair of source- drain electrodes 13 formed of the first conductivity type semiconductor arranged on an insulating film 12 separated at a specific interval; the second conductivity type semiconductor layer 15 having side part and surface part electrically connected respectively to the source electrode surface part on one side as well as to the drain electrode surface part on the other side formed on the source- drain electrodes 13 and the insulating film 12 exposed by the separation as if traversing the source drain electrodes 13; a gate insulating film 16 covering the semiconductor layer 15; and a gate electrode 17 formed on the insulating film 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of an SOI structure MOS field effect transistor.

[0002]

2. Description of the Related Art A conventional SOI structure MOS field effect transistor is based on IKEDA et, al, "A Polysilicon Transistor.
Technology For Large Capacity SRAMs "IEDM 90 tec
As described in h.digest pp469-472, the source / drain electrodes and the channel electrode are in the same semiconductor silicon layer, so that only the upper surface of the semiconductor silicon has the channel length.

[0003]

Conventional SOI structure MO
In the S field effect transistor, the channel length is determined in a self-aligned manner only by the gate length, and only the upper surface of the semiconductor silicon serving as the channel electrode contributes to the channel length. There is a problem that the short channel effect occurs when the length becomes short.

Further, the fine processing precision is higher in the vertical direction by thin film deposition than in the horizontal direction by photolithography and etching, and this tendency becomes more remarkable as the processing size by photolithography and etching becomes finer. Therefore, conventionally, since the channel is used only in the lateral direction, the controllability of the channel length is not good, and there is a problem that the tendency becomes stronger as the miniaturization progresses.

Therefore, according to the present invention, the short channel effect is extremely unlikely to occur, and the controllability of the channel length is good.
It can fully support further miniaturization of devices,
An object is to provide an SOI structure MOS field effect transistor.

[0006]

An SOI structure MOS field effect transistor according to the present invention comprises a pair of sources formed of a first conductivity type semiconductor, which are arranged on an insulating film and are separated from each other by a predetermined distance. , The drain electrode and the source and drain electrodes, and the insulating film exposed by the separation so as to traverse them. On the one hand, the source electrode upper surface portion and on the other hand, the drain electrode upper surface portion is electrically connected. A semiconductor layer of the second conductivity type that is electrically connected, a gate insulating film covering the semiconductor layer, and a gate electrode formed on the gate insulating film.

Alternatively, an SOI structure MOS field effect transistor according to the present invention includes a pair of source and drain electrodes formed of a first conductivity type semiconductor and arranged on an insulating film with a predetermined distance therebetween. , The source and drain electrodes, and the insulating film exposed by the separation so as to cross them, and electrically connect to the source electrode upper surface portion on the one hand and the drain electrode upper surface portion on the other hand, respectively. The semiconductor layer has the same conductivity type as the source and drain electrodes, the gate insulating film covering the semiconductor layer, and the gate electrode formed on the gate insulating film.

In this case, it is preferable that in the SOI structure MOS field effect transistor, sidewall spacers made of an insulating material are formed on the respective side surfaces of the source and drain electrodes.

Further, in the SOI structure MOS field effect transistor, it is preferable that the source and drain electrodes are formed of tungsten polycide. In this case, the source and drain electrodes formed of the tungsten polycide are: It is preferable that the semiconductor layer is arranged on the upper part and the tungsten silicide layer is arranged on the lower part.

In the SOI structure MOS field effect transistor, the source and drain electrodes may be made of polysilicon.

Further, in the SOI structure MOS field effect transistor, the semiconductor layer may be formed of semiconductor silicon, in which case the semiconductor silicon layer is formed of CVD polysilicon or amorphous silicon. It is preferable.

Further, the thickness of the semiconductor layer is preferably several hundreds nm, and more preferably 100 nm to 700 nm.

Further, in the SOI structure MOS field effect transistor, an interlayer insulating film is formed on the gate electrode and the semiconductor layer, and a part of the interlayer insulating film is not provided under the gate electrode. If a contact hole is formed in the semiconductor layer, a part of the surface of the semiconductor layer is opened from here, and a wiring material is embedded in the contact hole to electrically connect the external wiring to the semiconductor layer.
It is also possible to control the channel potential of the OI structure MOS field effect transistor.

Furthermore, in the SOI structure MOS field effect transistor, it is preferable that the gate insulating film is formed by thermally oxidizing the semiconductor layer or by growing a CVD nitride film.

Further, in the SOI structure MOS field effect transistor, it is preferable that the gate electrode is formed of tungsten polycide or polysilicon doped with high concentration of phosphorus, arsenic or boron. .

[0016]

In the SOI structure MOS field effect transistor according to the present invention, after the source and drain electrodes are formed, the semiconductor silicon layer to be the channel electrode is separately formed on the source and drain electrodes. Since the gate electrode is covered with the gate insulating film, the vicinity of the top surface portion and the side surface portion of the semiconductor silicon layer is inverted to form a channel when a gate voltage is applied.

Further, in the SOI structure MOS field effect transistor, punch-through between the source and the drain can be avoided by forming a side wall spacer made of an insulating material on each side surface of the source and drain electrodes. .

Further, in the SOI structure MOS field effect transistor, it is preferable that the source and drain electrodes are made of tungsten polycide or polysilicon, but in the former case, each of the source and drain electrodes is formed. Forming a semiconductor layer on the upper layer portion and a tungsten silicide layer on the lower layer portion to obtain a semiconductor-semiconductor junction between the source / drain electrodes and the semiconductor silicon layer serving as the channel, and It is possible to reduce the resistance.

Further, in the SOI structure MOS field effect transistor, the semiconductor silicon layer contains a second conductivity type impurity at a concentration lower than that of the source and drain electrodes or a first conductivity type impurity. It becomes a conductive structure.

Further, in the SOI structure MOS field effect transistor, an electrode may be taken out from the semiconductor silicon layer.

Further, in the SOI structure MOS field effect transistor, by forming the semiconductor silicon layer to have a film thickness of several hundred nm, preferably 100 nm to 700 nm, highly accurate etching becomes possible. The semiconductor silicon layer is preferably formed of CVD polysilicon or amorphous silicon.

Further, in the SOI structure MOS field effect transistor, the gate insulating film is preferably formed by growing a CVD silicon nitride film or by thermally oxidizing the semiconductor silicon. The electrodes are preferably formed of tungsten polycide or polysilicon heavily doped with phosphorus, arsenic or boron.

[0023]

1 to 5 show an SOI structure M according to the present invention.
FIG. 3 is a cross-sectional view for explaining an example of an OS field effect transistor, arranged in the order of manufacturing steps. In FIG. 5, the SOI structure MOS field effect transistor according to the present invention is configured to include a source / drain electrode 13 and a semiconductor silicon layer 15 serving as a channel electrode, which are formed to be separated from each other by a predetermined distance. ing.

The source / drain electrodes 13 are formed on an insulating film 12 formed on the semiconductor silicon substrate 11. The insulating film 12 is formed by thermal oxidation of silicon of the semiconductor silicon substrate 11 or a CVD silicon oxide film. Is formed by the growth of, and its film thickness is, for example, several hundreds nm. Here, the semiconductor silicon substrate 11 is a pedestal having mechanical strength, and if the insulating substrate can be used as a substitute, the insulating film 12 need not be formed. Sidewall spacers 14 are formed on the side surfaces of the source / drain electrodes 13 to avoid punch through.

Hereinafter, the structure of the SOI structure MOS field effect transistor according to the present invention will be described in the order of steps with reference to FIGS.

First, an insulating film 12 having a thickness of, for example, several hundreds nm is formed on a semiconductor silicon substrate 11 by thermal oxidation of silicon or growth of a CVD silicon oxide film. Here, the semiconductor silicon substrate 11 is a pedestal having mechanical strength, and if the insulating substrate can be used as a substitute, the insulating film 12 need not be formed. Then, a semiconductor material such as tungsten polycide or polysilicon is deposited on the insulating film 12 by a CVD method or a sputtering method to form a semiconductor layer 13 with a thickness of 100 nm to 200 nm to obtain the structure shown in FIG. In the case of forming with polycide, in order to obtain a channel electrode and a semiconductor-semiconductor junction to be formed later and to achieve low resistance, a semiconductor portion is formed above the semiconductor layer 13 and tungsten silicide is arranged below. To do. Further, since the semiconductor layer 13 becomes the source and drain electrodes, impurities of the first conductivity type are included in a high concentration by the ion implantation or diffusion method.

Next, the semiconductor layer 13 containing impurities of the first conductivity type is processed by photolithography and etching techniques to form the source and drain electrodes 13, and silicon oxide and silicon oxide are formed on the side surfaces of the source and drain electrodes 13. The sidewall spacers 14 are formed of an insulating material such as silicon nitride to obtain the structure shown in FIG.

Next, CV is formed on the source / drain electrodes 13, the sidewall spacers 14, and the insulating film 12 exposed by the separation between the source and drain electrodes.
The second semiconductor layer 15 is formed of a semiconductor material such as D polysilicon or amorphous silicon. Impurities of the second conductivity type are contained in the second semiconductor layer 15 at a low concentration by ion implantation, and the semiconductor layer 15 is microfabricated to form the channel electrode 15 to obtain the structure shown in FIG. At this time, the thickness of the second conductivity type semiconductor layer 15 is a side surface component of the channel electrode 15, and is, for example, several hundred nm, preferably 100 nm to 7 nm.
It is 00 nm. With this structure, the side surface component of the channel electrode 15 also contributes to the channel length. here,
Both ends of the bottom surface of the channel electrode 15 are overlapped so as to be electrically connected to the top surfaces of the source and drain electrodes 13, respectively. Also here, the semiconductor layer 15
The concentration of impurities to be implanted into the wafer is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ /
It is cm ³ .

Next, the gate insulating film 16 is formed on the entire surface of the channel electrode 15 by thermal oxidation of the surface of the semiconductor layer to be the channel electrode 15 or growth of a CVD nitride film, as shown in FIG.
The structure shown in is obtained.

Next, the gate electrode 17 is formed to have a film thickness of 100 nm to several hundreds so as to cover the upper surface and the side surface of the gate insulating film 16.
It is formed of a material such as tungsten polycide or polysilicon having a high concentration doped with phosphorus, arsenic or boron so as to have a thickness of nm to obtain the structure shown in FIG.

After that, the gate electrode 17 and the semiconductor layer 15 are formed.
An interlayer insulating film 18 is formed thereon, and a contact hole 19 is formed in a part of a region where the gate electrode 17 is not provided below the interlayer insulating film 18 as shown in FIG.
A part of the surface of the above is opened from here, and the wiring material 20 such as Al is embedded in the contact hole 19 to electrically connect the external wiring and the semiconductor layer 15 to obtain the structure shown in FIG. FIG. 7 is a sectional view taken along the line AA ′ in FIG.

As another embodiment of the SOI structure MOS field effect transistor according to the present invention, the semiconductor layer 15 is used.
May contain a first conductivity type impurity having the same conductivity type as the source / drain electrodes 13.

[0033]

As described above, according to the present invention, the channel electrode is formed on the source and drain electrodes by a semiconductor layer different from them, so that not only the width of the channel electrode but also the height of the channel electrode is increased. To realize an SOI structure MOS field-effect transistor that contributes to the length and is extremely unlikely to cause a short channel effect even if the gate length is shortened, and that has a high degree of precision in microfabrication and is sufficiently compatible with miniaturization of MOS devices. You can

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a state after photolithography and etching processing after forming a first semiconductor silicon layer in a manufacturing process of an SOI structure MOS field effect transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state after the formation of the sidewall spacer and before the formation of the second semiconductor silicon layer in the manufacturing process of the SOI structure MOS field effect transistor according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a state after the formation of the second semiconductor silicon layer and before the formation of the gate insulating film in the manufacturing process of the SOI structure MOS field effect transistor according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a state after the gate insulating film is formed and before the gate electrode is formed in the manufacturing process of the SOI structure MOS field effect transistor according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a state after forming a gate electrode in a manufacturing process of an SOI structure MOS field effect transistor according to an embodiment of the present invention.

FIG. 6 is a plan view showing an SOI structure MOS field effect transistor according to an embodiment of the present invention.

FIG. 7 is a sectional view taken along line AA ′ in FIG. 6 of the SOI structure MOS field effect transistor according to the embodiment of the present invention.

[Explanation of symbols]

 12 Insulating Film 13 Semiconductor Layer Containing First Conduction Type Impurity 14 Sidewall Spacer 15 Second Conduction Type Semiconductor Layer 16 Gate Insulating Film 17 Gate Electrode 18 Interlayer Insulating Film 19 Contact Hole 20 Wiring Material

Claims (16)

[Claims] 1. A pair of source and drain electrodes formed of a first conductivity type semiconductor, which are arranged on an insulating film and spaced apart from each other by a predetermined distance, and exposed on the source and drain electrodes and by the spacing. Is formed on the insulating film that crosses them,
A second-conductivity-type semiconductor layer having a source electrode upper surface portion on the one hand, a side surface portion and an upper surface portion electrically connected to the drain electrode upper surface portion, respectively, and a gate insulating film covering the semiconductor layer. And a gate electrode formed on the gate insulating film, an SOI structure MOS field effect transistor. 2. A pair of source and drain electrodes formed of a first conductivity type semiconductor, which are arranged on an insulating film and spaced apart from each other by a predetermined distance, and exposed on the source and drain electrodes and by the spacing. Is formed on the insulating film that crosses them,
A semiconductor layer that has the same conductivity type as the source and drain electrodes and has a side surface and an upper surface that are electrically connected to the upper surface of the source electrode on the one hand and the upper surface of the drain electrode on the other side, and covers the semiconductor layer. And a gate electrode formed on the gate insulating film, an SOI structure MOS field effect transistor. 3. The SOI structure M according to claim 1 or 2.
In the OS field effect transistor, an SOI structure MOS field effect transistor characterized in that the source and drain electrodes are formed of tungsten polycide. 4. The SOI structure MOS field effect transistor according to claim 3, wherein a semiconductor silicon layer is arranged above a source / drain electrode formed of the tungsten polycide, and a tungsten silicide layer is arranged below the source / drain electrode. SOI structure MOS characterized in that
Field effect transistor. 5. The SOI structure M according to claim 1 or 2.
An SOI field effect transistor, wherein the source and drain electrodes are formed of polysilicon in the OS field effect transistor. 6. The SOI structure MO according to any one of claims 1 to 5.
In the S field effect transistor, an SOI structure MOS field effect transistor is characterized in that side wall spacers made of an insulating material are formed on respective side surfaces of the source electrode and the drain electrode. 7. The SOI structure M according to claim 1 or 2.
An SOI structure MOS field effect transistor, wherein the semiconductor layer is formed of semiconductor silicon in the OS field effect transistor. 8. The SOI structure MOS field effect transistor according to claim 7, wherein the semiconductor silicon layer is formed of polysilicon.
OI structure MOS field effect transistor. 9. The SOI structure MOS field effect transistor according to claim 7, wherein the semiconductor silicon layer is formed of amorphous silicon. 10. The SOI structure MOS field effect transistor according to claim 1, wherein an interlayer insulating film is formed on the gate electrode and the semiconductor layer, and the gate electrode is not provided under the interlayer insulating film. A contact hole is formed in a part of the interlayer insulating film of, the part of the surface of the semiconductor layer is opened from here, and wiring material is embedded in the contact hole to electrically connect the external wiring and the semiconductor layer. A characteristic SOI structure MOS field effect transistor. 11. The SO according to claim 1, 2, or 7.
An I-structure MOS field-effect transistor, wherein the semiconductor layer has a film thickness of 100 nm to 700 nm. 12. The SOI structure MOS field effect transistor according to claim 1 or 2, wherein the gate insulating film is formed by thermally oxidizing the semiconductor layer. Type transistor. 13. The SOI structure MOS field effect transistor according to claim 1, wherein the gate insulating film includes a silicon nitride film. 14. The SOI structure MOS field effect transistor according to claim 1 or 2, wherein the gate electrode is formed of tungsten polycide. 15. The SOI structure MOS field effect transistor according to claim 1 or 2, wherein the gate electrode is formed of polysilicon highly doped with phosphorus or arsenic or boron. SOI structure MOS field effect transistor. 16. The SOI structure MOS field effect transistor according to claim 1, wherein the source is
An SOI structure MOS field effect transistor, wherein a base body of an insulating layer under a drain electrode is composed of a single crystal silicon substrate.