JPH06209076A - Method for adjusting high-frequency integrated circuit device - Google Patents

Method for adjusting high-frequency integrated circuit device

Info

Publication number
JPH06209076A
JPH06209076A JP325693A JP325693A JPH06209076A JP H06209076 A JPH06209076 A JP H06209076A JP 325693 A JP325693 A JP 325693A JP 325693 A JP325693 A JP 325693A JP H06209076 A JPH06209076 A JP H06209076A
Authority
JP
Japan
Prior art keywords
transmission line
circuit
line
frequency
adjusting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP325693A
Other languages
Japanese (ja)
Inventor
Kinya Atsumi
Koichi Hoshino
Hirotane Ikeda
Yoshiki Ueno
祥樹 上野
浩一 星野
裕胤 池田
欣也 渥美
Original Assignee
Nippondenso Co Ltd
日本電装株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippondenso Co Ltd, 日本電装株式会社 filed Critical Nippondenso Co Ltd
Priority to JP325693A priority Critical patent/JPH06209076A/en
Publication of JPH06209076A publication Critical patent/JPH06209076A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a high-frequency integrated circuit device which is constituted in such a way that the precise pattern of a matching circuit, etc., formed on a substrate which cannot withstand heat and stresses can be surely trimmed and adjusted. CONSTITUTION:A high-frequency transmission line 12 composed of a thin film is formed on a substrate 11 of GaAs, etc., and a load 13 is connected to the end of the line i2. A branched transmission line 14 which is formed of a thin film and has a length L2 is branched from the line 12 at a distance L1 from the load 13. After measuring the characteristic of a circuit, a transmission line 15 for adjustment is formed on a thin film at the front end of the line 14 by the lift-off method so that the length of the line 15 from the diverging point can become L3. Since the line 15 is extended from the line 14 in such a way, the length of the line 14 can be adjusted and trimming can be performed for matching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of adjusting a high frequency integrated circuit device, which enables adjustment of the shape of a circuit for matching a load with a transmission line.

[0002]

2. Description of the Related Art Due to an increase in communication demand, there has been a demand for development of a device used for such a high frequency circuit along with a higher frequency of a communication signal frequency in a microwave band and a millimeter wave band. By the way, when the frequency is higher than the microwave, it is necessary to match the load to the signal transmission line. For example, when configuring a low noise amplifier, if the input and output of the amplifying transistor are not matched, the noise characteristics will deteriorate significantly, and matching the load to the signal transmission line is an essential issue. Has become.

Therefore, conventionally, a low noise amplifier is constructed by a hybrid IC, and a matching circuit is trimmed after the hybrid construction by means such as cutting of a wiring pattern or wire bonding according to variations in characteristics of transistors used. ing.

However, in order to increase the frequency used over millimeter waves or reduce the chip size, it is necessary to use a microwave monolithic IC. When a monolithic IC is used in this way, there is currently no suitable means for post-adjusting the matching circuit.

That is, in the case of a monolithic IC, the pattern of the matching circuit is fine, and the substrate on which the IC is monolithically mounted is composed of a semiconductor material such as GaAs which is weak against heat and stress. It is difficult to adopt a known trimming method such as laser trimming, and the yield cannot be increased.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and post-adjustment such as matching of high-frequency transmission lines and adjustment of high-frequency circuit elements can be easily performed in a wafer state. It is an object of the present invention to provide an adjusting method for a high frequency integrated circuit device, which can surely improve the yield.

[0007]

In order to achieve the above object, a method of adjusting a high frequency integrated circuit device according to the present invention forms a high frequency circuit including a thin film type high frequency circuit element in a plurality of regions of a wafer to obtain a wafer state. Then, the characteristics of the high frequency circuit are inspected, and based on the inspection result, the adjusting circuit element is connected to the high frequency circuit element to be additionally formed.

[0008]

The wafer on which the high frequency circuit is formed is subjected to the characteristic inspection of the circuit in a wafer state, and the adjusting circuit element is connected to the thin film high frequency circuit element according to the result. By the additional formation of the adjusting circuit element, the substantial high frequency circuit element is extended and formed, and the high frequency circuit is trimmed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings. FIG. 1 shows a first embodiment applied to a matching circuit based on a series reactance of a high frequency circuit formed on a GaAs substrate 11, for example. The load 13 is connected. A branch transmission line 14 having a length L2, which constitutes a part of the high frequency circuit element, is connected to the position of the length L1 from the load 13 of the transmission line 12.
An adjustment transmission line (adjustment circuit element) 15 is formed at the tip of 4 so as to have a length L3 in combination with the branch transmission line 14.

In the high-frequency matching circuit configured as described above, considering the matching method with reference to the branch point from the transmission line 12 of the branch transmission line 14 set at the distance L1 from the load 13, this branch The lengths L1 and L2 are set so that the value obtained by adding the impedances from the point to the branch transmission line 14 side and from the branch point to the load 13 side is equal to the impedance from the transmission line 12 side to the branch point. Thus, the transmission line 12 and the load 13 can be brought into a matched state. That is, the GaAs substrate 1 has the lengths L1 and L2.
A low resistance transmission line 12 and a branch transmission line 14 made of gold are formed on the substrate 1 by, for example, electrolytic plating (FIG. 2).
(A)).

By the way, the length L2 of the branch transmission line 14 is
The length L1 from the branch point to the load 13 is designed based on a method such as circuit simulation,
The transmission line 12 and the load 13 are not in a completely matched state due to a deviation from a calculated value caused by variations in the load 13 such as a transistor or a manufacturing process of the transmission line, an error due to a calculation method, and the like, and as they are, A signal may be reflected at the joint between the transmission line 12 and the load 13, which deteriorates the circuit characteristics and lowers the yield.

In the circuit device shown in this embodiment, the adjustment transmission line 15 is connected to the branch transmission line 14, and the length of the branch transmission line 14 combined with the adjustment transmission line 15 is from L2 to L3. It is extended so that the deviation from the aligned state is alleviated.

In the actual adjustment work, after the fabrication process of this high frequency circuit is completed (FIG. 2A), the circuit characteristics are measured in a wafer state, and the length of the branch transmission line 14 is L3 rather than L2. When it is determined that a better alignment condition can be obtained and performance improvement can be expected, a mask having a required extension pattern is selected from several types of masks, and after the resist pattern 16 is formed. The adjustment transmission line 15 is formed by vapor deposition or the like (FIG. 2 (B)), and the resist 16 is lifted off to form the adjustment transmission line 15 having an appropriate extension length (FIG. 2).
(C)).

For example, in the case of a high-frequency circuit formed on a semiconductor substrate such as a GaAs substrate, it is necessary to determine whether or not the adjustment transmission line 15 should be extended, or to determine how long the adjustment transmission line 15 should be formed. By performing the characteristic measurement in the state of the wafer, the elements on the entire surface of the wafer can be adjusted at the same time by measuring the characteristic of at least one element, and a great effect can be expected in shortening the adjustment process. Further, since an appropriate mask is selected from among several types of masks having adjustment transmission line forming patterns having different adjustment lengths, a better matching state can be obtained with high accuracy. Further, since the mask is selected and adjusted for each wafer, the characteristic variation due to the process variation between the wafers of the circuit elements such as the transmission line 12 and the load 13 can be absorbed, and the yield can be further improved.

In this embodiment, the length L of the branch transmission line 14 is L.
2 is extended to L3 by forming the connection of the adjustment transmission line 15, but the branch transmission line 14 is adjusted before adjustment in the wafer state.
If the matching adjustment is performed without forming the, the distance L1 from the load 13 to the branch point can be made variable, and the degree of freedom of the matching adjustment can be improved.

Further, when the element characteristics have a certain distribution on the same wafer surface, the adjusting transmission line 15 is adjusted according to the distribution.
It is also possible to give a distribution to the mask pattern so as to change the length of the mask pattern.

In the above embodiment, the example of the high frequency transmission line is shown, but this can be applied to other high frequency circuit elements. FIG. 3 shows a second embodiment applied to the inductance element of the lumped constant circuit.
0 and the adjustment transmission line 21 are formed in a spiral shape.

In such a circuit element, the inductance changes depending on the number of turns of the transmission line 20 and the adjustment transmission line 21, but the adjusting method in this embodiment is similar to that of the first embodiment. When it is desired to increase the inductance by measuring the characteristics in a wafer state after the completion of the fabrication, a mask having the shape of the adjustment transmission line 21 that can obtain the required inductance is used as a mask having several windings of the adjustment transmission line. The adjustment transmission line 21 is formed by selecting from the mask.

FIG. 4 shows a third embodiment applied to a MIM type capacitor. In this capacitive element, a lower layer transmission line 32 is formed on a substrate 31, an insulating film 33 such as silicon nitride or silicon oxide is formed on the lower layer transmission line 32, and an upper layer transmission line 34 is formed on the insulating film 33. Is formed so that the capacitance is set between the lower layer transmission line 32 and the lower layer transmission line 32.

In such a capacitive element, the capacitance is determined by the area where the lower layer transmission line 32 and the upper layer transmission line 34 overlap each other. The characteristic is measured after the circuit is manufactured, and the capacitance is greatly adjusted. If desired, as in the above-described embodiment, a mask for forming the adjustment transmission line 36 having a formation pattern of an appropriate additional area is selected from among several types of masks, and the adjustment transmission line 36 is transferred to the upper layer. It may be extended so as to be connected to the wire 34.

[0021]

As described above, according to the adjusting method of the high frequency integrated circuit device according to the present invention, the circuit element having a fine pattern can be easily trimmed and adjusted after the circuit element is manufactured. For example, even when the substrate is made of a semiconductor material which is weak in response to heat or stress, it is possible to easily trim the substrate. Therefore, for example, post-adjustment of a matching circuit of a monolithic IC can be easily performed, and a great effect is exerted in improving the yield of this kind of semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 shows a matching circuit according to a first embodiment of the present invention, (A) showing a plane pattern, and (B) showing (A).
It is a cross-sectional block diagram corresponding to the bb line of a figure.

2A to 2C are cross-sectional configuration diagrams provided for explaining an adjusting method of the matching circuit shown in FIG.

FIG. 3 is a diagram showing a plane pattern of a second embodiment applied to an inductance element of a lumped constant circuit.

4A and 4B show a third embodiment applied to a MIM type capacitive element, FIG. 4A is a diagram showing a plane pattern thereof, and FIG. 4B is a sectional configuration diagram corresponding to line bb in FIG. 4A. Is.

[Explanation of symbols]

 11 substrate 12 transmission line 14 branch transmission line 15 adjustment transmission line 20 transmission line 21 adjustment transmission line 31 substrate 32 lower layer transmission line 34 upper layer transmission line 35 adjustment transmission line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiki Ueno 1-1, Showa-cho, Kariya city, Aichi Prefecture Nihondenso Co., Ltd.

Claims (3)

[Claims]
1. A step of forming a high-frequency circuit including a thin-film high-frequency circuit element in a plurality of regions of a wafer, a step of inspecting characteristics of the high-frequency circuit in a wafer state, and the high-frequency circuit based on the inspection result. A step of additionally forming an adjusting circuit element connected to the element, the adjusting method of the high frequency integrated circuit device.
2. The adjusting circuit element forming step includes the step of selecting a mask based on the inspection result from a plurality of masks in which the adjusting circuit element shapes are different. The method for adjusting a high frequency integrated circuit device according to claim 1.
3. The method of adjusting a high frequency integrated circuit device according to claim 1, wherein the step of forming the adjusting circuit element includes a step of forming the adjusting circuit element by a lift-off method.
JP325693A 1993-01-12 1993-01-12 Method for adjusting high-frequency integrated circuit device Pending JPH06209076A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP325693A JPH06209076A (en) 1993-01-12 1993-01-12 Method for adjusting high-frequency integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP325693A JPH06209076A (en) 1993-01-12 1993-01-12 Method for adjusting high-frequency integrated circuit device

Publications (1)

Publication Number Publication Date
JPH06209076A true JPH06209076A (en) 1994-07-26

Family

ID=11552395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP325693A Pending JPH06209076A (en) 1993-01-12 1993-01-12 Method for adjusting high-frequency integrated circuit device

Country Status (1)

Country Link
JP (1) JPH06209076A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072319A (en) * 2003-08-26 2005-03-17 Mitsubishi Electric Corp Method and device for evaluating and preparing microwave integrated circuit
JP2014096642A (en) * 2012-11-07 2014-05-22 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same
JP2016182589A (en) * 2015-03-27 2016-10-20 セントラルフィルター工業株式会社 Device for generating hypochlorous acid sterile water

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072319A (en) * 2003-08-26 2005-03-17 Mitsubishi Electric Corp Method and device for evaluating and preparing microwave integrated circuit
JP2014096642A (en) * 2012-11-07 2014-05-22 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same
JP2016182589A (en) * 2015-03-27 2016-10-20 セントラルフィルター工業株式会社 Device for generating hypochlorous acid sterile water

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Effective date: 20011009