JPH06197319A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To apply the processing circuit to both the MUSE and the NTSC systems and to reduce the cost by providing coefficient devices having a coefficient group corresponding to each filter characteristic of a MUSE simple decoder and a MUSE/NTSC converter and selecting any of them with a switch. CONSTITUTION:Four line delay elements 1a-1d are provided and five vertical tap outputs T1-T5 are obtained. Coefficient devices 2a-4a, 2b-4b,... are respectively connected to the tap outputs T1-T5. The coefficient devices 2a-2e correspond to the coefficients of the MUSE simple decode system and the coefficient devices 3a-3e, 4a-4d correspond to coefficients in odd and even number field interpolation processing by the MUSE/NTSC conversion system respectively. Then changeover switches Y1-Y5 are provided corresponding to the coefficient devices 2a-4a, 2b-4b,... and the coefficient group suitable for the MUSE simple decode system or the coefficient group suitable for the MUSE/NTSC conversion system is switched to revise the characteristic of a low pass filter.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a signal processing circuit,
Especially MUSE (Multipule Sub-Nyquist sumpling encod
ing) system, and a MUSE simple decoder and MUSE / N for performing a predetermined decoding process on a signal band-compressed by the
The present invention relates to a signal processing circuit provided in a TSC converter or the like and performing a field interpolation process which is one of decoding processes.

[0002]

2. Description of the Related Art Broadcasting by a high-definition system using satellite broadcasting has been realized. However, the frequency band of signals transmitted by this high-definition system requires about two channels of satellite broadcasting by the conventional system. , MUS
The band is compressed by the E method and transmitted.

As a decoder device for decoding a signal band-compressed and transmitted by the MUSE system and converting it into a video signal of a predetermined system, only field interpolation corresponding to moving image processing in the original decoding process of the MUSE signal is performed. There is known a MUSE simple decoder that obtains a video output by using, a MUSE / NTSC converter that finally converts a MUSE signal into an NTSC video signal. Since these decoder devices are relatively small in size and inexpensive, for example, a monitor device incorporating these decoder devices or a separate decoder device connected to a monitor device compatible with the decoding method is used. By doing so, users can easily enjoy high-definition broadcasting.

By the way, in the MUSE method, a process of subsampling a predetermined pixel (sampling is performed by thinning out a predetermined pixel) is performed. As one of the decoding processes of the field interpolation process, a field interpolation process that performs an interpolation process based on the data subsampled for each field is performed. A) horizontal signal processing unit for performing signal interpolation processing and a vertical signal processing unit for performing vertical (line) signal interpolation processing.

The vertical signal processing section, together with a processing section for performing vertical interpolation processing for reproducing a high frequency signal,
It is composed of a low-pass filter that removes unnecessary noise components. For the pass band of this low pass filter,
The number of scanning lines at the time of video signal output in the MUSE simple decoder is 1125 lines / frame, whereas MUSE / NT
In the SC converter, the number of scanning lines when outputting a video signal is
Since there are 525 lines / frame, the vertical frequency bands at the time of scanning with respect to the CRT are different from each other, and thus the optimum set values are different.

Now, referring to FIGS. 2 and 3, MUSE
FIG. 2 explaining the vertical signal interpolation processing of the simple decoder.
FIG. 4 is a block diagram showing a vertical signal processing unit that performs signal processing in the vertical direction in a field interpolation processing unit of a MUSE simple decoder. I in the drawing is an input terminal, which performs a predetermined process after A / D conversion. The MUSE signal that has been subjected to is input as data. In this case, it is transmitted to the input terminal I at a rate of 16.2MH _z. Also, 1a to 1d are line delay elements, each of which is one line (1/1125 × 30
[sec]) Output the delayed signal. In this case, 4
Since it has a One line delay elements, five vertical tap outputs of T ₁ through T ₅ is obtained as shown in FIG., In which the interpolation processing is performed on the basis of the five tap outputs. Reference numerals 2a to 2e denote coefficient units as low-pass filters that remove noise components, and output to the sub-sampling processing circuit 5 by weighting the respective tap outputs with coefficients a _{1 to} c ₁ described later. The sub-sample processing circuit 5 adds the sub-sample data output from the coefficient units 2a to 2e to obtain a vertically interpolated signal, and then outputs the sub-sample processing circuit 5. The data is input through the output terminal O to a horizontal signal processing unit (not shown) that performs horizontal interpolation processing. It should be noted that Z ^{-1 to} Z ^-4 represent respective data values of the tap outputs T _{2 to} T ₅ .

FIG. 3 is an explanatory view conceptually showing vertical interpolation processing in the vertical signal processing section of the MUSE simple decoder of FIG. T _{1 to} T ₅ shown in the figure are tap outputs respectively output from the line delay elements 1a to 1d,
S _{1 to} S ₅ represent processed signals to be subjected to interpolation processing in the vertical direction. Further, a _{1 to} c ₁ in the parentheses indicate the coefficients of the coefficient units 2a to 2e. This figure, for example, to load the coefficient to be described later, respectively at the coefficient multipliers 2a~2e for each tap output T ₁ through T ₅ in the odd and even fields, the sum of these data with subsampling circuit 5 It shows that the processed signal S ₃ can be obtained by calculation.

The coefficients (filter characteristics) to be applied to the tap outputs T _{1 to} T ₅ at this time are as follows.
In the simple decoder, the number of scanning lines at the time of video output is 1125 lines / frame, that is, the number of scanning lines of the high-definition system. Therefore, assuming that the filter characteristics are vertically symmetrical, the coefficient for tap output T ₃ is As a reference, the values will be symmetrical vertically. Therefore, () in the figure
Coefficients a ₁ for the tap output T ₁ and T ₅ as shown in among the coefficients b ₁ for tap output T ₂ and T _4, for the tap output T ₃ to load the coefficients c _1.

Therefore, in the case of the vertical signal interpolation processing configuration as shown in FIG. 2, the coefficient units 2a and 2e are a ₁ and the coefficient unit 2 is
b and 2d have coefficients b ₁ and coefficient unit 2c has coefficients c ₁ to form a vertical signal processing unit. Then, the transfer function by these coefficient groups is H ₁ (Z) = a ₁ + b ₁ Z ^-1 + c ₁ when Z ^{-1 to} Z ^-4 are data values of the tap outputs T _{2 to} T ₅ , respectively. Z ⁻² + b ₁ Z ⁻³ + c ₁ Z ⁻⁴ (1) where Z ⁻¹ = exp (−sT), T = 1/33750 [se
c]. Therefore, by setting the coefficients a ₁ , b ₁ , and c ₁ in the coefficient units 2a to 2e to appropriate values, optimum filter characteristics for the MUSE simple decoder can be obtained.

Next, referring to FIGS. 4 and 5, MUSE /
The vertical signal processing of the NTSC converter will be described.
FIG. 4 is a block diagram showing a vertical signal processing unit for performing signal processing in the vertical direction in the field interpolation processing unit of the MUSE / NTSC converter.
4d is a coefficient unit, a ₂ to e ₂ represents the coefficient to be described later. Further, Y _{1 to} Y ₄ are changeover switches, and A and B indicate terminals connected to the changeover switches Y _{1 to} Y ₄ . Also in this case, the four line delay elements 1a to 1d
As it can be seen since it has, in which the interpolation processing is performed on the basis of the five vertical tap outputs of T ₁ through T _5. Note that the same parts as those in FIG.

FIG. 5 is an explanatory view conceptually showing the vertical signal processing in the vertical signal processing unit of the MUSE / NTSC converter. T _{1 to} T ₅ shown in the figure represent vertical tap outputs, and S _{1 to} S. Reference numeral ₅ indicates a processed signal to be subjected to interpolation processing in the vertical direction. A _{2 to} e _{2 in} parentheses
Indicates the coefficients of the coefficient units 3a to 3e and 4a to 4d described later.

In this figure, for example, in the odd field or the even field, each tap output T _{1 to} T ₅ is weighted with a coefficient of a predetermined value, and the sub sample processing circuit 5 calculates the sum of these data. It is shown that the processed signal S ₃ is obtained.

However, in this case, each tap output T _{1 to} T
_{This is} a coefficient for ₅ , but in the MUSE / NTSC converter, the number of scanning lines when outputting a video signal is 525 lines / frame, so the filter characteristics are asymmetric in the vertical direction.

Further, in the MUSE / NTSC converter, after the field interpolating process, from the MUSE scanning format of 1125 2: 1 interlace to the NTSC scanning format of 525 2: 1 interlace. However, in order to prevent the vertical image correlation from changing field by field at this time, the coefficient groups for the tap outputs T _{1 to} T ₅ are inverted for each even and odd field. There is a need.

That is, as shown in FIG. 5, at the time of interpolation processing in an odd field, each tap output T ₁ ,
Coefficients a ₂ , b ₂ , c for T ₂ , T ₃ , T ₄ , T _{5
If 2} , ₂ , and e ₂ are respectively weighted, the coefficient e ₂ for each tap output T ₁ , T ₂ , T ₃ , T ₄ , and T ₅ at the time of interpolation processing in an even field,
d ₂ , c ₂ , b ₂ and a ₂ are loaded respectively.

Therefore, the coefficient weighting section in the vertical signal processing section of the MUSE / NTSC converter has a coefficient unit 3a having a coefficient a ₂ and a coefficient e ₂ having a coefficient a ₂ for the tap output T ₁ , as shown in the broken line in FIG. coefficient unit 4a having the coefficient unit 4b having a coefficient multiplier 3b and the coefficient d ₂ has a coefficient b ₂ for tap output T ₂ is, coefficient unit 3c having coefficients c ₂ for tap output T ₃ However, for the tap output T ₄ , the coefficient unit 3 d having the coefficient d ₂ and the coefficient unit 4 c having the coefficient b ₂ are used, and for the tap output T ₅ , the coefficient e ₂
Is connected to the coefficient unit 3e and the coefficient unit 4d having the coefficient a ₂ .

When the vertical signal processing unit is performing the interpolation processing on the odd number field, the changeover switch units Y _{1 to} Y ₄ are interlocked to be switched to the terminal A side, while the vertical signal processing unit is even. When processing is performed on the field, the switch units Y _{1 to} Y ₄ are switched in association with the terminal B side. Further, the tap output T ₃ has a common coefficient of c ₂ regardless of whether the odd number field processing or the even field processing is performed.
The load is applied by c.

As a result, the coefficient groups to be loaded on the tap outputs T _{1 to} T ₅ are alternately switched to the corresponding settings when processing the odd field or the even field. In addition, the changeover switch unit Y ₁ to
The switching timing of Y ₄ is performed by a switching operation based on a synchronizing signal clock or the like or a control operation of a control unit (not shown).

In the transfer function of these coefficient groups, when Z ^{-1 to} Z ^-4 are used as the respective data values of the tap outputs T _{2 to} T ₅ , H _2o is used during the interpolation processing of the odd field. (Z) = a ₂ + b ₂ Z ^-1 + c ₂ Z ^-2 + d ₂ Z ^-3 + e ₂ Z ^-4 (2) where Z ^-1 = exp (-sT), T = 1/33750 [ se
c], while H _2e (Z) = e ₂ + d ₂ Z ^-1 + c ₂ Z ^-2 + b ₂ Z ^-3 + a ₂ Z ^-4 ( 3) where Z ⁻¹ = exp (−sT), T = 1/33750 [se
c]. Therefore, the coefficient units 3a to 3e
By setting the coefficients a _{2 to} e ₂ of 4a to 4d to appropriate values, optimum filter characteristics as a MUSE / NTSC converter can be obtained.

[0020]

As mentioned above, the MUS
E Simple decoder and MUSE / NTSC converter
The characteristics that the low-pass filter should have at the time of vertical signal processing, that is, the coefficient groups of each coefficient unit are different from each other.

Therefore, the MUSE simple decoder and the MUS
Since the E / NTSC converter needs to be composed of different field interpolation processing circuits, it is possible to use common parts such as an IC chip having this field interpolation processing circuit. It couldn't be done and costly.

In addition, a MUSE simple decoder and MUSE /
Even when a decoder device having both functions of the NTSC converter is configured, a field interpolation processing circuit must be provided according to the characteristics of both functions, resulting in high cost and a simple MUSE decoder and MUSE / NTSC.
Switching of functions between converters has been difficult because of the complicated circuit configuration.

[0023]

In order to solve the above problems, the present invention provides, for example, a MUSE simple decoder and a MUS.
It is an object to construct a field interpolation processing circuit applicable to both types of E / NTSC converters. Therefore, in a signal processing circuit for performing field interpolation processing, the vertical signal processing section includes a vertical signal processing section that performs at least vertical interpolation processing on a video signal band-compressed by the MUSE method. A group of coefficients for obtaining a video signal by the simple decoding method, and MUSE /
A coefficient group for obtaining a video signal by the NTSC conversion method, and a coefficient group for obtaining a video signal by the MUSE simple decoding method, or MUSE / NTSC
It is configured to have a changeover switch capable of switching and outputting to a coefficient group for obtaining a video signal by the conversion method.

The signal processing circuit configured as described above is used as a MUSE simple decoder or MUSE.
It is installed in a / NTSC converter or in a decoder device having both functions of a MUSE simple decoder and a MUSE / NTSC converter.

[0025]

[Function] A changeover switch is provided for the coefficient unit, and MUSE
Coefficient group and MUSE / NTSC suitable for simple decoding method
It is possible to use a common field interpolation processing circuit for the MUSE simple decoder and the MUSE / NTSC converter by switching the coefficient group suitable for the conversion method and changing the characteristics of the low-pass filter in the vertical signal processing unit. it can.

[0026]

FIG. 1 is a block diagram showing a vertical signal processing unit in a field interpolation processing circuit as an embodiment of the present invention. The same parts as those in FIGS. And the coefficient switching unit indicated by the broken line, which is a feature of this embodiment, will be described below.

2a to 2e and 3 shown in the coefficient switching section of FIG.
a to 3e and 4a to 4d are coefficient units, and a _{1 to} c ₁ and a _{2 to} e ₂ are coefficients of the respective coefficient units. Also, Y _{1 to} Y
₅ changeover switch, A through C denotes a terminal connected to the changeover switch Y ₁ to Y _5, the change-over switch Y ₁ ~
Y ₅ is intended to be switched in conjunction with respect to any of terminals A through C. The terminals connected to the coefficient unit 3c are common to A and B.

Also in this embodiment, FIG. 2 and FIG.
Five vertical tap outputs of T ₁ through T ₅ are obtained from having a similarly four line delay elements 1a~1d and. Then, for tap output T ₁ , coefficient units 2a, 3a, 4
a is a coefficient multiplier 2b, 2b, 4 for tap output T ₂ .
b is the coefficient multipliers 2c and 3c for the tap output T ₃ .
However, for tap output T ₄ , coefficient multipliers 2d, 3d, 4c
However, for tap output T ₅ , coefficient units 2e, 3e, 4d
Are connected respectively.

The coefficient units 2a to 2e correspond to the coefficients a _{1 to} c ₁ in the MUSE simple decoding method described with reference to FIG. That is, the coefficient units 2a and 2e have the coefficient a ₁ , the coefficient units 2b and 2d have the coefficient b ₁ , and the coefficient unit 2c has the coefficient c ₁ . On the other hand, the coefficient units 3a to 3e are the MUs described in FIG.
Corresponding to the coefficient at the time of the odd field interpolation processing by the SE / NTSC conversion method, similarly, the coefficient units 4a to 4d correspond to the coefficient at the time of the odd field interpolation processing.
That is, the coefficient units 3a, 3b and 3c (common to odd / even fields), 3d and 3e are coefficients a ₂ , b ₂ and c, respectively.
₂ , d ₂ , e ₂ and the coefficient units 4a, 4b, 4
c and 4d are configured to have coefficients e ₂ , d ₂ , b ₂ and a ₂ , respectively.

Here, a case where the field interpolation processing circuit having the vertical signal processing unit of FIG. 1 according to the present embodiment is used in a MUSE simple decoder will be described. In this case, switching of the coefficient switching unit shown by the broken line switches Y ₁ to Y ₅
Will be fixed in a state where all are switched to the terminal C. As a result, the circuit configuration is substantially the same as that of FIG. 2, so that the field interpolation processing circuit of this embodiment functions as a field interpolation processing circuit for the MUSE simple decoder.

Next, a case where the field interpolation processing circuit of this embodiment is used in a MUSE / NTSC converter will be described. In this case, the change-over switch Y ₁ to Y ₅ in the coefficient switching unit shown by the broken line, the change-over switch Y ₁ to Y ₅ is in the vertical signal processor is performing the interpolation processing for the odd fields to the terminal A The field interpolation processing circuit is configured so that the changeover switches Y _{1 to} Y ₅ can be switched to the terminal B when the even number fields are subjected to interpolation processing.

However, since the terminals connected to the coefficient unit 3c are common to A and B, the changeover switch Y ₃ is always fixedly connected to the coefficient unit 3c, and the changeover operation is performed. I don't know. This is shown in FIGS.
As described above, with respect to the tap output T ₃ , the coefficient to be weighted is set to c ₂ even in the odd field processing and the even field processing, that is, the weight processing is commonly performed by the coefficient unit 3c. By being told.

The changeover switch section Y for each field
The switching operation of _{1 to} Y ₅ is, for example, similar to the case described with reference to FIG. 4, and is controlled by the switching operation or the control unit based on the synchronizing signal or the clock.

As a result, the vertical signal processing unit in the field interpolation processing circuit of the present embodiment has a circuit configuration substantially similar to that of FIG. 4, and therefore functions as a field interpolation processing circuit of the MUSE / NTSC converter. To do.

As described above, the field interpolation processing circuit according to the present embodiment has the MUSE simple decoder and the MUSE / NTS.
It can be applied to both C converters.

Of course, the field interpolation processing circuit of the present embodiment is a MUSE simple decoder and MUSE / NTSC.
It can also be used for a decoder device having both functions of a converter.

For example, when the decoder device functions as a MUSE simple decoder, the changeover switches Y ₁ to
All Y ₅ are fixed in the state of being switched to the terminal C.
Further, when the decoder device functions as a MUSE / NTSC converter, the changeover switches Y _{1 to} Y ₅ are alternately changed over to the terminal A or the terminal B according to the interpolation processing timing for each field. The changeover operation of these changeover switches Y _{1 to} Y ₅ is configured to be performed by the control by the control unit including a microcomputer, for example.

As described above, the field interpolation processing circuit of this embodiment is provided with the MUSE simple decoder and MUSE / NTS.
When it is used for a decoder device having both functions of a C converter, both functions can be dealt with by simply changing the changeover switches Y _{1 to} Y ₅ as described above. is there. In this embodiment, vertical 5
Although the field interpolation processing is performed based on the tap output, it goes without saying that the number of tap outputs is not limited to this.

[0039]

As described above, according to the signal processing circuit of the present invention, in the vertical signal processing section of the field interpolation processing circuit, the MUSE simple decoder and the MUSE / NTSC are used.
Since a coefficient unit having a coefficient group corresponding to each filter characteristic of the converter, that is, a filter is provided and these coefficient units can be switched by a switch according to a use condition, the MUSE simple decoder and the MUSE
It can be applied to both of the / NTSC converters.

Therefore, in the case where the signal processing circuit of the present invention is formed into an IC chip, this component can be used in common, so that the cost can be reduced. . Furthermore, even when the signal processing circuit of the present invention is used in a decoder device having both functions of a MUSE simple decoder and a MUSE / NTSC converter, the filter characteristic corresponding to each function can be obtained only by the changeover operation by the changeover switch. Since it is possible to switch, it is possible to avoid complication of the circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a vertical signal processing unit of a signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a vertical signal processing unit in a simple MUSE decoder.

FIG. 3 is an explanatory diagram showing a processing operation in a vertical signal processing unit of the MUSE simple decoder.

FIG. 4 is a block diagram showing a vertical signal processing unit in a MUSE / NTSC converter.

FIG. 5 is an explanatory diagram showing a processing operation in a vertical signal processing unit of the MUSE / NTSC converter.

[Explanation of symbols]

1a~1d line delay elements 2a to 2e, 3 a to 3 e, 4 a to 4 d coefficient unit Y ₁ to Y ₅ changeover switch 5 subsampling circuit T ₁ through T ₅ tap outputs A~C terminal

Claims (4)

[Claims] 1. A signal processing circuit, comprising a vertical signal processing unit for performing at least vertical interpolation processing on a video signal band-compressed by a predetermined method, wherein the vertical signal processing unit comprises: A coefficient group for obtaining a video signal according to the first method and a coefficient group for obtaining a video signal according to the second method, and a coefficient group for obtaining a video signal according to the first method, or A signal processing circuit comprising a switching means capable of switching and outputting to a coefficient group for obtaining a video signal according to the above method. 2. The signal processing circuit according to claim 1, wherein the first method is a MUSE simple decoding method and the second method is a MUSE / NTSC conversion method. 3. The signal processing circuit according to claim 1, wherein the signal processing circuit is installed in a simple MUSE decoder or in a MUSE / NTSC converter. 4. MUSE simple decoder and MUSE / NT
The signal processing circuit according to claim 1 or 2, wherein the signal processing circuit is provided in a decoder device having both functions of an SC converter.